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Merge tag 'soc-drivers-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann: "The updates to the mediatek, allwinner, ti, tegra, microchip, stm32, samsung, imx, zynq and amlogic platoforms are fairly small maintenance changes, either addressing minor mistakes or enabling additional hardware. The qualcomm platform changes add a number of features and are larger than the other ones combined, introducing the use of linux/cleanup.h across several drivers, adding support for Snapdragon X1E and other SoCs in platform drivers, a new "protection domain mapper" driver, and a "shared memory bridge" driver. The cznic "turris omnia" router based on Marvell Armada gets a platform driver that talks to the board specific microcontroller. The reset and cache subsystems get a few minor updates to SoC specific drivers, while the ff-a, scmi and optee firmware drivers get some code refactoring and new features" * tag 'soc-drivers-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (122 commits) firmware: turris-mox-rwtm: Initialize completion before mailbox firmware: turris-mox-rwtm: Fix checking return value of wait_for_completion_timeout() firmware: turris-mox-rwtm: Do not complete if there are no waiters MAINTAINERS: drop riscv list from cache controllers platform: cznic: turris-omnia-mcu: fix Kconfig dependencies bus: sunxi-rsb: Constify struct regmap_bus soc: sunxi: sram: Constify struct regmap_config platform: cznic: turris-omnia-mcu: Depend on WATCHDOG platform: cznic: turris-omnia-mcu: Depend on OF soc: samsung: exynos-pmu: add support for PMU_ALIVE non atomic registers arm64: stm32: enable scmi regulator for stm32 firmware: qcom: tzmem: blacklist more platforms for SHM Bridge soc: qcom: wcnss: simplify with cleanup.h soc: qcom: pdr: simplify with cleanup.h soc: qcom: ocmem: simplify with cleanup.h soc: qcom: mdt_loader: simplify with cleanup.h soc: qcom: llcc: simplify with cleanup.h firmware: qcom: tzmem: simplify returning pointer without cleanup soc: qcom: socinfo: Add PM6350 PMIC arm64: dts: renesas: rz-smarc: Replace fixed regulator for USB VBUS ...
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‎Documentation/ABI/testing/sysfs-bus-i2c-devices-turris-omnia-mcu

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What: /sys/bus/i2c/devices/<mcu_device>/board_revision
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RO) Contains board revision number.
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Only available if board information is burned in the MCU (older
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revisions have board information burned in the ATSHA204-A chip).
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Format: %u.
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What: /sys/bus/i2c/devices/<mcu_device>/first_mac_address
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RO) Contains device first MAC address. Each Turris Omnia is
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allocated 3 MAC addresses. The two additional addresses are
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computed from the first one by incrementing it.
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Only available if board information is burned in the MCU (older
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revisions have board information burned in the ATSHA204-A chip).
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Format: %pM.
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What: /sys/bus/i2c/devices/<mcu_device>/front_button_mode
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RW) The front button on the Turris Omnia router can be
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configured either to change the intensity of all the LEDs on the
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front panel, or to send the press event to the CPU as an
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interrupt.
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This file switches between these two modes:
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- "mcu" makes the button press event be handled by the MCU to
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change the LEDs panel intensity.
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- "cpu" makes the button press event be handled by the CPU.
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Format: %s.
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What: /sys/bus/i2c/devices/<mcu_device>/front_button_poweron
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RW) Newer versions of the microcontroller firmware of the
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Turris Omnia router support powering off the router into true
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low power mode. The router can be powered on by pressing the
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front button.
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This file configures whether front button power on is enabled.
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This file is present only if the power off feature is supported
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by the firmware.
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Format: %i.
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What: /sys/bus/i2c/devices/<mcu_device>/fw_features
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RO) Newer versions of the microcontroller firmware report the
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features they support. These can be read from this file. If the
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MCU firmware is too old, this file reads 0x0.
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Format: 0x%x.
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What: /sys/bus/i2c/devices/<mcu_device>/fw_version_hash_application
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RO) Contains the version hash (commit hash) of the application
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part of the microcontroller firmware.
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Format: %s.
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What: /sys/bus/i2c/devices/<mcu_device>/fw_version_hash_bootloader
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RO) Contains the version hash (commit hash) of the bootloader
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part of the microcontroller firmware.
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Format: %s.
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What: /sys/bus/i2c/devices/<mcu_device>/mcu_type
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RO) Contains the microcontroller type (STM32, GD32, MKL).
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Format: %s.
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What: /sys/bus/i2c/devices/<mcu_device>/reset_selector
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RO) Contains the selected factory reset level, determined by
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how long the rear reset button was held by the user during board
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reset.
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Format: %i.
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What: /sys/bus/i2c/devices/<mcu_device>/serial_number
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Date: September 2024
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KernelVersion: 6.11
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Contact: Marek Behún <kabel@kernel.org>
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Description: (RO) Contains the 64-bit board serial number in hexadecimal
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format.
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Only available if board information is burned in the MCU (older
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revisions have board information burned in the ATSHA204-A chip).
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Format: %016X.

‎Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml

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initialized early into boot process and provides services to Operating Systems
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on multiple processors including ones running Linux.
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See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
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See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
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The TI-SCI node describes the Texas Instrument's System Controller entity node.
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This parent node may optionally have additional children nodes which describe

‎Documentation/devicetree/bindings/cache/qcom,llcc.yaml

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compatible:
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enum:
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- qcom,qdu1000-llcc
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- qcom,sa8775p-llcc
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- qcom,sc7180-llcc
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- qcom,sc7280-llcc
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- qcom,sc8180x-llcc
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- const: llcc0_base
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- const: llcc_broadcast_base
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sa8775p-llcc
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then:
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properties:
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reg:
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items:
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- description: LLCC0 base register region
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- description: LLCC1 base register region
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- description: LLCC2 base register region
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- description: LLCC3 base register region
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- description: LLCC4 base register region
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- description: LLCC5 base register region
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- description: LLCC broadcast base register region
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reg-names:
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items:
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- const: llcc0_base
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- const: llcc1_base
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- const: llcc2_base
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- const: llcc3_base
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- const: llcc4_base
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- const: llcc5_base
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- const: llcc_broadcast_base
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- if:
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properties:
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compatible:
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- qcom,sm8150-llcc
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- qcom,sm8250-llcc
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- qcom,sm8350-llcc
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then:
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properties:
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reg:
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items:
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- description: LLCC0 base register region
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- description: LLCC1 base register region
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- description: LLCC2 base register region
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- description: LLCC3 base register region
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- description: LLCC broadcast base register region
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reg-names:
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items:
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- const: llcc0_base
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- const: llcc1_base
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- const: llcc2_base
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- const: llcc3_base
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- const: llcc_broadcast_base
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-llcc
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- qcom,sm8550-llcc
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- qcom,sm8650-llcc
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then:
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properties:
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reg:
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- description: LLCC1 base register region
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- description: LLCC2 base register region
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- description: LLCC3 base register region
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- description: LLCC broadcast base register region
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- description: LLCC broadcast OR register region
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- description: LLCC broadcast AND register region
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reg-names:
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items:
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- const: llcc0_base
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- const: llcc1_base
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- const: llcc2_base
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- const: llcc3_base
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- const: llcc_broadcast_base
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- const: llcc_broadcast_and_base
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additionalProperties: false
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‎Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive StarLink Cache Controller
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maintainers:
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- Joshua Yeong <joshua.yeong@starfivetech.com>
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description:
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StarFive's StarLink Cache Controller manages the L3 cache shared between
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clusters of CPU cores. The cache driver enables RISC-V non-standard cache
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management as an alternative to instructions in the RISC-V Zicbom extension.
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allOf:
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- $ref: /schemas/cache-controller.yaml#
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# We need a select here so we don't match all nodes with 'cache'
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select:
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properties:
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compatible:
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contains:
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enum:
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- starfive,jh8100-starlink-cache
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required:
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- compatible
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properties:
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compatible:
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items:
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- const: starfive,jh8100-starlink-cache
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- const: cache
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reg:
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maxItems: 1
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- cache-block-size
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- cache-level
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- cache-sets
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- cache-size
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- cache-unified
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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cache-controller@15000000 {
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compatible = "starfive,jh8100-starlink-cache", "cache";
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reg = <0x0 0x15000000 0x0 0x278>;
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cache-block-size = <64>;
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cache-level = <3>;
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cache-sets = <8192>;
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cache-size = <0x400000>;
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cache-unified;
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};
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};

‎Documentation/devicetree/bindings/clock/ti,sci-clk.yaml

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The second cell should contain the clock ID.
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Please see http://processors.wiki.ti.com/index.php/TISCI for
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Please see https://software-dl.ti.com/tisci/esd/latest/index.html for
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protocol documentation for the values to be used for different devices.
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additionalProperties: false

‎Documentation/devicetree/bindings/firmware/arm,scmi.yaml

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- const: tx
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- const: tx_reply
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- const: rx
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- const: rx_reply
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minItems: 2
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mboxes:
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description:
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List of phandle and mailbox channel specifiers. It should contain
80-
exactly one, two or three mailboxes; the first one or two for transmitting
81-
messages ("tx") and another optional ("rx") for receiving notifications
82-
and delayed responses, if supported by the platform.
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exactly one, two, three or four mailboxes; the first one or two for
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transmitting messages ("tx") and another optional ("rx") for receiving
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notifications and delayed responses, if supported by the platform.
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The optional ("rx_reply") is for notifications completion interrupt,
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if supported by the platform.
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The number of mailboxes needed for transmitting messages depends on the
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type of channels exposed by the specific underlying mailbox controller;
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one single channel descriptor is enough if such channel is bidirectional,
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2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels
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2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels
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3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels
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4 mbox / 2 shmem => SCMI TX and RX over 4 mailbox unidirectional channels
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Any other combination of mboxes and shmem is invalid.
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minItems: 1
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maxItems: 3
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maxItems: 4
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shmem:
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description:

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