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Commit a827ad9

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Uwe Kleine-Königbroonie
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spi: stm32: Revert change that enabled controller before asserting CS
On stm32mp157 enabling the controller before asserting CS makes the hardware trigger spurious interrupts in a tight loop and the transfers fail. Revert the commit that swapped the order of enable and CS. This reintroduces the problem that swapping was supposed to fix, which however is less grave. Reported-by: Leonard Göhrs <l.goehrs@pengutronix.de> Link: https://lore.kernel.org/all/39033ed7-3e57-4339-80b4-fc8919e26aa7@pengutronix.de/ Fixes: 52b62e7 ("spi: stm32: enable controller before asserting CS") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://msgid.link/r/20240523103326.792907-2-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
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drivers/spi/spi-stm32.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1016,8 +1016,10 @@ static irqreturn_t stm32fx_spi_irq_event(int irq, void *dev_id)
10161016
static irqreturn_t stm32fx_spi_irq_thread(int irq, void *dev_id)
10171017
{
10181018
struct spi_controller *ctrl = dev_id;
1019+
struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
10191020

10201021
spi_finalize_current_transfer(ctrl);
1022+
stm32fx_spi_disable(spi);
10211023

10221024
return IRQ_HANDLED;
10231025
}
@@ -1185,8 +1187,6 @@ static int stm32_spi_prepare_msg(struct spi_controller *ctrl,
11851187
~clrb) | setb,
11861188
spi->base + spi->cfg->regs->cpol.reg);
11871189

1188-
stm32_spi_enable(spi);
1189-
11901190
spin_unlock_irqrestore(&spi->lock, flags);
11911191

11921192
return 0;
@@ -1204,6 +1204,7 @@ static void stm32fx_spi_dma_tx_cb(void *data)
12041204

12051205
if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
12061206
spi_finalize_current_transfer(spi->ctrl);
1207+
stm32fx_spi_disable(spi);
12071208
}
12081209
}
12091210

@@ -1218,6 +1219,7 @@ static void stm32_spi_dma_rx_cb(void *data)
12181219
struct stm32_spi *spi = data;
12191220

12201221
spi_finalize_current_transfer(spi->ctrl);
1222+
spi->cfg->disable(spi);
12211223
}
12221224

12231225
/**
@@ -1305,6 +1307,8 @@ static int stm32fx_spi_transfer_one_irq(struct stm32_spi *spi)
13051307

13061308
stm32_spi_set_bits(spi, STM32FX_SPI_CR2, cr2);
13071309

1310+
stm32_spi_enable(spi);
1311+
13081312
/* starting data transfer when buffer is loaded */
13091313
if (spi->tx_buf)
13101314
spi->cfg->write_tx(spi);
@@ -1341,6 +1345,8 @@ static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
13411345

13421346
spin_lock_irqsave(&spi->lock, flags);
13431347

1348+
stm32_spi_enable(spi);
1349+
13441350
/* Be sure to have data in fifo before starting data transfer */
13451351
if (spi->tx_buf)
13461352
stm32h7_spi_write_txfifo(spi);
@@ -1372,6 +1378,8 @@ static void stm32fx_spi_transfer_one_dma_start(struct stm32_spi *spi)
13721378
*/
13731379
stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_ERRIE);
13741380
}
1381+
1382+
stm32_spi_enable(spi);
13751383
}
13761384

13771385
/**
@@ -1405,6 +1413,8 @@ static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
14051413

14061414
stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
14071415

1416+
stm32_spi_enable(spi);
1417+
14081418
if (STM32_SPI_HOST_MODE(spi))
14091419
stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
14101420
}

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