Skip to content

Commit 448ac3c

Browse files
paulwalker-armAnthony Tran
paulwalker-arm
authored and
Anthony Tran
committed
[LLVM][AArch64] Relax SVE/SME codegen predicates for crypto and bitperm instructions. (llvm#145696)
Adds sve-sha3 to reference FEAT_SVE_SHA3 without specifically enabling SVE2. The SVE2 requirement for AES, SHA3 and Bitperm is replaced with SVE for non-streaming function.
1 parent ea3cc32 commit 448ac3c

37 files changed

+131
-101
lines changed

‎clang/test/CodeGen/AArch64/fmv-dependencies.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -188,7 +188,7 @@ int caller() {
188188
// CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
189189
// CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-aes,+sve2,+sve2-aes,+v8a"
190190
// CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-bitperm,+sve2,+sve2-bitperm,+v8a"
191-
// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve2,+sve2-sha3,+v8a"
191+
// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve-sha3,+sve2,+sve2-sha3,+v8a"
192192
// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sm4,+sve,+sve2,+sve2-sm4,+v8a"
193193
// CHECK: attributes #[[wfxt]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt"
194194
// CHECK: attributes #[[cssc]] = { {{.*}} "target-features"="+cssc,+fp-armv8,+neon,+outline-atomics,+v8a"

‎clang/test/Driver/aarch64-implied-sve-features.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -46,13 +46,13 @@
4646
// SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-aes" "-target-feature" "+sve2" "-target-feature" "-sve2-aes"
4747

4848
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3+nosve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3-REVERT
49-
// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3"
49+
// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-sha3" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3"
5050

5151
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4-REVERT
5252
// SVE2-SM4-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sm4"
5353

5454
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3
55-
// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3"
55+
// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve-sha3" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3"
5656

5757
// RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-AES
5858
// SVE-AES: "-target-feature" "+aes"{{.*}} "-target-feature" "+sve-aes"

‎clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@
7070
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
7171
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
7272
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
73-
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
73+
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
7474
// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
7575
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
7676
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

‎clang/test/Driver/print-enabled-extensions/aarch64-grace.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@
5454
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
5555
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
5656
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
57-
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
57+
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
5858
// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
5959
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
6060
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

‎clang/test/Driver/print-enabled-extensions/aarch64-olympus.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@
7070
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
7171
// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
7272
// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
73-
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
73+
// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions
7474
// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
7575
// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
7676
// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

‎clang/test/Driver/print-supported-extensions-aarch64.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,10 +92,11 @@
9292
// CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions
9393
// CHECK-NEXT: sve-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
9494
// CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply
95+
// CHECK-NEXT: sve-sha3 FEAT_SVE_SHA3 Enable SVE SHA3 instructions
9596
// CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
9697
// CHECK-NEXT: sve2-aes Shorthand for +sve2+sve-aes
9798
// CHECK-NEXT: sve2-bitperm Shorthand for +sve2+sve-bitperm
98-
// CHECK-NEXT: sve2-sha3 FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
99+
// CHECK-NEXT: sve2-sha3 Shorthand for +sve2+sve-sha3
99100
// CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4 Enable SM4 SVE2 instructions
100101
// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
101102
// CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ def SVE2p1Unsupported : AArch64Unsupported;
6363

6464
def SVE2Unsupported : AArch64Unsupported {
6565
let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
66-
HasSMEF8F32, HasSVEAES, HasSVE2SHA3, HasSVE2SM4, HasSVEBitPerm,
66+
HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVE2SM4, HasSVEBitPerm,
6767
HasSVEB16B16],
6868
SVE2p1Unsupported.F);
6969
}
@@ -80,14 +80,14 @@ def SME2p2Unsupported : AArch64Unsupported;
8080
def SME2p1Unsupported : AArch64Unsupported {
8181
let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1,
8282
HasSME_MOP4, HasSME_TMOP, HasNonStreamingSVE_or_SSVE_FEXPA,
83-
HasNonStreamingSVE2_or_SSVE_BitPerm],
83+
HasNonStreamingSVE_or_SSVE_BitPerm],
8484
SME2p2Unsupported.F);
8585
}
8686

8787
def SME2Unsupported : AArch64Unsupported {
8888
let F = !listconcat([HasSME2, HasSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
8989
HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16,
90-
HasNonStreamingSVE2_or_SSVE_AES],
90+
HasNonStreamingSVE_or_SSVE_AES],
9191
SME2p1Unsupported.F);
9292
}
9393

‎llvm/lib/Target/AArch64/AArch64Features.td

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -373,8 +373,11 @@ def FeatureAliasSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
373373
def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
374374
"Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
375375

376-
def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3", "FEAT_SVE_SHA3",
377-
"Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
376+
def FeatureSVESHA3 : ExtensionWithMArch<"sve-sha3", "SVESHA3", "FEAT_SVE_SHA3",
377+
"Enable SVE SHA3 instructions", [FeatureSHA3]>;
378+
379+
def FeatureAliasSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3",
380+
"", "Shorthand for +sve2+sve-sha3", [FeatureSVE2, FeatureSVESHA3]>;
378381

379382
def FeatureSVEBitPerm : ExtensionWithMArch<"sve-bitperm", "SVEBitPerm",
380383
"FEAT_SVE_BitPerm", "Enable bit permutation SVE2 instructions">;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 17 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -153,8 +153,8 @@ def HasSVEAES : Predicate<"Subtarget->hasSVEAES()">,
153153
AssemblerPredicateWithAll<(all_of FeatureSVEAES), "sve-aes">;
154154
def HasSVE2SM4 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SM4()">,
155155
AssemblerPredicateWithAll<(all_of FeatureSVE2SM4), "sve2-sm4">;
156-
def HasSVE2SHA3 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SHA3()">,
157-
AssemblerPredicateWithAll<(all_of FeatureSVE2SHA3), "sve2-sha3">;
156+
def HasSVESHA3 : Predicate<"Subtarget->hasSVESHA3()">,
157+
AssemblerPredicateWithAll<(all_of FeatureSVESHA3), "sve-sha3">;
158158
def HasSVEBitPerm : Predicate<"Subtarget->hasSVEBitPerm()">,
159159
AssemblerPredicateWithAll<(all_of FeatureSVEBitPerm), "sve-bitperm">;
160160
def HasSMEandIsNonStreamingSafe
@@ -248,11 +248,26 @@ def HasSVE_or_SME
248248
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable()">,
249249
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
250250
"sve or sme">;
251+
def HasNonStreamingSVE_or_SME2p1
252+
: Predicate<"Subtarget->isSVEAvailable() ||"
253+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p1())">,
254+
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p1),
255+
"sve or sme2p1">;
251256
def HasNonStreamingSVE_or_SME2p2
252257
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
253258
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
254259
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2),
255260
"sve or sme2p2">;
261+
def HasNonStreamingSVE_or_SSVE_AES
262+
: Predicate<"Subtarget->isSVEAvailable() ||"
263+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,
264+
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_AES),
265+
"sve or ssve-aes">;
266+
def HasNonStreamingSVE_or_SSVE_BitPerm
267+
: Predicate<"Subtarget->isSVEAvailable() ||"
268+
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">,
269+
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_BitPerm),
270+
"sve or ssve-bitperm">;
256271
def HasNonStreamingSVE_or_SSVE_FEXPA
257272
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
258273
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA())">,
@@ -267,11 +282,6 @@ def HasSVE2_or_SME2
267282
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
268283
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME2),
269284
"sve2 or sme2">;
270-
def HasNonStreamingSVE2_or_SSVE_AES
271-
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
272-
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">,
273-
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_AES),
274-
"sve2 or ssve-aes">;
275285

276286
def HasSVE2p1_or_SME
277287
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
@@ -300,11 +310,6 @@ def HasSMEF16F16_or_SMEF8F16
300310
: Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">,
301311
AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16),
302312
"sme-f16f16 or sme-f8f16">;
303-
def HasNonStreamingSVE2_or_SSVE_BitPerm
304-
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
305-
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">,
306-
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_BitPerm),
307-
"sve2 or ssve-bitperm">;
308313

309314
// A subset of NEON instructions are legal in Streaming SVE execution mode,
310315
// so don't need the additional check for 'isNeonAvailable'.

‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -897,7 +897,7 @@ def ProcessorFeatures {
897897
FeatureFPAC, FeatureFP16FML, FeatureRandGen,
898898
FeatureSSBS, FeatureLS64, FeatureCLRBHB,
899899
FeatureSPECRES2, FeatureSVEAES, FeatureSVE2SM4,
900-
FeatureSVE2SHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE,
900+
FeatureSVESHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE,
901901
FeatureMEC, FeatureFAMINMAX, FeatureFP8DOT2, FeatureFP8DOT4,
902902
FeatureFP8FMA, FeatureLUT];
903903
list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES,
@@ -910,7 +910,7 @@ def ProcessorFeatures {
910910
FeatureLS64, FeatureLUT, FeatureMEC,
911911
FeatureMTE, FeaturePerfMon, FeatureRandGen,
912912
FeatureSPE, FeatureSPE_EEF, FeatureSSBS,
913-
FeatureSVEBitPerm, FeatureSVE2SHA3,
913+
FeatureSVEBitPerm, FeatureSVESHA3,
914914
FeatureSVE2SM4, FeatureSVEAES];
915915
list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
916916
FeatureNEON,FeaturePerfMon];
@@ -1107,7 +1107,7 @@ def ProcessorFeatures {
11071107
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
11081108
FeatureSSBS, FeatureCCIDX,
11091109
FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
1110-
list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVE2SHA3]);
1110+
list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVESHA3]);
11111111

11121112
// ETE and TRBE are future architecture extensions. We temporarily enable them
11131113
// by default for users targeting generic AArch64. The extensions do not

0 commit comments

Comments
 (0)