You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
This adds support for ADAQ7767/68/69-1 series, which includes PGIA and
AAF gains, configurable through devicetree.
It also fixes sampling frequency calculation, sync pulse using registers
and data acquisition with iio.
the driver now can work in low-latency mode. In low-latency mode the filter
type is fixed in Sinc5 Dec8 and ADC data width is set to 16 bits to reach
maximum sample rate. When disabled, the ADC data is 24 bits and it is
possible to change between filters in runtime (except for Sinc5 Dec8).
Signed-off-by: jonathanns <Jonathan.Santos@analog.com>
0 commit comments