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iio: adc: ad4170-4: Add support for buffered data capture
Extend the AD4170-4 driver to allow buffered data capture in continuous read mode. In continuous read mode, the chip skips the instruction phase and outputs just ADC sample data, enabling faster sample rates to be reached. The internal channel sequencer always starts sampling from channel 0 and channel 0 must be enabled if more than one channel is selected for data capture. The scan mask validation callback checks if the aforementioned condition is met. Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com> Link: https://patch.msgid.link/10ed544d31aa86eb40f93ea947f151d3d9827952.1751895245.git.marcelo.schmitt@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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‎drivers/iio/adc/Kconfig

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,8 @@ config AD4170_4
8989
tristate "Analog Device AD4170-4 ADC Driver"
9090
depends on SPI
9191
select REGMAP_SPI
92+
select IIO_BUFFER
93+
select IIO_TRIGGERED_BUFFER
9294
help
9395
Say yes here to build support for Analog Devices AD4170-4 SPI analog
9496
to digital converters (ADC).

‎drivers/iio/adc/ad4170-4.c

Lines changed: 215 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,11 @@
1616
#include <linux/delay.h>
1717
#include <linux/device.h>
1818
#include <linux/err.h>
19+
#include <linux/iio/buffer.h>
1920
#include <linux/iio/iio.h>
21+
#include <linux/iio/trigger.h>
22+
#include <linux/iio/trigger_consumer.h>
23+
#include <linux/iio/triggered_buffer.h>
2024
#include <linux/interrupt.h>
2125
#include <linux/irq.h>
2226
#include <linux/math64.h>
@@ -61,6 +65,7 @@
6165
#define AD4170_FILTER_FS_REG(x) (0xC7 + 14 * (x))
6266
#define AD4170_OFFSET_REG(x) (0xCA + 14 * (x))
6367
#define AD4170_GAIN_REG(x) (0xCD + 14 * (x))
68+
#define AD4170_ADC_CTRL_CONT_READ_EXIT_REG 0x200 /* virtual reg */
6469

6570
#define AD4170_REG_READ_MASK BIT(14)
6671

@@ -72,6 +77,7 @@
7277

7378
/* AD4170_ADC_CTRL_REG */
7479
#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7)
80+
#define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4)
7581
#define AD4170_ADC_CTRL_MODE_MSK GENMASK(3, 0)
7682

7783
/* AD4170_CHAN_EN_REG */
@@ -116,9 +122,13 @@
116122
#define AD4170_PIN_MUXING_DIG_AUX1_RDY 0x1
117123

118124
/* AD4170_ADC_CTRL_REG constants */
125+
#define AD4170_ADC_CTRL_MODE_CONT 0x0
119126
#define AD4170_ADC_CTRL_MODE_SINGLE 0x4
120127
#define AD4170_ADC_CTRL_MODE_IDLE 0x7
121128

129+
#define AD4170_ADC_CTRL_CONT_READ_DISABLE 0x0
130+
#define AD4170_ADC_CTRL_CONT_READ_ENABLE 0x1
131+
122132
/* AD4170_FILTER_REG constants */
123133
#define AD4170_FILTER_FILTER_TYPE_SINC5_AVG 0x0
124134
#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4
@@ -150,6 +160,8 @@
150160

151161
#define AD4170_GAIN_REG_DEFAULT 0x555555
152162

163+
#define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5
164+
153165
static const unsigned int ad4170_reg_size[] = {
154166
[AD4170_CONFIG_A_REG] = 1,
155167
[AD4170_DATA_24B_REG] = 3,
@@ -186,6 +198,7 @@ static const unsigned int ad4170_reg_size[] = {
186198
[AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3,
187199
[AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3,
188200
[AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3,
201+
[AD4170_ADC_CTRL_CONT_READ_EXIT_REG] = 0,
189202
};
190203

191204
enum ad4170_ref_buf {
@@ -325,6 +338,10 @@ struct ad4170_state {
325338
struct spi_device *spi;
326339
struct regmap *regmap;
327340
int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2];
341+
__be32 bounce_buffer[AD4170_MAX_ADC_CHANNELS];
342+
struct spi_message msg;
343+
struct spi_transfer xfer;
344+
struct iio_trigger *trig;
328345
unsigned int pins_fn[AD4170_NUM_ANALOG_PINS];
329346
/*
330347
* DMA (thus cache coherency maintenance) requires the transfer buffers
@@ -410,6 +427,10 @@ static int ad4170_reg_write(void *context, unsigned int reg, unsigned int val)
410427
case 1:
411428
tx_buf[AD4170_SPI_INST_PHASE_LEN] = val;
412429
break;
430+
case 0:
431+
/* Write continuous read exit code */
432+
tx_buf[0] = AD4170_ADC_CTRL_CONT_READ_EXIT;
433+
return spi_write_then_read(st->spi, tx_buf, 1, NULL, 0);
413434
default:
414435
return -EINVAL;
415436
}
@@ -803,6 +824,7 @@ static const struct iio_chan_spec ad4170_channel_template = {
803824
.scan_type = {
804825
.realbits = 24,
805826
.storagebits = 32,
827+
.shift = 8,
806828
.endianness = IIO_BE,
807829
},
808830
};
@@ -1392,11 +1414,27 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,
13921414
}
13931415
}
13941416

1417+
static int ad4170_update_scan_mode(struct iio_dev *indio_dev,
1418+
const unsigned long *active_scan_mask)
1419+
{
1420+
struct ad4170_state *st = iio_priv(indio_dev);
1421+
unsigned int chan_index;
1422+
int ret;
1423+
1424+
iio_for_each_active_channel(indio_dev, chan_index) {
1425+
ret = ad4170_set_channel_enable(st, chan_index, true);
1426+
if (ret)
1427+
return ret;
1428+
}
1429+
return 0;
1430+
}
1431+
13951432
static const struct iio_info ad4170_info = {
13961433
.read_raw = ad4170_read_raw,
13971434
.read_avail = ad4170_read_avail,
13981435
.write_raw = ad4170_write_raw,
13991436
.write_raw_get_fmt = ad4170_write_raw_get_fmt,
1437+
.update_scan_mode = ad4170_update_scan_mode,
14001438
.debugfs_reg_access = ad4170_debugfs_reg_access,
14011439
};
14021440

@@ -1700,16 +1738,178 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)
17001738
AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK);
17011739
}
17021740

1741+
static int ad4170_prepare_spi_message(struct ad4170_state *st)
1742+
{
1743+
/*
1744+
* Continuous data register read is enabled on buffer postenable so
1745+
* no instruction phase is needed meaning we don't need to send the
1746+
* register address to read data. Transfer only needs the read buffer.
1747+
*/
1748+
st->xfer.rx_buf = &st->rx_buf;
1749+
st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.realbits);
1750+
1751+
spi_message_init_with_transfers(&st->msg, &st->xfer, 1);
1752+
1753+
return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->msg);
1754+
}
1755+
1756+
static int ad4170_buffer_postenable(struct iio_dev *indio_dev)
1757+
{
1758+
struct ad4170_state *st = iio_priv(indio_dev);
1759+
int ret;
1760+
1761+
ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
1762+
AD4170_ADC_CTRL_MODE_MSK,
1763+
FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
1764+
AD4170_ADC_CTRL_MODE_CONT));
1765+
if (ret)
1766+
return ret;
1767+
1768+
/*
1769+
* This enables continuous read of the ADC data register. The ADC must
1770+
* be in continuous conversion mode.
1771+
*/
1772+
return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
1773+
AD4170_ADC_CTRL_CONT_READ_MSK,
1774+
FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
1775+
AD4170_ADC_CTRL_CONT_READ_ENABLE));
1776+
}
1777+
1778+
static int ad4170_buffer_predisable(struct iio_dev *indio_dev)
1779+
{
1780+
struct ad4170_state *st = iio_priv(indio_dev);
1781+
unsigned int i;
1782+
int ret;
1783+
1784+
/*
1785+
* Use a high register address (virtual register) to request a write of
1786+
* 0xA5 to the ADC during the first 8 SCLKs of the ADC data read cycle,
1787+
* thus exiting continuous read.
1788+
*/
1789+
ret = regmap_write(st->regmap, AD4170_ADC_CTRL_CONT_READ_EXIT_REG, 0);
1790+
if (ret)
1791+
return ret;
1792+
1793+
ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
1794+
AD4170_ADC_CTRL_CONT_READ_MSK,
1795+
FIELD_PREP(AD4170_ADC_CTRL_CONT_READ_MSK,
1796+
AD4170_ADC_CTRL_CONT_READ_DISABLE));
1797+
if (ret)
1798+
return ret;
1799+
1800+
ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
1801+
AD4170_ADC_CTRL_MODE_MSK,
1802+
FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
1803+
AD4170_ADC_CTRL_MODE_IDLE));
1804+
if (ret)
1805+
return ret;
1806+
1807+
/*
1808+
* The ADC sequences through all the enabled channels (see datasheet
1809+
* page 95). That can lead to incorrect channel being read if a
1810+
* single-shot read (or buffered read with different active_scan_mask)
1811+
* is done after buffer disable. Disable all channels so only requested
1812+
* channels will be read.
1813+
*/
1814+
for (i = 0; i < indio_dev->num_channels; i++) {
1815+
ret = ad4170_set_channel_enable(st, i, false);
1816+
if (ret)
1817+
return ret;
1818+
}
1819+
1820+
return 0;
1821+
}
1822+
1823+
static bool ad4170_validate_scan_mask(struct iio_dev *indio_dev,
1824+
const unsigned long *scan_mask)
1825+
{
1826+
unsigned int masklength = iio_get_masklength(indio_dev);
1827+
unsigned int enabled;
1828+
1829+
/*
1830+
* The channel sequencer cycles through the enabled channels in
1831+
* sequential order, from channel 0 to channel 15, bypassing disabled
1832+
* channels. When more than one channel is enabled, channel 0 must
1833+
* always be enabled. See datasheet channel_en register description at
1834+
* page 95.
1835+
*/
1836+
enabled = bitmap_weight(scan_mask, masklength);
1837+
if (enabled > 1)
1838+
return test_bit(0, scan_mask);
1839+
1840+
return enabled == 1;
1841+
}
1842+
1843+
static const struct iio_buffer_setup_ops ad4170_buffer_ops = {
1844+
.postenable = ad4170_buffer_postenable,
1845+
.predisable = ad4170_buffer_predisable,
1846+
.validate_scan_mask = ad4170_validate_scan_mask,
1847+
};
1848+
1849+
static irqreturn_t ad4170_trigger_handler(int irq, void *p)
1850+
{
1851+
struct iio_poll_func *pf = p;
1852+
struct iio_dev *indio_dev = pf->indio_dev;
1853+
struct ad4170_state *st = iio_priv(indio_dev);
1854+
unsigned int chan_index;
1855+
unsigned int i = 0;
1856+
int ret;
1857+
1858+
iio_for_each_active_channel(indio_dev, chan_index) {
1859+
ret = spi_sync(st->spi, &st->msg);
1860+
if (ret)
1861+
goto err_out;
1862+
1863+
memcpy(&st->bounce_buffer[i++], st->rx_buf, ARRAY_SIZE(st->rx_buf));
1864+
}
1865+
1866+
iio_push_to_buffers(indio_dev, st->bounce_buffer);
1867+
err_out:
1868+
iio_trigger_notify_done(indio_dev->trig);
1869+
return IRQ_HANDLED;
1870+
}
1871+
1872+
static const struct iio_trigger_ops ad4170_trigger_ops = {
1873+
.validate_device = iio_trigger_validate_own_device,
1874+
};
1875+
17031876
static irqreturn_t ad4170_irq_handler(int irq, void *dev_id)
17041877
{
17051878
struct iio_dev *indio_dev = dev_id;
17061879
struct ad4170_state *st = iio_priv(indio_dev);
17071880

1708-
complete(&st->completion);
1881+
if (iio_buffer_enabled(indio_dev))
1882+
iio_trigger_poll(st->trig);
1883+
else
1884+
complete(&st->completion);
17091885

17101886
return IRQ_HANDLED;
17111887
};
17121888

1889+
static int ad4170_trigger_setup(struct iio_dev *indio_dev)
1890+
{
1891+
struct ad4170_state *st = iio_priv(indio_dev);
1892+
struct device *dev = &st->spi->dev;
1893+
int ret;
1894+
1895+
st->trig = devm_iio_trigger_alloc(dev, "%s-trig%d",
1896+
indio_dev->name,
1897+
iio_device_id(indio_dev));
1898+
if (!st->trig)
1899+
return -ENOMEM;
1900+
1901+
st->trig->ops = &ad4170_trigger_ops;
1902+
1903+
iio_trigger_set_drvdata(st->trig, indio_dev);
1904+
ret = devm_iio_trigger_register(dev, st->trig);
1905+
if (ret)
1906+
return dev_err_probe(dev, ret, "Failed to register trigger\n");
1907+
1908+
indio_dev->trig = iio_trigger_get(st->trig);
1909+
1910+
return 0;
1911+
}
1912+
17131913
static int ad4170_regulator_setup(struct ad4170_state *st)
17141914
{
17151915
struct device *dev = &st->spi->dev;
@@ -1834,8 +2034,22 @@ static int ad4170_probe(struct spi_device *spi)
18342034
IRQF_ONESHOT, indio_dev->name, indio_dev);
18352035
if (ret)
18362036
return ret;
2037+
2038+
ret = ad4170_trigger_setup(indio_dev);
2039+
if (ret)
2040+
return ret;
18372041
}
18382042

2043+
ret = ad4170_prepare_spi_message(st);
2044+
if (ret)
2045+
return dev_err_probe(dev, ret, "Failed to prepare SPI message\n");
2046+
2047+
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
2048+
&ad4170_trigger_handler,
2049+
&ad4170_buffer_ops);
2050+
if (ret)
2051+
return dev_err_probe(dev, ret, "Failed to setup read buffer\n");
2052+
18392053
return devm_iio_device_register(dev, indio_dev);
18402054
}
18412055

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