pwm: axi-pwmgen: Improve precision in .get_state()

axi_pwmgen_get_state() does an integer division first and then
multiplies the result. This way the possible error of the result is the
error of the division (i.e. 0.5) multiplied by the other factor.

With a typical clk_rate of 166666665 Hz the error isn't that visible
because AXI_PWMGEN_PSEC_PER_SEC / rate is nearly integer. But even then
it's visible for big register values: With AXI_PWMGEN_CHX_PERIOD =
0xffffffff we get:

	clk_period_ps = 6000; /* exact value: 6000.00006 */
	state->period = 25769803770;

The exact value is 25769804027.69804 which corresponds to an absolute
error of approximately 257.7 ns. With other rates, the error is
considerably worse (consider rate = 176102844 Hz, with the same value of
AXI_PWMGEN_CHX_PERIOD the absolute error is approx. 2147475 ns)

Improve precision by doing the multiplication first and only divide
then. In the above examples the error is reduced to less than 1.

As a side effect the number of divisions is reduced from four to three
which probably even improves run time.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>

Author: ukleinek

drivers/pwm/pwm-axi-pwmgen.c

@@ -129,32 +129,21 @@ static void axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
 {
 	struct axi_pwmgen *pwmgen = to_axi_pwmgen(chip);
 	unsigned long rate;
-	unsigned long long cnt, clk_period_ps;
+	unsigned long long cnt;
 	unsigned int ch = pwm->hwpwm;
 
 	rate = clk_get_rate(pwmgen->clk);
 	if (!rate)
 		return;
 
-	clk_period_ps = DIV_ROUND_CLOSEST_ULL(AXI_PWMGEN_PSEC_PER_SEC, rate);
 	cnt = axi_pwmgen_read(pwmgen, AXI_PWMGEN_CHX_PERIOD(pwmgen, ch));
-	cnt *= clk_period_ps;
-	if (cnt)
-		state->period = DIV_ROUND_CLOSEST_ULL(cnt, PSEC_PER_NSEC);
-	else
-		state->period = 0;
+	state->period = DIV_ROUND_CLOSEST_ULL(cnt * NSEC_PER_SEC, rate);
+
 	cnt = axi_pwmgen_read(pwmgen, AXI_PWMGEN_CHX_DUTY(pwmgen, ch));
-	cnt *= clk_period_ps;
-	if (cnt)
-		state->duty_cycle = DIV_ROUND_CLOSEST_ULL(cnt, PSEC_PER_NSEC);
-	else
-		state->duty_cycle = 0;
+	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(cnt * NSEC_PER_SEC, rate);
+
 	cnt = axi_pwmgen_read(pwmgen, AXI_PWMGEN_CHX_PHASE(pwmgen, ch));
-	cnt *= clk_period_ps;
-	if (cnt)
-		state->phase = DIV_ROUND_CLOSEST_ULL(cnt, PSEC_PER_NSEC);
-	else
-		state->phase = 0;
+	state->phase = DIV_ROUND_CLOSEST_ULL(cnt * NSEC_PER_SEC, rate);
 
 	state->enabled = state->period > 0;
 	state->time_unit = PWM_UNIT_NSEC;