Merge tag 'xilinx-v2024.2' of https://github.com/Xilinx/linux-xlnx.git

This is the 2024.2 merge. Clean and with no conflicts.

Author: nunojsa

Documentation/ABI/testing/sysfs-bus-platform-onboard-usb-hub renamed to Documentation/ABI/testing/sysfs-bus-platform-onboard-usb-dev

@@ -5,4 +5,5 @@ Contact:	Matthias Kaehlcke <matthias@kaehlcke.net>
 		linux-usb@vger.kernel.org
 Description:
 		(RW) Controls whether the USB hub remains always powered
-		during system suspend or not.
+		during system suspend or not. This attribute is not
+		available for non-hub devices.

Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt

@@ -0,0 +1,156 @@
+Binding for IDT 8T49N24x Universal Frequency Translator
+
+The 8T49N241 has one fractional-feedback PLL that can be used as a
+jitter attenuator and frequency translator. It is equipped with one
+integer and three fractional output dividers, allowing the generation
+of up to four different output frequencies, ranging from 8kHz to 1GHz.
+These frequencies are completely independent of each other, the input
+reference frequencies and the crystal reference frequency. The device
+places virtually no constraints on input to output frequency conversion,
+supporting all FEC rates, including the new revision of ITU-T
+Recommendation G.709 (2009), most with 0ppm conversion error.
+The outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels.
+
+The driver can read a full register map from the DT, and will use that
+register map to initialize the attached part (via I2C) when the system
+boots. Any configuration not supported by the common clock framework
+must be done via the full register map, including optimized settings.
+
+The 8T49N241 accepts up to two differential or single-ended input clocks
+and a fundamental-mode crystal input. The internal PLL can lock to either
+of the input reference clocks or just to the crystal to behave as a
+frequency synthesizer. The PLL can use the second input for redundant
+backup of the primary input reference, but in this case, both input clock
+references must be related in frequency.
+
+All outputs are currently assumed to be LVDS, unless overridden in the
+full register map in the DT.
+
+==I2C device node==
+
+Required properties:
+- compatible:	shall be one of "idt,idt8t49n241"
+- reg:		i2c device address, shall be one of 0x7C, 0x6C, 0x7D, 0x6D,
+		0x7E, 0x6E, 0x7F, 0x6F.
+- #clock-cells: From common clock bindings: Shall be 1.
+
+- clocks:	from common clock binding; input clock handle. Required.
+- clock-names:	from common clock binding; clock input names, shall be
+		one of "input-clk0", "input-clk1", "input-xtal". Required.
+
+==Mapping between clock specifier and physical pins==
+
+When referencing the provided clock in the DT using phandle and
+clock specifier, the following mapping applies:
+
+8T49N241:
+	0 -- Q0
+	1 -- Q1
+	2 -- Q2
+	3 -- Q3
+
+==Example==
+
+/* Example1: 25MHz input clock (via CLK0) */
+
+ref25: ref25m {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <25000000>;
+};
+
+i2c-master-node {
+
+	/* IDT 8T49N241 i2c universal frequency translator */
+	i2c241: clock-generator@6a {
+		compatible = "idt,idt8t49n241";
+		reg = <0x6c>;
+		#clock-cells = <1>;
+
+		/* Connect input-clk0 to 25MHz reference */
+		clocks = <&ref25m>;
+		clock-names = "input-clk0";
+	};
+};
+
+/* Consumer referencing the 8T49N241 pin Q1 */
+consumer {
+	...
+	clocks = <&i2c241 1>;
+	...
+}
+
+/* Example2: 40MHz xtal frequency, specify all settings */
+
+ref40: ref40m {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <40000000>;
+};
+
+i2c-master-node {
+
+	/* IDT 8T49N241 i2c universal frequency translator */
+	i2c241: clock-generator@6a {
+		compatible = "idt,idt8t49n241";
+		reg = <0x6c>;
+		#clock-cells = <1>;
+
+		/* Connect input-xtal to 40MHz reference */
+		clocks = <&ref40m>;
+		clock-names = "input-xtal";
+
+		settings=[
+09 50 00 60 67 C5 6C FF 03 00 30 00 00 01 00 00
+01 07 00 00 07 00 00 77 6D 06 00 00 00 00 00 FF
+FF FF FF 00 3F 00 2A 00 16 33 33 00 01 00 00 D0
+00 00 00 00 00 00 00 00 00 04 00 00 00 02 00 00
+00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 D7 0A 2B 20 00 00 00 0B
+00 00 00 00 00 00 00 00 00 00 27 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+C3 00 08 01 00 00 00 00 00 00 00 00 00 30 00 00
+00 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 85 00 00 9C 01 D4 02 71 07 00 00 00
+00 83 00 10 02 08 8C
+];
+	};
+};

Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml

@@ -24,7 +24,9 @@ properties:
     const: 1
 
   compatible:
-    const: xlnx,zynqmp-dma-1.0
+    enum:
+      - amd,versal2-dma-1.0
+      - xlnx,zynqmp-dma-1.0
 
   reg:
     description: memory map for gdma/adma module access

Documentation/devicetree/bindings/iio/adc/xlnx,versal-sysmon.yaml

@@ -42,6 +42,9 @@ properties:
   '#size-cells':
     const: 0
 
+  '#io-channel-cells':
+    const: 0
+
   xlnx,numchannels:
     $ref: /schemas/types.yaml#/definitions/uint8
     description: |
@@ -87,6 +90,8 @@ patternProperties:
       - reg
       - xlnx,name
 
+    additionalProperties: false
+
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/media/xilinx/xlnx,isppipeline.yaml

@@ -9,6 +9,7 @@ title: Xilinx Video ISP Pipeline IP
 maintainers:
   - Kaushal Kumar <kaushal.kumar@amd.com>
   - Venkat Praveen Kancharlapalli <venkat.praveen.kancharlapalli@amd.com>
+  - Mounik Katikala <mounik.katikala@amd.com>
 
 description: |
     The Xilinx Video ISP pipeline IP is used to interface to a bayer video source.
@@ -17,11 +18,13 @@ description: |
     Gamma_lut array values are computed using compute_gamma function whose link is mentioned below:
     https://github.com/Xilinx/Vitis_Libraries/blob/de67b58ca9c7f4a76411103c0ecf9d467731b476/vision/L1/examples/isppipeline/xf_isp_tb.cpp#L313
     Link to product guide for ISP pipeline is mentioned below:
-    https://docs.xilinx.com/r/en-US/Vitis_Libraries/vision/overview.html_3_8
+    https://docs.amd.com/r/en-US/Vitis_Libraries/vision/index.html
 
 properties:
   compatible:
-    const: xlnx,isppipeline-1.0
+    enum:
+      - xlnx,isppipeline-1.0
+      - xlnx,isppipeline-2.0
 
   reg:
     maxItems: 1
@@ -107,6 +110,12 @@ properties:
 
             additionalProperties: false
 
+          xlnx,video-width:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Width of the video data in bits
+            enum: [8, 10, 12, 16]
+            default: 10
+
         required:
           - reg
           - endpoint
@@ -136,6 +145,12 @@ properties:
 
             additionalProperties: false
 
+          xlnx,video-width:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            description: Width of the video data in bits
+            enum: [8, 10, 12, 16]
+            default: 8
+
         required:
           - reg
           - endpoint
@@ -155,21 +170,46 @@ required:
   - reg
   - clocks
   - reset-gpios
-  - xlnx,max-width
-  - xlnx,max-height
-  - xlnx,rgain
-  - xlnx,bgain
-  - xlnx,pawb
-  - xlnx,mode-reg
   - ports
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: xlnx,isppipeline-1.0
+    then:
+      required:
+        - xlnx,max-height
+        - xlnx,max-width
+        - xlnx,rgain
+        - xlnx,bgain
+        - xlnx,pawb
+        - xlnx,mode-reg
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: xlnx,isppipeline-2.0
+    then:
+      properties:
+        ports:
+          properties:
+            port@0:
+              required:
+                - xlnx,video-width
+            port@1:
+              required:
+                - xlnx,video-width
+
 examples:
   - |
-   ISPPipeline: ISPPipeline@a40f0000 {
+   ISPPipeline0: ISPPipeline@a40c0000 {
         compatible = "xlnx,isppipeline-1.0";
-        reg = <0xa40f0000 0x10000>;
+        reg = <0xa40c0000 0x10000>;
         clocks = <&misc_clk_0>;
         clock-names = "ap_clk";
         reset-gpios = <&gpio 87 1>;
@@ -186,17 +226,46 @@ examples:
             port@0 {
                 /* Sink port */
                 reg = <0>;
-                isppipeline_in: endpoint {
+                isppipeline0_in: endpoint {
                     remote-endpoint = <&isp_csiss_out>;
                 };
             };
             port@1 {
                 /* Source port */
                 reg = <1>;
-                isppipeline_out: endpoint {
+                isppipeline0_out: endpoint {
+                    remote-endpoint = <&isp_vcap_csi_in>;
+                };
+            };
+        };
+    };
+
+  - |
+    ISPPipeline1: ISPPipeline@a40f0000 {
+        compatible = "xlnx,isppipeline-2.0";
+        reg = <0xa40f0000 0x10000>;
+        clocks = <&misc_clk_0>;
+        reset-gpios = <&gpio0 27 1>;
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                /* Sink port */
+                reg = <0>;
+                xlnx,video-width = <10>;
+                isppipeline1_in: endpoint {
+                    remote-endpoint = <&isp_csiss_out>;
+                };
+            };
+
+            port@1 {
+                /* Source port */
+                reg = <1>;
+                xlnx,video-width = <8>;
+                isppipeline1_out: endpoint {
                     remote-endpoint = <&isp_vcap_csi_in>;
                 };
             };
         };
     };
-...

Documentation/devicetree/bindings/media/xilinx/xlnx,v-hdmi-rxss1.yaml

@@ -30,7 +30,18 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 2
+    maxItems: 5
+
+  interrupt-names:
+    description: Only irq is mandatory. Others are optional.
+                 hdcp14_irq and  hdcp14_timer_irq will be present when HDCP 1x is selected.
+                 hdcp22_irq and hdcp22_timer_irq will be present when HDCP 2x is selected.
+    items:
+      - const: hdcp14_irq
+      - const: hdcp14_timer_irq
+      - const: hdcp22_irq
+      - const: hdcp22_timer_irq
+      - const: irq
 
   clocks:
     items:
@@ -172,6 +183,7 @@ required:
   - compatible
   - reg
   - interrupts
+  - interrupt-names
   - clocks
   - clock-names
   - xlnx,edid-ram-size
@@ -194,7 +206,8 @@ examples:
       clock-names = "s_axi_cpu_aclk", "frl_clk", "s_axis_video_aclk";
       clocks = <&zynqmp_clk 71>, <&misc_clk_4>, <&misc_clk_5>;
       interrupt-parent = <&gic>;
-      interrupts = <0 90 4>, <0 104 4>;
+      interrupt-names = "hdcp14_irq", "hdcp14_timer_irq", "hdcp22_irq", "hdcp22_timer_irq", "irq";
+      interrupts = <0 106 4>, <0 107 4>, <0 110 4>, <0 111 4>, <0 91 4>;
       xlnx,edid-ram-size = /bits/ 16 <0x100>;
       xlnx,input-pixels-per-clock = /bits/ 8 <0x8>;
       xlnx,max-bits-per-component = /bits/ 8 <0xa>;

Documentation/devicetree/bindings/net/can/xilinx,can.yaml

@@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title:
-  Xilinx Axi CAN/Zynq CANPS controller
+  Xilinx CAN and CANFD controller
 
 maintainers:
   - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>