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86 | 86 | #define ADI_AXI_ADC_REG_CHAN_CTRL_3(c) (0x0418 + (c) * 0x40)
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87 | 87 | #define ADI_AXI_ADC_CHAN_PN_SEL_MASK GENMASK(19, 16)
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88 | 88 |
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| 89 | +#define ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(c) (0x0424 + (c) * 0x40) |
| 90 | +#define ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK GENMASK(15, 0) |
| 91 | + |
89 | 92 | /* IO Delays */
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90 | 93 | #define ADI_AXI_ADC_REG_DELAY(l) (0x0800 + (l) * 0x4)
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91 | 94 | #define AXI_ADC_DELAY_CTRL_MASK GENMASK(4, 0)
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@@ -248,6 +251,19 @@ static int axi_adc_test_pattern_set(struct iio_backend *back,
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248 | 251 | }
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249 | 252 | }
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250 | 253 |
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| 254 | +static int axi_adc_oversampling_ratio_set(struct iio_backend *back, |
| 255 | + unsigned int chan, |
| 256 | + unsigned int rate) |
| 257 | +{ |
| 258 | + struct adi_axi_adc_state *st = iio_backend_get_priv(back); |
| 259 | + |
| 260 | + return regmap_update_bits(st->regmap, |
| 261 | + ADI_AXI_ADC_REG_CHAN_USR_CTRL_2(chan), |
| 262 | + ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK, |
| 263 | + FIELD_PREP(ADI_AXI_ADC_CHAN_USR_CTRL_2_DEC_RATE_N_MASK, |
| 264 | + rate)); |
| 265 | +} |
| 266 | + |
251 | 267 | static int axi_adc_read_chan_status(struct adi_axi_adc_state *st, unsigned int chan,
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252 | 268 | unsigned int *status)
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253 | 269 | {
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@@ -600,6 +616,7 @@ static const struct iio_backend_ops adi_axi_adc_ops = {
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600 | 616 | .test_pattern_set = axi_adc_test_pattern_set,
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601 | 617 | .chan_status = axi_adc_chan_status,
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602 | 618 | .interface_type_get = axi_adc_interface_type_get,
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| 619 | + .oversampling_ratio_set = axi_adc_oversampling_ratio_set, |
603 | 620 | .debugfs_reg_access = iio_backend_debugfs_ptr(axi_adc_reg_access),
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604 | 621 | .debugfs_print_chan_status = iio_backend_debugfs_ptr(axi_adc_debugfs_print_chan_status),
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605 | 622 | };
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