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PopPaul2021nunojsa
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arm64: dts: xilinx: Add dts for AD9164
The devicetree was added for the EVAL-AD9164 board working in MODE 8 on the ZCU102. Signed-off-by: PopPaul2021 <paul.pop@analog.com>
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‎arch/arm64/boot/dts/xilinx/adi-ad9164-fmc-ebz.dtsi

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// SPDX-License-Identifier: GPL-2.0
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/*
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* dtsi file for AD916x-FMC-EBZ on Xilinx ZynqMP ZCU102 Rev 1.0
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*
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* Copyright (C) 2024 Analog Devices Inc.
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*/
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/ {
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clocks {
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adf4355_clkin: clock@0 {
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compatible = "fixed-clock";
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clock-frequency = <120000000>;
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clock-output-names = "clkin";
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#clock-cells = <0>;
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};
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adf4355_out_div4: hmc365 {
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&adf4355_clk>;
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#clock-cells = <0>;
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};
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ad9508_clkin: clock@1 {
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&adf4355_out_div4>;
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#clock-cells = <0>;
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};
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};
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};
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#include <dt-bindings/iio/frequency/ad9508.h>
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&fmc_spi {
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adf4355_clk: adf4355@2 {
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compatible = "adi,adf4355-2";
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reg = <2>;
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spi-max-frequency = <10000000>;
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clocks = <&adf4355_clkin>;
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clock-names = "clkin";
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clock-scales = <1 1>;
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clock-output-names = "adf4355_pll";
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#clock-cells = <0>;
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adi,charge-pump-current = <900>;
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adi,muxout-select = <6>;
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adi,output-a-power = <3>;
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adi,output-b-power = <3>;
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adi,charge-pump-negative-bleed-enable;
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adi,reference-differential-input-enable;
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adi,muxout-level-3v3-enable;
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adi,power-up-frequency = /bits/ 64 <5000000000>;
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adi,output-a-enable;
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adi,output-b-enable;
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adi,clock-shift = <1>;
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};
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ad9508_clk: ad9508@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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compatible = "adi,ad9508";
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reg = <0>;
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spi-cpol;
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spi-cpha;
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clocks = <&ad9508_clkin>;
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spi-max-frequency = <10000000>;
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clock-output-names = "ad9508-1_out0", "ad9508-1_out1", "ad9508-1_out2", "ad9508-1_out3";
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jesd204-device;
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adi,write-mode-only;
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#jesd204-cells = <2>;
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jesd204-sysref-provider;
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ad9508_0_c0:channel@0 {
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reg = <0>;
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adi,extended-name = "REF_CLK";
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adi,driver-mode = <(DRIVER_PHASE_NORMAL | DRIVER_MODE_LVDS_1_00)>;
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adi,divider-phase = <0>;
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adi,channel-divider = <4>;
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};
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ad9508_0_c2:channel@2 {
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reg = <2>;
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adi,extended-name = "SYSREF2";
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adi,driver-mode = <(DRIVER_PHASE_NORMAL | DRIVER_MODE_LVDS_1_00)>;
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adi,divider-phase = <0>;
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adi,channel-divider = <32>;
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};
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ad9508_0_c3:channel@3 {
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reg = <3>;
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adi,extended-name = "SYSREF";
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adi,driver-mode = <(DRIVER_PHASE_NORMAL | DRIVER_MODE_LVDS_1_00)>;
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adi,divider-phase = <0>;
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adi,channel-divider = <32>;
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};
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};
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dac0_ad9164: ad9164@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "adi,ad9164";
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reg = <1>;
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spi-max-frequency = <1000000>;
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clocks = <&adf4355_clk 0>;
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clock-names = "dac_clk";
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spi-cpol;
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spi-cpha;
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adi,full-scale-current-mircoamp = <40000>;
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dac_clk-clock-scales = <1 1>;
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jesd204-device;
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#jesd204-cells = <2>;
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jesd204-top-device = <0>; /* This is the TOP device */
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jesd204-link-ids = <0>;
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jesd204-inputs = <&axi_ad9164_core 0 0>;
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adi,jesd-subclass = <1>;
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adi,dac-interpolation = <2>;
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adi,channel-interpolation = <2>;
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adi,clock-output-divider = <1>;
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adi,syncoutb-signal-type-lvds-enable;
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//adi,scrambling = <1>;
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adi,sysref-mode = <2>; /* SYSREF_CONTINUOUS */
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adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
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adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
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adi,converters-per-device = <2>; /* JESD M */
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adi,octets-per-frame = <1>; /* JESD F */
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adi,frames-per-multiframe = <32>; /* JESD K */
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adi,converter-resolution = <16>; /* JESD N */
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adi,bits-per-sample = <16>; /* JESD NP' */
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adi,control-bits-per-sample = <0>; /* JESD CS */
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adi,lanes-per-device = <8>; /* JESD L */
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adi,samples-per-converter-per-frame = <2>; /* JESD S */
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adi,interpolation = <2>;
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};
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};

‎arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9164-fmc-ebz_m2_s2.dts

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// SPDX-License-Identifier: GPL-2.0
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/*
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* AD9164-FMC-EBZ on Xilinx ZynqMP ZCU102 Rev 1.0
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*
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* JESD Link Mode 8 Example: M2, L8, S2, F1, NP'16, Interpolation: 2
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*
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* https://analogdevicesinc.github.io/hdl/projects/dac_fmc_ebz/index.html
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*
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* hdl_project: <dac_fmc_ebz/zcu102>
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* ADI_DAC_DEVICE: <AD9164>
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* ADI_LANE_RATE: <12.5>
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* ADI_DAC_MODE: <08>
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* board_revision: <H>
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*
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* Copyright (C) 2024 Analog Devices Inc.
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*/
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#include "zynqmp-zcu102-rev1.0.dts"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/jesd204/adxcvr.h>
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&i2c1 {
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i2c-mux@75 {
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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eeprom@50 {
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compatible = "at24,24c02";
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reg = <0x50>;
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};
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};
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};
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};
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/ {
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ad9164_control@0 {
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compatible = "adi,one-bit-adc-dac";
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#address-cells = <1>;
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#size-cells = <0>;
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out-gpios = <&gpio 99 0>, <&gpio 100 0>, <&gpio 101 0>, <&gpio 102 0>, <&gpio 103 0>;
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label = "ad9164_control";
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channel@0 {
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reg = <0>;
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label = "dac_ctrl_0";
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};
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channel@1 {
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reg = <1>;
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label = "dac_ctrl_1";
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};
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channel@2 {
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reg = <2>;
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label = "dac_ctrl_2";
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};
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channel@3 {
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reg = <3>;
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label = "dac_ctrl_3";
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};
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channel@4 {
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reg = <4>;
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label = "dac_ctrl_4";
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};
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};
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fpga_axi: fpga-axi@0 {
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interrupt-parent = <&gic>;
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compatible = "simple-bus";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges = <0 0 0 0xffffffff>;
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tx_dma: tx-dmac@9c420000 {
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#dma-cells = <1>;
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compatible = "adi,axi-dmac-1.00.a";
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adi,cyclic;
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reg = <0x9c420000 0x10000>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&zynqmp_clk 71>;
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};
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axi_ad9164_core: axi-ad9164-hpc@84a04000 {
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compatible = "adi,axi-ad9162-1.0";
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reg = <0x84a04000 0x10000>;
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dmas = <&tx_dma 0>;
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dma-names = "tx";
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spibus-connected = <&dac0_ad9164>;
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adi,axi-pl-fifo-enable;
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/* jesd204-fsm support */
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jesd204-device;
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#jesd204-cells = <2>;
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jesd204-inputs = <&axi_ad9164_jesd 0 0>;
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};
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axi_ad9164_jesd: axi-jesd204-tx@84a90000 {
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compatible = "adi,axi-jesd204-tx-1.0";
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reg = <0x84a90000 0x4000>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&zynqmp_clk 71>, <&axi_ad9164_adxcvr 1>, <&axi_ad9164_adxcvr 0>;
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clock-names = "s_axi_aclk", "device_clk", "lane_clk";
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#clock-cells = <0>;
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clock-output-names = "jesd_dac_lane_clk";
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/* jesd204-fsm support */
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jesd204-device;
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#jesd204-cells = <2>;
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jesd204-inputs = <&axi_ad9164_adxcvr 0 0>;
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};
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axi_ad9164_adxcvr: axi-adxcvr-tx@84a60000 {
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compatible = "adi,axi-adxcvr-1.0";
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reg = <0x84a60000 0x1000>;
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clocks = <&ad9508_clk 0>;
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clock-names = "conv";
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adi,sys-clk-select = <XCVR_QPLL>;
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adi,out-clk-select = <XCVR_REFCLK>;
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adi,use-lpm-enable;
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#clock-cells = <1>;
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clock-output-names = "dac_gt_clk", "tx_out_clk";
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/* jesd204-fsm support */
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jesd204-device;
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#jesd204-cells = <2>;
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};
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axi_sysid_0: axi-sysid-0@85000000 {
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compatible = "adi,axi-sysid-1.00.a";
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reg = <0x85000000 0x10000>;
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};
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};
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};
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&spi0 {
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status = "okay";
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};
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#define fmc_spi spi0
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#include "adi-ad9164-fmc-ebz.dtsi"

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