iio: adc: ad_pulsar: Specify PWM parameters in nanoseconds

With the reference clock running at less than 1 GHz two different
settings for the used PWM differ by more than 1 ns. So there is no
advantage to differ from the upstream pwm subsystem and give the
illusion of pico second resolution.

With the goal to drop support for time_unit, don't explicitly set
.time_unit = PWM_UNIT_NSEC but rely on this being the default.

Also improve precision in the period calculation by not multiplying the
result of two divisions but a single (reduced) division.

Further use up-rounding instead of round-to-nearest to make the driver
robust to rounding changes in the axi-pwmgen driver and to make freq a
hard upper limit on sample frequency. Upstream pwm drivers are expected
to round down requested values in pwm_apply_state(). There is a
potential error introduced by changing the rounding here until the
axi-pwmgen driver is aligned to mainline requirements. This error is
however in the same order as the already existing one that is introduced
by the integer divisions.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>

Author: ukleinek

drivers/iio/adc/ad_pulsar.c

@@ -423,28 +423,30 @@ static int ad_pulsar_reg_access(struct iio_dev *indio_dev, unsigned int reg,
 
 static int ad_pulsar_set_samp_freq(struct ad_pulsar_adc *adc, int freq)
 {
-	unsigned long long target, ref_clk_period_ps;
+	unsigned long long ref_clk_period_ns;
 	struct pwm_state cnv_state;
 	int ret;
 
+	/*
+	 * The objective here is to configure the PWM such that we don't have
+	 * more than $freq periods per second and duty_cycle and phase should be
+	 * their minimal positive value.
+	 */
 	freq = clamp(freq, 1, adc->info->max_rate);
-	target = DIV_ROUND_CLOSEST_ULL(adc->ref_clk_rate, freq);
-	ref_clk_period_ps = DIV_ROUND_CLOSEST_ULL(1000000000000,
-						  adc->ref_clk_rate);
+	ref_clk_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, adc->ref_clk_rate);
 
 	cnv_state = (struct pwm_state){
-		.period = ref_clk_period_ps * target,
-		.duty_cycle = ref_clk_period_ps,
-		.phase = ref_clk_period_ps,
-		.time_unit = PWM_UNIT_PSEC,
+		.period = DIV_ROUND_UP(NSEC_PER_SEC, freq),
+		.duty_cycle = ref_clk_period_ns,
+		.phase = ref_clk_period_ns,
 		.enabled = true,
 	};
 
 	ret = pwm_apply_state(adc->cnv, &cnv_state);
 	if (ret)
 		return ret;
 
-	adc->samp_freq = DIV_ROUND_CLOSEST_ULL(adc->ref_clk_rate, target);
+	adc->samp_freq = freq;
 
 	return ret;
 }