arm: dts: socfpga: Shuffle devices between dtsi files for de10-nano

There are two device tree include files for the de10-nano machine:
socfpga_cyclone5_de10_nano.dtsi and socfpga_cyclone5_de10_nano_hps.dtsi.
Reorganize such that the former include contains all definitions of the
board's actual hardware that doesn't depend on a certain FPGA
configuration.  and the latter has all the default FPGA stuff.

Note that for this separation it's right that the hps dtsi includes the
generic one and not the other way round. Accordingly adapt all dts files
that include the dtsi, to include the hps one.

As devices only were moved between the two dtsi files and all dts files
(recursively) included and include both dtsi, nothing relevant was
changed for these. The only exception is
socfpga_cyclone5_de10_nano_hps.dts. This only included one dtsi (the hps
one). Delete that one as it is a subset of
socfpga_cyclone5_de10_nano.dts and the latter should work wherever the
former does.

dtdiff was used to verify that socfpga_cyclone5_de10_nano*.dtb didn't
change by this commit.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>

Author: ukleinek

arch/arm/boot/dts/socfpga_cyclone5_de10_nano.dts

@@ -9,4 +9,4 @@
  * Copyright (C) 2020 Analog Devices Inc.
  */
 /dts-v1/;
-#include "socfpga_cyclone5_de10_nano.dtsi"
+#include "socfpga_cyclone5_de10_nano_hps.dtsi"

arch/arm/boot/dts/socfpga_cyclone5_de10_nano.dtsi

@@ -5,178 +5,102 @@
  * based on socfpga_cyclone5_de0_nano_soc.dts
  */
 
-#include "socfpga_cyclone5_de10_nano_hps.dtsi"
+#include "socfpga_cyclone5.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 
+/ {
+	model = "Terasic DE10-Nano";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
 
-&i2c0 {
-	adv7513: adv7513@39 {
-		compatible = "adi,adv7513";
-		reg = <0x39>, <0x3f>;
-		reg-names = "primary", "edid";
-
-		adi,input-depth = <8>;
-		adi,input-colorspace = "rgb";
-		adi,input-clock = "1x";
-		adi,clock-delay = <0>;
-
-		#sound-dai-cells = <0>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-				adv7513_in: endpoint {
-					remote-endpoint = <&axi_hdmi_out>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-			};
-		};
+	chosen {
+		bootargs = "earlyprintk";
+		stdout-path = "serial0:115200n8";
 	};
-};
 
-&fpga_axi {
-	gpio_in: gpio_in@0x00010100 {
-		compatible = "altr,pio-18.1", "altr,pio-1.0";
-		reg = <0x00010100 0x00000010>;
-		altr,gpio-bank-width = <32>;
-		altr,interrupt-type = <4>;
-		altr,interrupt_type = <4>;
-		level_trigger = <1>;
-		resetvalue = <0>;
-		#gpio-cells = <2>;
-		gpio-controller;
+	aliases {
+		ethernet0 = &gmac1;
+		udc0 = &usb1;
 	};
 
-	gpio_out: gpio_out@0x00109000 {
-		compatible = "altr,pio-1.0";
-		reg = <0x00109000 0x00000010>;
-		altr,gpio-bank-width = <32>;
-		resetvalue = <0>;
-		#gpio-cells = <2>;
-		gpio-controller;
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>;	/* 1GB */
 	};
 
-	spi@0x00010A000 {
-		compatible = "altr,spi-18.1", "altr,spi-1.0";
-		reg = <0x0010a000 0x00000020>;
-		interrupt-parent = <&intc>;
-		interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
-		#address-cells = <0x1>;
-		#size-cells = <0x0>;
-
-		ltc2308: adc@0 {
-			compatible = "adi,ltc2308";
-			reg = <0>;
-			spi-max-frequency = <40000000>;
-			vref-supply = <&ltc2308_vref>;
-			cnv-gpios = <&gpio_out 9 GPIO_ACTIVE_HIGH>;
+	soc {
+		fpga_axi: axi_h2f_lw_bridge@0xff200000 {
+			compatible = "simple-bus";
+			reg = <0xff200000 0x00200000>;
 			#address-cells = <1>;
-			#size-cells = <0>;
-			channel@0 {
-				reg = <0>;
-			};
-			channel@1 {
-				reg = <1>;
-			};
-			channel@2 {
-				reg = <2>;
-			};
-			channel@3 {
-				reg = <3>;
-			};
-			channel@4 {
-				reg = <4>;
-			};
-			channel@5 {
-				reg = <5>;
-			};
-			channel@6 {
-				reg = <6>;
-			};
-			channel@7 {
-				reg = <7>;
-			};
+			#size-cells = <1>;
+			ranges = <0x00000000 0xff200000 0x00200000>;
 		};
 	};
+};
 
-	axi_sysid_0: axi-sysid-0@00018000 {
-		compatible = "adi,axi-sysid-1.00.a";
-		reg = <0x00018000 0x8000>;
-	};
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <420>;
+	rxd1-skew-ps = <420>;
+	rxd2-skew-ps = <420>;
+	rxd3-skew-ps = <420>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <1860>;
+	rxdv-skew-ps = <420>;
+	rxc-skew-ps = <1680>;
+};
 
-	hdmi_tx_dma: dma@0x00080000 {
-		compatible = "adi,axi-dmac-1.00.a";
-		reg = <0x00080000 0x00000800>;
-		interrupt-parent = <&intc>;
-		interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
-		#dma-cells = <1>;
-		clocks = <&sys_clk>;
+&gpio0 {
+	status = "okay";
+};
 
-		adi,channels {
-			#size-cells = <0>;
-			#address-cells = <1>;
+&gpio1 {
+	status = "okay";
+};
 
-			dma-channel@0 {
-				reg = <0>;
-				adi,source-bus-width = <64>;
-				adi,source-bus-type = <0>;
-				adi,destination-bus-width = <64>;
-				adi,destination-bus-type = <1>;
-			};
-		};
-	};
+&gpio2 {
+	status = "okay";
+};
 
-	axi_hdmi@0x00090000 {
-		compatible = "adi,axi-hdmi-tx-1.00.a";
-		reg = <0x00090000 0x10000>;
-		dmas = <&hdmi_tx_dma 0>;
-		dma-names = "video";
-		clocks = <&pixel_clock 0>;
-		adi,is-rgb;
-
-		port {
-			axi_hdmi_out: endpoint {
-				remote-endpoint = <&adv7513_in>;
-			};
-		};
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	adxl345@53 {
+		compatible = "adi,adxl34x";
+		reg = <0x53>;
+		interrupt-parent = <&portc>;
+		interrupts = <3 2>;
 	};
+};
 
-	ref_clk: ref_clk {
-		#clock-cells = <0x0>;
-		compatible = "fixed-clock";
-		clock-frequency = <50000000>;
-		clock-output-names = "reference_clock";
-	};
+&mmc0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
 
-	pixel_clock: fpll@0x00100000 {
-		#clock-cells = <0x1>;
-		compatible = "altr,c5-fpll";
-		reg = <0x00100000 0x00000100>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		clocks = <&ref_clk>;
-		assigned-clocks = <&pixel_clock 0>, <&pixel_clock 1>;
-		assigned-clock-rates = <148500000>, <100000000>;
-		clock-output-names = "c5_out0", "c5_out1", "c5_out2",
-				     "c5_out3", "c5_out4", "c5_out5",
-				     "c5_out6", "c5_out7", "c5_out8";
-		adi,fractional-carry-bit = <32>;
-
-		fpll_c0: channel@0 {
-			reg = <0>;
-			adi,extended-name = "PIXEL_CLOCK";
-		};
+&porta {
+	bank-name = "porta";
+};
 
-		fpll_c1: channel@1 {
-			reg = <1>;
-			adi,extended-name = "DMA_CLOCK";
-		};
-	};
+&portb {
+	bank-name = "portb";
+};
+
+&portc {
+	bank-name = "portc";
+};
+
+&uart0 {
+	status = "okay";
+	clock-frequency = <100000000>;
+	u-boot,dm-pre-reloc;
+};
+
+&usb1 {
+	status = "okay";
 };

arch/arm/boot/dts/socfpga_cyclone5_de10_nano_cn0501.dts

@@ -9,7 +9,7 @@
  * Copyright (C) 2021 Analog Devices Inc.
  */
 /dts-v1/;
-#include "socfpga_cyclone5_de10_nano.dtsi"
+#include "socfpga_cyclone5_de10_nano_hps.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 

arch/arm/boot/dts/socfpga_cyclone5_de10_nano_cn0540.dts

@@ -11,7 +11,7 @@
  * Copyright (C) 2020 Analog Devices Inc.
  */
 /dts-v1/;
-#include "socfpga_cyclone5_de10_nano.dtsi"
+#include "socfpga_cyclone5_de10_nano_hps.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 

arch/arm/boot/dts/socfpga_cyclone5_de10_nano_cn0579_i2c.dts

@@ -8,7 +8,7 @@
  *
  * Copyright (C) 2023 Analog Devices Inc.
  */
-#include "socfpga_cyclone5_de10_nano.dtsi"
+#include "socfpga_cyclone5_de10_nano_hps.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>