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50 | 50 | #define SPI_ENGINE_CONFIG_CPHA BIT(0)
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51 | 51 | #define SPI_ENGINE_CONFIG_CPOL BIT(1)
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52 | 52 | #define SPI_ENGINE_CONFIG_3WIRE BIT(2)
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| 53 | +#define SPI_ENGINE_CONFIG_SDO_IDLE_HIGH BIT(3) |
53 | 54 |
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54 | 55 | #define SPI_ENGINE_INST_TRANSFER 0x0
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55 | 56 | #define SPI_ENGINE_INST_ASSERT 0x1
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@@ -146,6 +147,10 @@ static unsigned int spi_engine_get_config(struct spi_device *spi)
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146 | 147 | config |= SPI_ENGINE_CONFIG_CPHA;
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147 | 148 | if (spi->mode & SPI_3WIRE)
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148 | 149 | config |= SPI_ENGINE_CONFIG_3WIRE;
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| 150 | + if (spi->mode & SPI_MOSI_IDLE_HIGH) |
| 151 | + config |= SPI_ENGINE_CONFIG_SDO_IDLE_HIGH; |
| 152 | + if (spi->mode & SPI_MOSI_IDLE_LOW) |
| 153 | + config &= ~SPI_ENGINE_CONFIG_SDO_IDLE_HIGH; |
149 | 154 |
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150 | 155 | return config;
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151 | 156 | }
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@@ -785,9 +790,13 @@ static int spi_engine_probe(struct platform_device *pdev)
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785 | 790 | host->num_chipselect = 8;
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786 | 791 |
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787 | 792 | /* Some features depend of the IP core version. */
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788 |
| - if (ADI_AXI_PCORE_VER_MINOR(version) >= 2) { |
789 |
| - host->mode_bits |= SPI_CS_HIGH; |
790 |
| - host->setup = spi_engine_setup; |
| 793 | + if (ADI_AXI_PCORE_VER_MAJOR(version) >= 1) { |
| 794 | + if (ADI_AXI_PCORE_VER_MINOR(version) >= 2) { |
| 795 | + host->mode_bits |= SPI_CS_HIGH; |
| 796 | + host->setup = spi_engine_setup; |
| 797 | + } |
| 798 | + if (ADI_AXI_PCORE_VER_MINOR(version) >= 3) |
| 799 | + host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH; |
791 | 800 | }
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792 | 801 |
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793 | 802 | if (host->max_speed_hz == 0)
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