arm: dts: xilinx: normalize node name@address

dlech · nunojsa · commit 566fb43906c5 · 2025-03-05T10:44:20.000Z
Remove 0x from address in the name@address. This is the preferred style.

Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7687-pmdz.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7687-pmdz.dts
@@ -26,7 +26,7 @@
 
 &fpga_axi {
 
-	adc_trigger: pwm@0x44b00000 {
+	adc_trigger: pwm@44b00000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
@@ -76,7 +76,7 @@
 		clocks = <&clkc 16>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7689-ardz.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7689-ardz.dts
@@ -26,7 +26,7 @@
 
 &fpga_axi {
 
-	adc_trigger: pwm@0x44b00000 {
+	adc_trigger: pwm@44b00000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
@@ -99,7 +99,7 @@
 		clocks = <&clkc 16>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7946.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7946.dts
@@ -26,7 +26,7 @@
 
 &fpga_axi {
 
-	adc_trigger: pwm@0x44b00000 {
+	adc_trigger: pwm@44b00000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
@@ -75,7 +75,7 @@
 		clocks = <&clkc 16>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7984.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7984.dts
@@ -26,7 +26,7 @@
 
 &fpga_axi {
 
-	adc_trigger: pwm@0x44b00000 {
+	adc_trigger: pwm@44b00000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
@@ -76,7 +76,7 @@
 		clocks = <&clkc 16>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-adaq4003.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-adaq4003.dts
@@ -25,7 +25,7 @@
 
 &fpga_axi {
 
-		adc_trigger: pwm@0x44b00000 {
+		adc_trigger: pwm@44b00000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
@@ -78,7 +78,7 @@
 		clocks = <&clkc 16>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-cn0540.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-cn0540.dts
@@ -149,7 +149,7 @@
 		};
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad3552r-hs.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad3552r-hs.dts
@@ -59,7 +59,7 @@
 		clock-output-names = "ref_clk";
 	};
 
-	dac_tx_dma: dma-controller@0x44a30000 {
+	dac_tx_dma: dma-controller@44a30000 {
 		compatible = "adi,axi-dmac-1.00.a";
 		reg = <0x44a30000 0x10000>;
 		#dma-cells = <1>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4030-24.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4030-24.dts
@@ -58,7 +58,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4032-24.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4032-24.dts
@@ -58,7 +58,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-16.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-16.dts
@@ -58,7 +58,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-24.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-24.dts
@@ -58,7 +58,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7625.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7625.dts
@@ -67,7 +67,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	ref_clk: clock@0x44a80000 {
+	ref_clk: clock@44a80000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a80000 0x10000>;
 		#clock-cells = <0>;
@@ -76,15 +76,15 @@
 		clock-output-names = "ref_clk";
 	};
 
-	axi_pwm_gen: pwm@0x44a60000 {
+	axi_pwm_gen: pwm@44a60000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44a60000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <3>;
 		clocks = <&ref_clk>;
 	};
 
-	iio_backend: backend@0x44a00000{
+	iio_backend: backend@44a00000{
 		reg = <0x44a00000 0x10000>;
 		compatible = "adi,axi-adc-10.0.a";
 		dmas = <&rx_dma 0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7768-1-evb.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7768-1-evb.dts
@@ -34,7 +34,7 @@
 };
 
 &fpga_axi {
-	rx_dma: rx-dmac@0x44a30000 {
+	rx_dma: rx-dmac@44a30000 {
 		compatible = "adi,axi-dmac-1.00.a";
 		reg = <0x44a30000 0x1000>;
 		#dma-cells = <1>;
@@ -51,7 +51,7 @@
 		clock-names = "clkin1", "s_axi_aclk";
 	};
 
-	axi_spi_engine_0: spi@0x44a00000 {
+	axi_spi_engine_0: spi@44a00000 {
 		compatible = "adi,legacy-axi-spi-engine-1.00.a";
 		reg = <0x44a00000 0x1000>;
 		interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7960.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7960.dts
@@ -69,7 +69,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	ref_clk: clock@0x44a80000 {
+	ref_clk: clock@44a80000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a80000 0x10000>;
 		#clock-cells = <0>;
@@ -78,15 +78,15 @@
 		clock-output-names = "ref_clk";
 	};
 
-	axi_pwm_gen: pwm@0x44a60000 {
+	axi_pwm_gen: pwm@44a60000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44a60000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <3>;
 		clocks = <&ref_clk>;
 	};
 
-	iio_backend: backend@0x44a00000{
+	iio_backend: backend@44a00000{
 		reg = <0x44a00000 0x10000>;
 		compatible = "adi,axi-adc-10.0.a";
 		dmas = <&rx_dma 0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4216.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4216.dts
@@ -74,7 +74,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4220.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4220.dts
@@ -85,7 +85,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24.dts
@@ -85,7 +85,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24_cm0_sdi4_cz2.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24_cm0_sdi4_cz2.dts
@@ -72,7 +72,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	spi_clk: axi-clkgen@0x44a70000 {
+	spi_clk: axi-clkgen@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-cn0577.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-cn0577.dts
@@ -56,7 +56,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	axi_pwm_gen: pwm@0x44a60000 {
+	axi_pwm_gen: pwm@44a60000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44a60000 0x1000>;
 		label = "ltc2387_if";
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ltc2387.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ltc2387.dts
@@ -34,7 +34,7 @@
 		clocks = <&clkc 15>;
 	};
 
-	ref_clk: clk@0x44a70000 {
+	ref_clk: clk@44a70000 {
 		compatible = "adi,axi-clkgen-2.00.a";
 		reg = <0x44a70000 0x10000>;
 		#clock-cells = <0>;
@@ -43,7 +43,7 @@
 		clock-output-names = "ref_clk";
 	};
 
-	axi_pwm_gen: pwm@0x44a60000 {
+	axi_pwm_gen: pwm@44a60000 {
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44a60000 0x1000>;
 		label = "ltc2387_if";
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-fmc-ebz.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-fmc-ebz.dts
@@ -53,7 +53,7 @@
 			jesd204-inputs = <&axi_ad9083_rx_jesd 0 0>;
 		};
 
-		axi_ad9083_rx_jesd: axi-jesd204-rx@0x84AA0000 {
+		axi_ad9083_rx_jesd: axi-jesd204-rx@84AA0000 {
 			compatible = "adi,axi-jesd204-rx-1.0";
 			reg = <0x84AA0000 0x1000>;
 
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-vna-15p625msps.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-vna-15p625msps.dts
@@ -44,7 +44,7 @@
 			jesd204-inputs = <&axi_ad9083_rx_jesd 0 0>;
 		};
 
-		axi_ad9083_rx_jesd: axi-jesd204-rx@0x84AA0000 {
+		axi_ad9083_rx_jesd: axi-jesd204-rx@84AA0000 {
 			compatible = "adi,axi-jesd204-rx-1.0";
 			reg = <0x84AA0000 0x1000>;
 
