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ukleineknunojsa
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iio: adc: ad4630: Specify PWM parameters in nanoseconds
With ref_clk running with a rate not bigger than 1 GHz there is no gain in using picosecond units as two different PWM settings differ by at least one nanosecond. So there is no need to differ from upstream where the pwm subsystem uses nanoseconds to specify PWM parameters. With the goal to drop support for time_unit, don't explicitly set state.time_unit = PWM_UNIT_NSEC but rely on this being the default. Note that in corner cases this change might result in different settings being used. However with the current implemention in the axi-pwmgen driver the result only gets more exact because only one rounding operation is done. Note further the rounding of the phase value isn't exact. I didn't try to do the math to make this exact because I assume having .phase > .period doesn't have the intended effect anyhow. Also with an input rate of less than 500 MHz for the PWM the error cancels out when the absolute time is converted to clock ticks. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
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drivers/iio/adc/ad4630.c

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -370,17 +370,15 @@ static int ad4630_read_avail(struct iio_dev *indio_dev,
370370
static int __ad4630_set_sampling_freq(const struct ad4630_state *st, unsigned int freq)
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{
372372
struct pwm_state conv_state = {
373-
.duty_cycle = 10000,
374-
.time_unit = PWM_UNIT_PSEC,
373+
.duty_cycle = 10,
375374
.enabled = true,
376375
}, fetch_state = {
377-
.duty_cycle = 10000,
378-
.time_unit = PWM_UNIT_PSEC,
376+
.duty_cycle = 10,
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.enabled = true,
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};
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int ret;
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383-
conv_state.period = DIV_ROUND_CLOSEST_ULL(PICO, freq);
381+
conv_state.period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq);
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ret = pwm_apply_state(st->conv_trigger, &conv_state);
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if (ret)
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return ret;
@@ -406,7 +404,7 @@ static int __ad4630_set_sampling_freq(const struct ad4630_state *st, unsigned in
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* tsync + tquiet_con_delay being tsync the conversion signal period
407405
* and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly.
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*/
409-
fetch_state.phase = fetch_state.period + 9800;
407+
fetch_state.phase = fetch_state.period + 10;
410408

411409
return pwm_apply_state(st->fetch_trigger, &fetch_state);
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}

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