iio: adc: ad400x: Change rounding to prepare using upstream pwm driver

Upstream pwm drivers are supposed to round down (period and) duty_cycle.
The axi-pwmgen driver used in this vendor fork uses round to nearest. To
ensure the ad400x driver is not affected when the axi-pwmgen driver is
aligned to the requested upstream behaviour, change the rounding used to
calculate duty cycle. Period is addressed in the next commit.

Under the assumption that the pwm used is provided by the axi-pwmgen
driver and st->ref_clk_rate matches the pwm's clk rate and this clock
rate is less than 500 MHz the change implemented in this commit doesn't
result in any changes in the used register settings. These conditions
are all met.

With these conditions met (and period fixed in the next commit), the
rounding in the axi-pwmgen driver can be aligned to the upstream driver
without further changes.

Also pick a cheaper division function, the calculation's parameters both
fit into an u32, so no need for a 64 bit division.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>

Author: ukleinek

drivers/iio/adc/ad400x.c

@@ -204,16 +204,14 @@ static int ad400x_get_sampling_freq(struct ad400x_state *st)
 
 static int __ad400x_set_sampling_freq(struct ad400x_state *st, int freq)
 {
-	unsigned long long ref_clk_period_ns;
 	struct pwm_state cnv_state;
 
 	/* Sync up PWM state and prepare for pwm_apply_state(). */
 	pwm_init_state(st->cnv_trigger, &cnv_state);
 
-	ref_clk_period_ns = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC,
-						  st->ref_clk_rate);
 	cnv_state.period = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, freq);
-	cnv_state.duty_cycle = ref_clk_period_ns;
+	cnv_state.duty_cycle = DIV_ROUND_UP(NSEC_PER_SEC, st->ref_clk_rate);
+
 	return pwm_apply_state(st->cnv_trigger, &cnv_state);
 }