arm64: zynqmp: Enable Cache Coherency

podgori · nunojsa · commit 1fc69ff0528f · 2025-03-03T08:46:59.000Z
Enable dma coherent in the currently supported zynqmp device trees.

Signed-off-by: Ionut Podgoreanu &lt;ionut.podgoreanu@analog.com&gt;
Signed-off-by: Nuno Sá &lt;nuno.sa@analog.com&gt;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva.dtsi
@@ -1329,6 +1329,7 @@
 			reg = <0x0 0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -1338,6 +1339,7 @@
 			reg = <0x0 0x9c440000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -1347,6 +1349,7 @@
 			reg = <0x0 0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-jupiter-sdr.dts b/arch/arm64/boot/dts/xilinx/zynqmp-jupiter-sdr.dts
@@ -17,6 +17,7 @@
 		compatible = "adi,axi-dmac-1.00.a";
 		reg = <0x84A40000 0x10000>;
 		#dma-cells = <1>;
+		dma-coherent;
 		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&zynqmp_clk 71>;
 	};
@@ -25,6 +26,7 @@
 		compatible = "adi,axi-dmac-1.00.a";
 		reg = <0x84A60000 0x10000>;
 		#dma-cells = <1>;
+		dma-coherent;
 		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&zynqmp_clk 71>;
 	};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-jupiter-sdr.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-jupiter-sdr.dtsi
@@ -441,6 +441,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x84A30000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
@@ -449,6 +450,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x84A50000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-default.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-default.dtsi
@@ -40,6 +40,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -49,6 +50,7 @@
 			reg = <0x9c430000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-overlay.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-overlay.dts
@@ -415,6 +415,7 @@
 				reg = <0x0 0x9c420000 0x0 0x10000>;
 				#dma-cells = <1>;
 				#clock-cells = <0>;
+				dma-coherent;
 				interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&zynqmp_clk 73>;
 			};
@@ -424,6 +425,7 @@
 				reg = <0x0 0x9c430000  0x0 0x10000>;
 				#dma-cells = <1>;
 				#clock-cells = <0>;
+				dma-coherent;
 				interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&zynqmp_clk 73>;
 			};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-fmc-ebz.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-fmc-ebz.dts
@@ -36,6 +36,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-vna-15p625msps.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-vna-15p625msps.dts
@@ -27,6 +27,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9161-fmc-ebz_m2_s2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9161-fmc-ebz_m2_s2.dts
@@ -73,6 +73,7 @@
 
 		tx_dma: tx-dmac@9c420000 {
 			#dma-cells = <1>;
+			dma-coherent;
 			compatible = "adi,axi-dmac-1.00.a";
 			adi,cyclic;
 			reg = <0x9c420000 0x10000>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9162-fmc-ebz_m2_s2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9162-fmc-ebz_m2_s2.dts
@@ -74,6 +74,7 @@
 
 		tx_dma: tx-dmac@9c420000 {
 			#dma-cells = <1>;
+			dma-coherent;
 			compatible = "adi,axi-dmac-1.00.a";
 			adi,cyclic;
 			reg = <0x9c420000 0x10000>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9163-fmc-ebz_m2_l8.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9163-fmc-ebz_m2_l8.dts
@@ -73,6 +73,7 @@
 
 		tx_dma: tx-dmac@9c420000 {
 			#dma-cells = <1>;
+			dma-coherent;
 			compatible = "adi,axi-dmac-1.00.a";
 			adi,cyclic;
 			reg = <0x9c420000 0x10000>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9164-fmc-ebz_m2_s2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9164-fmc-ebz_m2_s2.dts
@@ -74,6 +74,7 @@
 
 		tx_dma: tx-dmac@9c420000 {
 			#dma-cells = <1>;
+			dma-coherent;
 			compatible = "adi,axi-dmac-1.00.a";
 			adi,cyclic;
 			reg = <0x9c420000 0x10000>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9172-fmc-ebz.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9172-fmc-ebz.dts
@@ -45,6 +45,7 @@
 
 		tx_dma: tx-dmac@9c420000 {
 			#dma-cells = <1>;
+			dma-coherent;
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x9c420000 0x10000>;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms2-3.dts
@@ -47,6 +47,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
@@ -56,6 +57,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9361-fmcomms5.dts
@@ -35,6 +35,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -44,6 +45,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9364-fmcomms4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9364-fmcomms4.dts
@@ -46,6 +46,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
@@ -55,6 +56,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9694.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9694.dts
@@ -63,6 +63,7 @@
 
 		rx_dma: rx-dmac@9c400000 {
 			#dma-cells = <1>;
+			dma-coherent;
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x9c400000 0x1000>;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9695.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9695.dts
@@ -63,6 +63,7 @@
 
 		rx_dma: rx-dmac@9c400000 {
 			#dma-cells = <1>;
+			dma-coherent;
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x9c400000 0x1000>;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9783.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9783.dts
@@ -48,6 +48,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9002-rx2tx2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9002-rx2tx2.dts
@@ -39,6 +39,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x84A30000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
@@ -47,6 +48,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x84A50000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9002.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9002.dts
@@ -38,6 +38,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x84A30000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
@@ -46,6 +47,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x84A40000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
@@ -54,6 +56,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x84A50000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
@@ -62,6 +65,7 @@
 			compatible = "adi,axi-dmac-1.00.a";
 			reg = <0x84A60000 0x10000>;
 			#dma-cells = <1>;
+			dma-coherent;
 			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9008-1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9008-1.dts
@@ -47,6 +47,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9008-2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9008-2.dts
@@ -47,6 +47,7 @@
 			reg = <0x9c440000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -56,6 +57,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009-fmcomms8.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009-fmcomms8.dts
@@ -206,6 +206,7 @@
 			reg = <0x9d420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -215,6 +216,7 @@
 			reg = <0x9d440000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -224,6 +226,7 @@
 			reg = <0x9d400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009.dts
@@ -65,6 +65,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -74,6 +75,7 @@
 			reg = <0x9c440000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -83,6 +85,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9025.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9025.dts
@@ -257,6 +257,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -266,6 +267,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371.dts
@@ -46,6 +46,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -55,6 +56,7 @@
 			reg = <0x9c440000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
@@ -64,6 +66,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 73>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq2.dts
@@ -47,6 +47,7 @@
 			reg = <0x9c400000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
@@ -56,6 +57,7 @@
 			reg = <0x9c420000 0x10000>;
 			#dma-cells = <1>;
 			#clock-cells = <0>;
+			dma-coherent;
 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&zynqmp_clk 71>;
 		};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmcdaq3.dts
