iio: adc: ad4000: Add support for adjustable sampling rate

Some ADI HDL projects include a PWM generator and a clock generator IP
in addition to the SPI engine. The clock generator is needed for the PWM.
The PWM IP triggers the SPI engine offload module which in turn
triggers ADC device conversions. With that, it is possible to set a
particular sample rate for the device by setting the proper PWM duty
cycle and related state parameters.
Add support for adjustable device sampling rate when PWM and clock
generators are available.

Signed-off-by: Marcelo Schmitt <marcelo.schmitt@analog.com>

Author: machschmitt