diff --git a/docs/projects/ad4052_ardz/index.rst b/docs/projects/ad4052_ardz/index.rst
index 3468bf508f..a1990eec34 100644
--- a/docs/projects/ad4052_ardz/index.rst
+++ b/docs/projects/ad4052_ardz/index.rst
@@ -1,4 +1,4 @@
-.. _ad4052-ardz:
+.. _ad4052_ardz:
AD4052-ARDZ HDL project
================================================================================
@@ -7,7 +7,7 @@ Overview
--------------------------------------------------------------------------------
The HDL reference design for the :adi:`AD4050`, :adi:`AD4052`, :adi:`AD4056`, and
-:adi:`AD4058` .
+:adi:`AD4058`.
They are versatile, 16-bit/12-bit, successive approximation register (SAR)
analog-to-digital converters (ADCs) that enable low-power, high-density data
acquisition solutions without sacrificing precision. These ADCs offer a unique
@@ -21,9 +21,6 @@ battery-powered, compact data acquisition and edge sensing applications.
The :adi:`EVAL-AD4050-ARDZ`/:adi:`EVAL-AD4052-ARDZ` evaluation boards enable
quick and easy evaluation of the performance and features of the :adi:`AD4050`
or the :adi:`AD4052`, respectively.
-The AD4050 and AD4052 are compact, low power, 12-bit or 16-bit (respectively)
-Easy Drive successive approximation register (SAR) analog-to-digital converters
-(ADCs).
This project has a :ref:`spi_engine` instance to control and acquire data from
the precision ADC.
diff --git a/docs/projects/ad4062_ardz/ad4062_hdl.svg b/docs/projects/ad4062_ardz/ad4062_hdl.svg
new file mode 100644
index 0000000000..ab1aee1d08
--- /dev/null
+++ b/docs/projects/ad4062_ardz/ad4062_hdl.svg
@@ -0,0 +1,2430 @@
+
+
+
+
diff --git a/docs/projects/ad4062_ardz/index.rst b/docs/projects/ad4062_ardz/index.rst
new file mode 100644
index 0000000000..c763362628
--- /dev/null
+++ b/docs/projects/ad4062_ardz/index.rst
@@ -0,0 +1,279 @@
+.. _ad4062_ardz:
+
+AD4062-ARDZ HDL project
+================================================================================
+
+Overview
+--------------------------------------------------------------------------------
+
+The HDL reference design for the :adi:`AD4060`, :adi:`AD4062`.
+They are versatile, 16-bit/12-bit, successive approximation register (SAR)
+analog-to-digital converters (ADCs) that enable low-power, high-density data
+acquisition solutions without sacrificing precision. These ADCs offer a unique
+balance of performance and power efficiency, plus innovative features for
+seamlessly switching between high-resolution and low-power modes tailored to the
+immediate needs of the system.
+
+The :adi:`AD4060 `/:adi:`AD4062 `
+evaluation boards enable quick and easy evaluation of the performance and
+features of the :adi:`AD4060` or the :adi:`AD4062`, respectively.
+
+This project has an :ref:`i3c_controller` instance to control and acquire data
+from the precision ADC.
+
+Supported boards
+-------------------------------------------------------------------------------
+
+- :adi:`EVAL-AD4060`
+- :adi:`EVAL-AD4062`
+
+Supported devices
+-------------------------------------------------------------------------------
+
+- :adi:`AD4060`
+- :adi:`AD4062`
+
+Supported carriers
+-------------------------------------------------------------------------------
+
+- `Cora Z7S `__
+ Arduino shield connector
+- :intel:`DE10-Nano `
+ Arduino shield connector
+
+Block design
+-------------------------------------------------------------------------------
+
+Block diagram
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The data path and clock domains are depicted in the below diagram:
+
+.. image:: ad4062_hdl.svg
+ :width: 800
+ :align: center
+ :alt: AD4062-ARDZ block diagram
+
+Configuration modes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``OFFLOAD`` parameter is used to enable the offload interface, as well as
+adding the :ref:`axi_dmac` and :ref:`axi_pwm_gen` to the design.
+
+- 0 - no offload (default)
+- 1 - with default
+
+CPU/Memory interconnects addresses
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The addresses are dependent on the architecture of the FPGA, having an offset
+added to the base address from HDL (see more at :ref:`architecture`).
+
+.. table:: Cora Z7S
+
+ =============== ===========
+ Instance Address
+ =============== ===========
+ i3c_controller 0x44A0_0000
+ i3c_offload_dma 0x44A3_0000
+ i3c_offload_pwm 0x44B0_0000
+ =============== ===========
+
+.. table:: DE10-Nano
+
+ =============== ===========
+ Instance Address
+ =============== ===========
+ i3c_offload_dma 0x0002_0000
+ i3c_controller 0x0003_0000
+ i3c_offload_pwm 0x0004_0000
+ =============== ===========
+
+I3C/I2C connections
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table:: Cora Z7s
+ :header-rows: 1
+
+ * - I2C/I3C subordinate
+ - address
+ - I3C manager
+ * - EEPROM
+ - 0x52
+ - i3c_controller
+ * - ADC
+ - i3c_controller
+ - Provisioned PID
+
+.. list-table:: DE10-Nano
+ :header-rows: 1
+
+ * - I2C/I3C subordinate
+ - EEPROM
+ - I3C manager
+ * - EEPROM
+ - 0x52
+ - i3c_controller
+ * - ADC
+ - i3c_controller
+ - Provisioned PID
+
+.. caution::
+
+ By default, the DE10-Nano does not populate the passive pull-up in the SDA
+ lane (DNI). Either populate the DE10-Nano's resistor R1 with a 2.2k ohm
+ resistor, or use the ``WEAK_PULL_UP_RESISTOR`` to the ``i3c_sda`` pin.
+
+Device address considering the EEPROM address pins ``A0=0``, ``A1=1``, ``A2=0``.
+For the ADC, check the part datasheet and the set address pins.
+
+GPIOs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Software GPIO number is calculated as follows:
+
+- Cora Z7S: the offset is 54
+
+.. list-table::
+ :widths: 25 25 25 25
+ :header-rows: 2
+
+ * - GPIO signal
+ - Direction
+ - HDL GPIO EMIO
+ - Software GPIO
+ * -
+ - (from FPGA view)
+ -
+ - Zynq-7000
+ * - adc_gp1
+ - INOUT
+ - 33
+ - 87
+ * - adc_gp0
+ - INOUT
+ - 32
+ - 86
+
+- DE10-Nano: the offset is 32
+
+.. list-table::
+ :widths: 25 25 25 25
+ :header-rows: 2
+
+ * - GPIO signal
+ - Direction
+ - HDL GPIO EMIO
+ - Software GPIO
+ * -
+ - (from FPGA view)
+ -
+ -
+ * - adc_gp1
+ - INPUT
+ - 33
+ - 1
+ * - adc_gp0
+ - INPUT
+ - 32
+ - 0
+
+Interrupts
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Below are the Programmable Logic interrupts used in this project.
+
+=================== === ========== ===========
+Instance name HDL Linux Zynq Actual Zynq
+=================== === ========== ===========
+axi_adc_dma 13 57 89
+i3c_controller 12 56 88
+=================== === ========== ===========
+
+================ === =============== ================
+Instance name HDL Linux DE10-Nano Actual DE10-Nano
+================ === =============== ================
+i3c_controller 5 45 77
+axi_dmac 4 44 76
+================ === =============== ================
+
+Building the HDL project
+-------------------------------------------------------------------------------
+
+The design is built upon ADI's generic HDL reference design framework.
+ADI distributes the bit/elf files of these projects as part of the
+:dokuwiki:`ADI Kuiper Linux `.
+If you want to build the sources, ADI makes them available on the
+:git-hdl:`HDL repository `. To get the source you must
+`clone `__
+the HDL repository, and then build the project as follows:
+
+**Linux/Cygwin/WSL**
+
+.. shell::
+
+ $cd hdl/projects/ad4062_ardz/coraz7s
+ $make
+
+.. shell::
+
+ $cd hdl/projects/ad4062_ardz/de10nano
+ $make
+
+A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
+
+Resources
+-------------------------------------------------------------------------------
+
+Hardware related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Product datasheets:
+
+ - :adi:`AD4060`
+ - :adi:`AD4062`
+
+HDL related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- :git-hdl:`AD4062-ARDZ HDL project source code `
+
+.. list-table::
+ :widths: 30 35 35
+ :header-rows: 1
+
+ * - IP name
+ - Source code link
+ - Documentation link
+ * - AXI_SYSID
+ - :git-hdl:`library/axi_sysid `
+ - :ref:`here `
+ * - AXI_PWM_GEN
+ - :git-hdl:`library/axi_pwm_gen `
+ - :ref:`here `
+ * - AXI_DMAC
+ - :git-hdl:`library/axi_dmac `
+ - :ref:`here `
+ * - AXI_HDMI_TX
+ - :git-hdl:`library/axi_hdmi_tx ` *
+ - :ref:`here `
+ * - I3C_CONTROLLER_HOST_INTERFACE
+ - :git-hdl:`library/i3c_controller/i3c_controller_host_interface`
+ - :ref:`here `
+ * - I3C_CONTROLLER_CORE
+ - :git-hdl:`library/i3c_controller/i3c_controller_core`
+ - :ref:`here `
+ * - SYSID_ROM
+ - :git-hdl:`library/sysid_rom `
+ - :ref:`here `
+
+.. admonition:: Legend
+ :class: note
+
+ - ``*`` instantiated only for DE10-Nano
+
+- :ref:`I3C Controller documentation `
+
+.. include:: ../common/more_information.rst
+
+.. include:: ../common/support.rst
diff --git a/docs/projects/index.rst b/docs/projects/index.rst
index 787aaba5ce..86caa2d8b5 100644
--- a/docs/projects/index.rst
+++ b/docs/projects/index.rst
@@ -23,6 +23,7 @@ Contents
AD353XR
AD35XXR-EVB
AD4052-ARDZ
+ AD4062-ARDZ
AD408X-FMC-EVB
AD4110-SDZ
AD411x-AD717x
diff --git a/projects/ad4052_ardz/README.md b/projects/ad4052_ardz/README.md
index cf6e001b80..6b8b9662ef 100644
--- a/projects/ad4052_ardz/README.md
+++ b/projects/ad4052_ardz/README.md
@@ -1,17 +1,17 @@
# AD4052-ARDZ HDL Project
-- Evaluation board product page: [EVAL-AD4052-ARDZ](https://www.analog.com/eval-ad4052-ardz)
+- Evaluation board product page: [EVAL-AD4050-ARDZ](https://www.analog.com/eval-ad4050-ardz)/[EVAL-AD4052-ARDZ](https://www.analog.com/eval-ad4052-ardz)
- System documentation:TO BE ADDED
- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad4052_ardz/index.html
## Supported parts
-| Part name | Description |
-|--------------------------------------------|------------------------------------------------------------------|
-| [AD4050](https://www.analog.com/ad4050) | Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC |
-| [AD4052](https://www.analog.com/ad4052) | Compact, Low Power, 16-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC |
-| [AD4056](https://www.analog.com/ad4056) | Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC |
-| [AD4058](https://www.analog.com/ad4058) | Compact, Low Power, 16-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC |
+| Part name | Description |
+|--------------------------------------------|---------------------------------------------------------|
+| [AD4050](https://www.analog.com/ad4050) | Compact, Low Power, 12-Bit, 2 MSPS Easy Drive SAR ADC |
+| [AD4052](https://www.analog.com/ad4052) | Compact, Low Power, 16-Bit, 2 MSPS Easy Drive SAR ADC |
+| [AD4056](https://www.analog.com/ad4056) | Compact, Low Power, 12-Bit, 500 kSPS Easy Drive SAR ADC |
+| [AD4058](https://www.analog.com/ad4058) | Compact, Low Power, 16-Bit, 500 kSPS Easy Drive SAR ADC |
## Building the project
diff --git a/projects/ad4062_ardz/Makefile b/projects/ad4062_ardz/Makefile
new file mode 100644
index 0000000000..68a7ed005c
--- /dev/null
+++ b/projects/ad4062_ardz/Makefile
@@ -0,0 +1,7 @@
+####################################################################################
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+include ../scripts/project-toplevel.mk
diff --git a/projects/ad4062_ardz/README.md b/projects/ad4062_ardz/README.md
new file mode 100644
index 0000000000..635fbe79b9
--- /dev/null
+++ b/projects/ad4062_ardz/README.md
@@ -0,0 +1,16 @@
+# AD4062-ARDZ HDL Project
+
+- Evaluation board product page: [EVAL-AD4060/EVAL-AD4062](https://www.analog.com/eval-ad4060-eval-ad4062)
+- System documentation:TO BE ADDED
+- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad4062_ardz/index.html
+
+## Supported parts
+
+| Part name | Description |
+|--------------------------------------------|------------------------------------------------------------|
+| [AD4060](https://www.analog.com/ad4060) | Compact, Low Power, 12-Bit, 2 MSPS kSPS Easy Drive SAR ADC |
+| [AD4062](https://www.analog.com/ad4062) | Compact, Low Power, 16-Bit, 2 MSPS kSPS Easy Drive SAR ADC |
+
+## Building the project
+
+Please enter the folder for the FPGA carrier you want to use and read the README.md.
\ No newline at end of file
diff --git a/projects/ad4062_ardz/common/ad4062_bd.tcl b/projects/ad4062_ardz/common/ad4062_bd.tcl
new file mode 100644
index 0000000000..32075cc5e9
--- /dev/null
+++ b/projects/ad4062_ardz/common/ad4062_bd.tcl
@@ -0,0 +1,65 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_bd_intf_port -mode Master -vlnv analog.com:interface:i3c_controller_rtl:1.0 i3c
+
+source $ad_hdl_dir/library/i3c_controller/scripts/i3c_controller_bd.tcl
+
+set async_clk 0
+set i2c_mod 4
+set offload $ad_project_params(OFFLOAD)
+set max_devs 16
+
+i3c_controller_create i3c $async_clk $i2c_mod $offload $max_devs
+
+if {$offload == 1} {
+ # pwm to trigger on offload data burst
+ ad_ip_instance axi_pwm_gen i3c_offload_pwm
+ ad_ip_parameter i3c_offload_pwm CONFIG.PULSE_0_PERIOD 120
+ ad_ip_parameter i3c_offload_pwm CONFIG.PULSE_0_WIDTH 1
+
+ # dma to receive offload data stream
+ ad_ip_instance axi_dmac i3c_offload_dma
+ ad_ip_parameter i3c_offload_dma CONFIG.DMA_TYPE_SRC 1
+ ad_ip_parameter i3c_offload_dma CONFIG.DMA_TYPE_DEST 0
+ ad_ip_parameter i3c_offload_dma CONFIG.CYCLIC 0
+ ad_ip_parameter i3c_offload_dma CONFIG.SYNC_TRANSFER_START 0
+ ad_ip_parameter i3c_offload_dma CONFIG.AXI_SLICE_SRC 0
+ ad_ip_parameter i3c_offload_dma CONFIG.AXI_SLICE_DEST 1
+ ad_ip_parameter i3c_offload_dma CONFIG.DMA_2D_TRANSFER 0
+ ad_ip_parameter i3c_offload_dma CONFIG.DMA_DATA_WIDTH_SRC 32
+ ad_ip_parameter i3c_offload_dma CONFIG.DMA_DATA_WIDTH_DEST 64
+
+ ad_connect sys_cpu_clk i3c_offload_pwm/ext_clk
+ ad_connect sys_cpu_clk i3c_offload_pwm/s_axi_aclk
+ ad_connect sys_cpu_resetn i3c_offload_pwm/s_axi_aresetn
+ ad_connect i3c_offload_pwm/pwm_0 i3c/trigger
+
+ ad_connect i3c_offload_dma/s_axis i3c/offload_sdi
+}
+ad_connect i3c/m_i3c i3c
+
+ad_connect sys_cpu_clk i3c/clk
+ad_connect sys_cpu_resetn i3c/reset_n
+if {$offload == 1} {
+ ad_connect sys_cpu_clk i3c_offload_dma/s_axis_aclk
+ ad_connect sys_cpu_resetn i3c_offload_dma/m_dest_axi_aresetn
+}
+
+ad_cpu_interconnect 0x44a00000 i3c/host_interface
+if {$offload == 1} {
+ ad_cpu_interconnect 0x44a30000 i3c_offload_dma
+ ad_cpu_interconnect 0x44b00000 i3c_offload_pwm
+}
+
+if {$offload == 1} {
+ ad_cpu_interrupt "ps-13" "mb-13" i3c_offload_dma/irq
+}
+ad_cpu_interrupt "ps-12" "mb-12" i3c/irq
+
+if {$offload == 1} {
+ ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
+ ad_mem_hp1_interconnect sys_cpu_clk i3c_offload_dma/m_dest_axi
+}
diff --git a/projects/ad4062_ardz/common/ad4062_qsys.tcl b/projects/ad4062_ardz/common/ad4062_qsys.tcl
new file mode 100755
index 0000000000..a514c40536
--- /dev/null
+++ b/projects/ad4062_ardz/common/ad4062_qsys.tcl
@@ -0,0 +1,90 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/library/i3c_controller/scripts/i3c_controller_qsys.tcl
+
+# disable I2C1
+
+set_instance_parameter_value sys_hps {I2C1_Mode} {N/A}
+set_instance_parameter_value sys_hps {I2C1_PinMuxing} {Unused}
+
+set async_clk 0
+set i2c_mod 4
+set offload $ad_project_params(OFFLOAD)
+set max_devs 16
+
+i3c_controller_create i3c $async_clk $i2c_mod $offload $max_devs
+
+if {$offload} {
+ # axi pwm gen
+
+ add_instance i3c_offload_pwm axi_pwm_gen
+ set_instance_parameter_value i3c_offload_pwm {N_PWMS} {1}
+ set_instance_parameter_value i3c_offload_pwm {PULSE_0_PERIOD} {120}
+ set_instance_parameter_value i3c_offload_pwm {PULSE_0_WIDTH} {1}
+
+ # receive dma
+
+ add_instance i3c_offload_dma axi_dmac
+ set_instance_parameter_value i3c_offload_dma {DMA_TYPE_SRC} {1}
+ set_instance_parameter_value i3c_offload_dma {DMA_TYPE_DEST} {0}
+ set_instance_parameter_value i3c_offload_dma {AXI_SLICE_SRC} {0}
+ set_instance_parameter_value i3c_offload_dma {AXI_SLICE_DEST} {1}
+ set_instance_parameter_value i3c_offload_dma {DMA_DATA_WIDTH_SRC} {32}
+ set_instance_parameter_value i3c_offload_dma {DMA_DATA_WIDTH_DEST} {64}
+}
+
+# clocks
+
+add_connection sys_clk.clk i3c_host_interface.s_axi_clock
+add_connection sys_clk.clk i3c_core.if_clk
+if {$offload} {
+ add_connection sys_clk.clk i3c_offload_dma.s_axi_clock
+ add_connection sys_clk.clk i3c_offload_dma.if_s_axis_aclk
+ add_connection sys_clk.clk i3c_offload_dma.m_dest_axi_clock
+ add_connection sys_clk.clk i3c_offload_pwm.s_axi_clock
+ add_connection sys_clk.clk i3c_offload_pwm.if_ext_clk
+}
+
+# resets
+
+add_connection sys_clk.clk_reset i3c_host_interface.s_axi_reset
+if {$offload} {
+ add_connection sys_clk.clk_reset i3c_offload_dma.s_axi_reset
+ add_connection sys_clk.clk_reset i3c_offload_dma.m_dest_axi_reset
+ add_connection sys_clk.clk_reset i3c_offload_pwm.s_axi_reset
+}
+
+# interfaces
+
+if {$offload} {
+ add_connection i3c_host_interface.offload_sdi i3c_offload_dma.s_axis
+ add_connection i3c_offload_pwm.if_pwm_0 i3c_host_interface.if_offload_trigger
+}
+
+# exported interface
+
+set_interface_property i3c EXPORT_OF i3c_core.i3c
+
+# cpu interconnects
+
+ad_cpu_interconnect 0x00030000 i3c_host_interface.s_axi
+if {$offload} {
+ ad_cpu_interconnect 0x00020000 i3c_offload_dma.s_axi
+ ad_cpu_interconnect 0x00040000 i3c_offload_pwm.s_axi
+}
+
+# dma interconnect
+
+if {$offload} {
+ ad_dma_interconnect i3c_offload_dma.m_dest_axi
+}
+
+# interrupts
+
+if {$offload} {
+ ad_cpu_interrupt 4 i3c_offload_dma.interrupt_sender
+}
+ad_cpu_interrupt 5 i3c_host_interface.interrupt_sender
diff --git a/projects/ad4062_ardz/coraz7s/Makefile b/projects/ad4062_ardz/coraz7s/Makefile
new file mode 100644
index 0000000000..4012ad2bfa
--- /dev/null
+++ b/projects/ad4062_ardz/coraz7s/Makefile
@@ -0,0 +1,24 @@
+####################################################################################
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad4062_ardz_coraz7s
+
+M_DEPS += ../common/ad4062_bd.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
+M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
+M_DEPS += ../../../library/i3c_controller/scripts/i3c_controller_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_pwm_gen
+LIB_DEPS += axi_sysid
+LIB_DEPS += i3c_controller/i3c_controller_core
+LIB_DEPS += i3c_controller/i3c_controller_host_interface
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-xilinx.mk
diff --git a/projects/ad4062_ardz/coraz7s/README.md b/projects/ad4062_ardz/coraz7s/README.md
new file mode 100644
index 0000000000..eb6cd96fc3
--- /dev/null
+++ b/projects/ad4062_ardz/coraz7s/README.md
@@ -0,0 +1,8 @@
+# AD4062-ARDZ/CORAZ7S HDL Project
+
+## Building the project
+
+```
+cd projects/ad4062_ardz/coraz7s
+make
+```
\ No newline at end of file
diff --git a/projects/ad4062_ardz/coraz7s/system_bd.tcl b/projects/ad4062_ardz/coraz7s/system_bd.tcl
new file mode 100644
index 0000000000..4ddbe5b3ae
--- /dev/null
+++ b/projects/ad4062_ardz/coraz7s/system_bd.tcl
@@ -0,0 +1,22 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+
+# Remove common IIC interface to add I3C controller
+delete_bd_objs [get_bd_intf_nets axi_iic_ard_IIC] [get_bd_intf_ports iic_ard]
+delete_bd_objs [get_bd_nets axi_iic_ard_iic2intc_irpt] [get_bd_intf_nets axi_gp0_interconnect_M00_AXI] [get_bd_cells axi_iic_ard]
+
+source ../common/ad4062_bd.tcl
+
+set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path";
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file
diff --git a/projects/ad4062_ardz/coraz7s/system_constr.xdc b/projects/ad4062_ardz/coraz7s/system_constr.xdc
new file mode 100644
index 0000000000..0ae77d85c7
--- /dev/null
+++ b/projects/ad4062_ardz/coraz7s/system_constr.xdc
@@ -0,0 +1,39 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports adc_gp0]
+set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports adc_gp1]
+
+# clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
+set i3c_clk clk_fpga_0
+
+# Input data driven the peripherals toggles every 4 cycles max (PP) of the capture clock
+# gets registered by rx_reg
+set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -setup 4
+set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -hold 3
+
+# Output data toggles every 2 cycles max of the capture clock (PP)
+set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -setup 2
+set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -hold 1
+set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -setup 2
+set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -hold 1
+
+# Notes
+# tcr/tcf rising/fall time for SCL is 150e06 * 1 / fSCL, at fSCL = 12.5 MHz => 12ns, at fSCL = 6.25 MHz, 24ns.
+# and t_SCO has a minimum/default value of 8ns and max of 12 ns
+# The input_delay and output_delay are selected for the worst case scenario.
+# One i3c_clk clock cycle is included in the sdo signal to ensure thd_pp(min) is met.
+set tsco_max 12;
+set tsco_min 8;
+set trc_dly_max 1;
+set trc_dly_min 0;
+set_input_delay -clock $i3c_clk -max [expr $tsco_max + $trc_dly_max] [get_ports i3c_sda]
+set_input_delay -clock $i3c_clk -min [expr $tsco_min + $trc_dly_min] [get_ports i3c_sda]
+set tsu 2;
+set thd 0;
+set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_sda]
+set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_sda]
+set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_scl]
+set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_scl]
diff --git a/projects/ad4062_ardz/coraz7s/system_project.tcl b/projects/ad4062_ardz/coraz7s/system_project.tcl
new file mode 100644
index 0000000000..b3d022b593
--- /dev/null
+++ b/projects/ad4062_ardz/coraz7s/system_project.tcl
@@ -0,0 +1,33 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+# get_env_param retrieves parameter value from the environment if exists,
+# other case use the default value.
+#
+# How to use over-writable parameters from the environment:
+#
+# e.g.
+# make OFFLOAD=1
+#
+# Parameter description:
+#
+# OFFLOAD : Enable offload mode, includes AXI_DMAC and AXI_PWM to the design
+# 1 - enabled
+# 0 - disabled (default)
+
+adi_project ad4062_ardz_coraz7s 0 [list \
+ OFFLOAD [get_env_param OFFLOAD 0]]
+
+adi_project_files ad4062_ardz_coraz7s [list \
+ "$ad_hdl_dir/library/common/ad_iobuf.v" \
+ "system_top.v" \
+ "system_constr.xdc" \
+ "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
+
+adi_project_run ad4062_ardz_coraz7s
diff --git a/projects/ad4062_ardz/coraz7s/system_top.v b/projects/ad4062_ardz/coraz7s/system_top.v
new file mode 100644
index 0000000000..449f05e11d
--- /dev/null
+++ b/projects/ad4062_ardz/coraz7s/system_top.v
@@ -0,0 +1,168 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+// 1. The GNU General Public License version 2 as published by the
+// Free Software Foundation, which can be found in the top level directory
+// of this repository (LICENSE_GPL2), and also online at:
+//
+//
+// OR
+//
+// 2. An ADI specific BSD license, which can be found in the top level directory
+// of this repository (LICENSE_ADIBSD), and also on-line at:
+// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+// This will allow to generate bit files and not release the source code,
+// as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+ inout [14:0] ddr_addr,
+ inout [ 2:0] ddr_ba,
+ inout ddr_cas_n,
+ inout ddr_ck_n,
+ inout ddr_ck_p,
+ inout ddr_cke,
+ inout ddr_cs_n,
+ inout [ 3:0] ddr_dm,
+ inout [31:0] ddr_dq,
+ inout [ 3:0] ddr_dqs_n,
+ inout [ 3:0] ddr_dqs_p,
+ inout ddr_odt,
+ inout ddr_ras_n,
+ inout ddr_reset_n,
+ inout ddr_we_n,
+
+ inout fixed_io_ddr_vrn,
+ inout fixed_io_ddr_vrp,
+ inout [53:0] fixed_io_mio,
+ inout fixed_io_ps_clk,
+ inout fixed_io_ps_porb,
+ inout fixed_io_ps_srstb,
+
+ inout [ 1:0] btn,
+ inout [ 5:0] led,
+
+ output iic_ard_scl,
+ inout iic_ard_sda,
+
+ inout adc_gp1,
+ inout adc_gp0
+);
+
+ // internal signals
+
+ wire [63:0] gpio_i;
+ wire [63:0] gpio_o;
+ wire [63:0] gpio_t;
+ wire i3c_sdo;
+ wire i3c_sdi;
+ wire i3c_t;
+
+ // instantiations
+
+ assign gpio_i[31:8] = gpio_o[31:8];
+ assign gpio_i[63:34] = gpio_o[63:34];
+
+ ad_iobuf #(
+ .DATA_WIDTH(2)
+ ) i_iobuf_gp (
+ .dio_t(gpio_t[33:32]),
+ .dio_i(gpio_o[33:32]),
+ .dio_o(gpio_i[33:32]),
+ .dio_p({adc_gp1, // device ready then ~data ready
+ adc_gp0})); // threshold event
+
+ ad_iobuf #(
+ .DATA_WIDTH(1)
+ ) i_iobuf_sda (
+ .dio_t(i3c_t),
+ .dio_i(i3c_sdo),
+ .dio_o(i3c_sdi),
+ .dio_p(iic_ard_sda));
+
+ ad_iobuf #(
+ .DATA_WIDTH(2)
+ ) i_iobuf_buttons (
+ .dio_t(gpio_t[1:0]),
+ .dio_i(gpio_o[1:0]),
+ .dio_o(gpio_i[1:0]),
+ .dio_p(btn));
+
+ ad_iobuf #(
+ .DATA_WIDTH(6)
+ ) i_iobuf_leds (
+ .dio_t(gpio_t[7:2]),
+ .dio_i(gpio_o[7:2]),
+ .dio_o(gpio_i[7:2]),
+ .dio_p(led));
+
+ system_wrapper i_system_wrapper (
+ .ddr_addr (ddr_addr),
+ .ddr_ba (ddr_ba),
+ .ddr_cas_n (ddr_cas_n),
+ .ddr_ck_n (ddr_ck_n),
+ .ddr_ck_p (ddr_ck_p),
+ .ddr_cke (ddr_cke),
+ .ddr_cs_n (ddr_cs_n),
+ .ddr_dm (ddr_dm),
+ .ddr_dq (ddr_dq),
+ .ddr_dqs_n (ddr_dqs_n),
+ .ddr_dqs_p (ddr_dqs_p),
+ .ddr_odt (ddr_odt),
+ .ddr_ras_n (ddr_ras_n),
+ .ddr_reset_n (ddr_reset_n),
+ .ddr_we_n (ddr_we_n),
+ .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+ .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+ .fixed_io_mio (fixed_io_mio),
+ .fixed_io_ps_clk (fixed_io_ps_clk),
+ .fixed_io_ps_porb (fixed_io_ps_porb),
+ .fixed_io_ps_srstb (fixed_io_ps_srstb),
+ .gpio_i (gpio_i),
+ .gpio_o (gpio_o),
+ .gpio_t (gpio_t),
+ .spi0_clk_i (1'b0),
+ .spi0_clk_o (),
+ .spi0_csn_0_o (),
+ .spi0_csn_1_o (),
+ .spi0_csn_2_o (),
+ .spi0_csn_i (1'b1),
+ .spi0_sdi_i (1'b0),
+ .spi0_sdo_i (1'b0),
+ .spi0_sdo_o (),
+ .spi1_clk_i (1'b0),
+ .spi1_clk_o (),
+ .spi1_csn_0_o (),
+ .spi1_csn_1_o (),
+ .spi1_csn_2_o (),
+ .spi1_csn_i (1'b1),
+ .spi1_sdi_i (1'b0),
+ .spi1_sdo_i (1'b0),
+ .spi1_sdo_o (),
+ .i3c_scl (iic_ard_scl),
+ .i3c_sdi (i3c_sdi),
+ .i3c_sdo (i3c_sdo),
+ .i3c_t (i3c_t));
+
+endmodule
diff --git a/projects/ad4062_ardz/de10nano/Makefile b/projects/ad4062_ardz/de10nano/Makefile
new file mode 100755
index 0000000000..7a6e17c0d9
--- /dev/null
+++ b/projects/ad4062_ardz/de10nano/Makefile
@@ -0,0 +1,22 @@
+####################################################################################
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad4062_ardz_de10nano
+
+M_DEPS += ../common/ad4062_qsys.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl
+M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl
+M_DEPS += ../../../library/i3c_controller/scripts/i3c_controller_qsys.tcl
+
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_hdmi_tx
+LIB_DEPS += axi_sysid
+LIB_DEPS += i3c_controller/i3c_controller_core
+LIB_DEPS += i3c_controller/i3c_controller_host_interface
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-intel.mk
diff --git a/projects/ad4062_ardz/de10nano/README.md b/projects/ad4062_ardz/de10nano/README.md
new file mode 100644
index 0000000000..9186c033db
--- /dev/null
+++ b/projects/ad4062_ardz/de10nano/README.md
@@ -0,0 +1,8 @@
+# AD4062-ARDZ/DE10NANO HDL Project
+
+## Building the project
+
+```
+cd projects/ad4062_ardz/de10nano
+make
+```
\ No newline at end of file
diff --git a/projects/ad4062_ardz/de10nano/system_constr.sdc b/projects/ad4062_ardz/de10nano/system_constr.sdc
new file mode 100755
index 0000000000..7dea998942
--- /dev/null
+++ b/projects/ad4062_ardz/de10nano/system_constr.sdc
@@ -0,0 +1,42 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
+create_clock -period "16.666 ns" -name usb1_clk [get_ports {usb1_clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set i3c_clk sys_clk
+
+# Input data driven the peripherals toggles every 4 cycles max (PP) of the capture clock
+# gets registered by rx_reg
+set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -setup 4
+set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -hold 3
+
+# Output data toggles every 2 cycles max of the capture clock (PP)
+set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -setup 2
+set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -hold 1
+set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -setup 2
+set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -hold 1
+
+
+# Notes
+# tcr/tcf rising/fall time for SCL is 150e06 * 1 / fSCL, at fSCL = 12.5 MHz => 12ns, at fSCL = 6.25 MHz, 24ns.
+# and t_SCO has a minimum/default value of 8ns and max of 12 ns
+# The input_delay and output_delay are selected for the worst case scenario.
+# One i3c_clk clock cycle is included in the sdo signal to ensure thd_pp(min) is met.
+set tsco_max 12;
+set tsco_min 8;
+set trc_dly_max 1;
+set trc_dly_min 0;
+set_input_delay -clock $i3c_clk -max [expr $tsco_max + $trc_dly_max] [get_ports i3c_sda]
+set_input_delay -clock $i3c_clk -min [expr $tsco_min + $trc_dly_min] [get_ports i3c_sda]
+set tsu 2;
+set thd 0;
+set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_sda]
+set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_sda]
+set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_scl]
+set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_scl]
diff --git a/projects/ad4062_ardz/de10nano/system_project.tcl b/projects/ad4062_ardz/de10nano/system_project.tcl
new file mode 100755
index 0000000000..2eec2195f6
--- /dev/null
+++ b/projects/ad4062_ardz/de10nano/system_project.tcl
@@ -0,0 +1,65 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+set REQUIRED_QUARTUS_VERSION 22.1std.0
+set QUARTUS_PRO_ISUSED 0
+source ../../../scripts/adi_env.tcl
+source ../../scripts/adi_project_intel.tcl
+
+# get_env_param retrieves parameter value from the environment if exists,
+# other case use the default value.
+#
+# How to use over-writable parameters from the environment:
+#
+# e.g.
+# make OFFLOAD=1
+#
+# Parameter description:
+#
+# OFFLOAD : Enable offload mode, includes AXI_DMAC and AXI_PWM to the design
+# 1 - enabled
+# 0 - disabled (default)
+
+adi_project ad4062_ardz_de10nano [list \
+ OFFLOAD [get_env_param OFFLOAD 0]]
+
+source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl
+
+# I3C interface bus
+
+set_location_assignment PIN_AG11 -to i3c_scl ; ## Arduino_IO15
+set_location_assignment PIN_AH9 -to i3c_sda ; ## Arduino_IO14
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i3c_scl
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i3c_sda
+
+# Enable if not using an external 2.2k ohm passive pull-up
+#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i3c_sda
+
+# reset and GPIO signals
+
+set_location_assignment PIN_AE15 -to common_shutdown ; ## Arduino_IO9
+set_location_assignment PIN_AH8 -to common_reset_adc ; ## Arduino_IO7
+set_location_assignment PIN_U13 -to common_csb_aux ; ## Arduino_IO5
+set_location_assignment PIN_U14 -to common_sw_ff ; ## Arduino_IO4
+set_location_assignment PIN_AG9 -to common_drdy_aux ; ## Arduino_IO3
+set_location_assignment PIN_AF13 -to common_blue_led ; ## Arduino_IO1
+set_location_assignment PIN_AG13 -to common_yellow_led ; ## Arduino_IO0
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to common_shutdown
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to common_reset_adc
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to common_csb_aux
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to common_sw_ff
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to common_drdy_aux
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to common_blue_led
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to common_yellow_led
+
+# synchronization and timing
+
+set_location_assignment PIN_AG8 -to common_sync_in ; ## arduino_IO6
+
+set_instance_assignment -name io_standard "3.3-v lvttl" -to common_sync_in
+
+execute_flow -compile
diff --git a/projects/ad4062_ardz/de10nano/system_qsys.tcl b/projects/ad4062_ardz/de10nano/system_qsys.tcl
new file mode 100755
index 0000000000..a16b514f58
--- /dev/null
+++ b/projects/ad4062_ardz/de10nano/system_qsys.tcl
@@ -0,0 +1,31 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl
+
+# disable I2C1
+
+set_instance_parameter_value sys_hps {I2C1_Mode} {N/A}
+set_instance_parameter_value sys_hps {I2C1_PinMuxing} {Unused}
+
+# set clk to 100MHz
+
+set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_FREQ} {100.0}
+
+if [info exists ad_project_dir] {
+ source ../../common/ad4062_qsys.tcl
+} else {
+ source ../common/ad4062_qsys.tcl
+}
+
+# system ID
+
+set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9}
+set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
+
+set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt"
+
+sysid_gen_sys_init_file;
diff --git a/projects/ad4062_ardz/de10nano/system_top.v b/projects/ad4062_ardz/de10nano/system_top.v
new file mode 100755
index 0000000000..f3a28c3fba
--- /dev/null
+++ b/projects/ad4062_ardz/de10nano/system_top.v
@@ -0,0 +1,286 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+// 1. The GNU General Public License version 2 as published by the
+// Free Software Foundation, which can be found in the top level directory
+// of this repository (LICENSE_GPL2), and also online at:
+//
+//
+// OR
+//
+// 2. An ADI specific BSD license, which can be found in the top level directory
+// of this repository (LICENSE_ADIBSD), and also on-line at:
+// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+// This will allow to generate bit files and not release the source code,
+// as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+ // clock and resets
+
+ input sys_clk,
+
+ // hps-ddr
+
+ output [14:0] ddr3_a,
+ output [ 2:0] ddr3_ba,
+ output ddr3_reset_n,
+ output ddr3_ck_p,
+ output ddr3_ck_n,
+ output ddr3_cke,
+ output ddr3_cs_n,
+ output ddr3_ras_n,
+ output ddr3_cas_n,
+ output ddr3_we_n,
+ inout [31:0] ddr3_dq,
+ inout [ 3:0] ddr3_dqs_p,
+ inout [ 3:0] ddr3_dqs_n,
+ output [ 3:0] ddr3_dm,
+ output ddr3_odt,
+ input ddr3_rzq,
+
+ // hps-ethernet
+
+ output eth1_tx_clk,
+ output eth1_tx_ctl,
+ output [ 3:0] eth1_tx_d,
+ input eth1_rx_clk,
+ input eth1_rx_ctl,
+ input [ 3:0] eth1_rx_d,
+ output eth1_mdc,
+ inout eth1_mdio,
+
+ // hps-sdio
+
+ output sdio_clk,
+ inout sdio_cmd,
+ inout [ 3:0] sdio_d,
+
+ // hps-spim1
+
+ output spim1_ss0,
+ output spim1_clk,
+ output spim1_mosi,
+ input spim1_miso,
+
+ // hps-usb
+
+ input usb1_clk,
+ output usb1_stp,
+ input usb1_dir,
+ input usb1_nxt,
+ inout [ 7:0] usb1_d,
+
+ // hps-uart
+
+ input uart0_rx,
+ output uart0_tx,
+ inout hps_conv_usb_n,
+
+ // board gpio
+
+ output [ 7:0] gpio_bd_o,
+ input [ 5:0] gpio_bd_i,
+
+ // hdmi
+
+ output hdmi_out_clk,
+ output hdmi_vsync,
+ output hdmi_hsync,
+ output hdmi_data_e,
+ output [ 23:0] hdmi_data,
+
+ inout hdmi_i2c_scl,
+ inout hdmi_i2c_sda,
+
+ // i3c bus
+
+ output i3c_scl,
+ inout i3c_sda,
+
+ output common_reset_adc,
+ output common_shutdown,
+ output common_csb_aux,
+ input common_sw_ff,
+ output common_drdy_aux,
+ output common_blue_led,
+ output common_yellow_led,
+ output common_sync_in,
+
+ // ltc20308
+
+ output ltc2308_cs,
+ output ltc2308_sclk,
+ output ltc2308_mosi,
+ input ltc2308_miso
+);
+
+ // internal signals
+
+ wire sys_resetn;
+ wire [63:0] gpio_i;
+ wire [63:0] gpio_o;
+
+ wire i3c_sdi;
+
+ wire i2c0_out_data;
+ wire i2c0_sda;
+ wire i2c0_out_clk;
+ wire i2c0_scl_in_clk;
+
+ // instantiations
+
+ // unused
+ assign gpio_i[63:42] = gpio_o[63:42];
+ assign gpio_i[37] = gpio_o[37];
+
+ // GPIO outputs
+ assign ltc2308_cs = gpio_o[41];
+ assign common_blue_led = gpio_o[40];
+ assign common_yellow_led = gpio_o[39];
+ assign common_shutdown = gpio_o[36];
+ assign common_drdy_aux = gpio_o[35];
+ assign common_sync_in = gpio_o[33];
+ assign common_csb_aux = gpio_o[34];
+ assign common_reset_adc = gpio_o[32];
+
+ assign gpio_bd_o[7:0] = gpio_o[7:0];
+
+ // GPIO inputs
+ assign gpio_i[38] = common_sw_ff;
+
+ assign gpio_i[31:14] = gpio_o[31:14];
+ assign gpio_i[13:8] = gpio_bd_i[5:0];
+
+ // IO Buffers for I3C
+
+ ALT_IOBUF #(
+ .enable_bus_hold("off"),
+ .weak_pull_up_resistor("off")
+ ) i3c_sda_iobuf (
+ .i(i3c_sdo),
+ .oe(~i3c_t),
+ .o(i3c_sdi),
+ .io(i3c_sda));
+
+ // IO Buffers for I2C
+
+ ALT_IOBUF scl_video_iobuf (
+ .i(1'b0),
+ .oe(i2c0_out_clk),
+ .o(i2c0_scl_in_clk),
+ .io(hdmi_i2c_scl));
+
+ ALT_IOBUF sda_video_iobuf (
+ .i(1'b0),
+ .oe(i2c0_out_data),
+ .o(i2c0_sda),
+ .io(hdmi_i2c_sda));
+
+ system_bd i_system_bd (
+ .sys_clk_clk (sys_clk),
+ .sys_hps_h2f_reset_reset_n (sys_resetn),
+ .sys_hps_memory_mem_a (ddr3_a),
+ .sys_hps_memory_mem_ba (ddr3_ba),
+ .sys_hps_memory_mem_ck (ddr3_ck_p),
+ .sys_hps_memory_mem_ck_n (ddr3_ck_n),
+ .sys_hps_memory_mem_cke (ddr3_cke),
+ .sys_hps_memory_mem_cs_n (ddr3_cs_n),
+ .sys_hps_memory_mem_ras_n (ddr3_ras_n),
+ .sys_hps_memory_mem_cas_n (ddr3_cas_n),
+ .sys_hps_memory_mem_we_n (ddr3_we_n),
+ .sys_hps_memory_mem_reset_n (ddr3_reset_n),
+ .sys_hps_memory_mem_dq (ddr3_dq),
+ .sys_hps_memory_mem_dqs (ddr3_dqs_p),
+ .sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
+ .sys_hps_memory_mem_odt (ddr3_odt),
+ .sys_hps_memory_mem_dm (ddr3_dm),
+ .sys_hps_memory_oct_rzqin (ddr3_rzq),
+ .sys_rst_reset_n (sys_resetn),
+ .sys_hps_i2c0_out_data (i2c0_out_data),
+ .sys_hps_i2c0_sda (i2c0_sda),
+ .sys_hps_i2c0_clk_clk (i2c0_out_clk),
+ .sys_hps_i2c0_scl_in_clk (i2c0_scl_in_clk),
+ .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
+ .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
+ .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
+ .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
+ .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
+ .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
+ .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
+ .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
+ .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
+ .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
+ .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
+ .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
+ .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
+ .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
+ .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
+ .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
+ .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
+ .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
+ .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
+ .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
+ .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
+ .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
+ .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
+ .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
+ .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
+ .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
+ .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
+ .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
+ .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
+ .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
+ .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
+ .sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n),
+ .sys_gpio_bd_in_port (gpio_i[31:0]),
+ .sys_gpio_bd_out_port (gpio_o[31:0]),
+ .sys_gpio_in_export (gpio_i[63:32]),
+ .sys_gpio_out_export (gpio_o[63:32]),
+ .i3c_scl (i3c_scl),
+ .i3c_sdo (i3c_sdo),
+ .i3c_sdi (i3c_sdi),
+ .i3c_t (i3c_t),
+ .sys_spi_MISO (1'b0),
+ .sys_spi_MOSI (),
+ .sys_spi_SCLK (),
+ .sys_spi_SS_n (),
+ .ltc2308_spi_MISO (ltc2308_miso),
+ .ltc2308_spi_MOSI (ltc2308_mosi),
+ .ltc2308_spi_SCLK (ltc2308_sclk),
+ .ltc2308_spi_SS_n (),
+ .axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk),
+ .axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync),
+ .axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync),
+ .axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e),
+ .axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data));
+
+endmodule