diff --git a/library/corundum/ethernet/Makefile b/library/corundum/ethernet/Makefile index c72dece27e1..e7cde1dcb99 100644 --- a/library/corundum/ethernet/Makefile +++ b/library/corundum/ethernet/Makefile @@ -2,19 +2,116 @@ LIBRARY_NAME := ethernet XILINX_DEPS += ethernet_ip.tcl -EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port_map_mac_axis.v -EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v -EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cmac_gty_wrapper.v -EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cmac_gty_ch_wrapper.v -EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rb_drp.v -EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cmac_pad.v -EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mac_ts_insert.v +GENERIC_DEPS += ethernet_core_k26.v +GENERIC_DEPS += ethernet_core_vcu118.v -EXTERNAL_DEPS += ../../../../corundum/fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl -EXTERNAL_DEPS += ../../../../corundum/fpga/mqnic/VCU118/fpga_100g/ip/cmac_gty.tcl +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_core_axi.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_core.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_dram_if.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_interface.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_interface_tx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_interface_rx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port_tx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port_rx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_egress.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_ingress.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_l2_egress.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_l2_ingress.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_rx_queue_map.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_ptp.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_ptp_clock.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_ptp_perout.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_rb_clk_info.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_port_map_phy_xgmii.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cpl_write.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cpl_op_mux.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/desc_fetch.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/desc_op_mux.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/queue_manager.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/cpl_queue_manager.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_fifo.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rx_fifo.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_req_mux.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_engine.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rx_engine.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_checksum.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rx_hash.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rx_checksum.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/rb_drp.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/stats_counter.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/stats_collect.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/stats_dma_if_axi.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/stats_dma_latency.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tx_scheduler_rr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tdma_scheduler.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tdma_ber.v +EXTERNAL_DEPS += ../../../../corundum/fpga/common/rtl/tdma_ber_ch.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_mac_10g.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_64.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_32.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_64.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_32.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/mac_ctrl_rx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/mac_ctrl_tx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_rx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_tx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/lfsr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/ptp_clock.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/ptp_clock_cdc.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/ptp_perout.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_interconnect.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_crossbar.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_crossbar_addr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_crossbar_rd.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_crossbar_wr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_reg_if.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_reg_if_rd.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_reg_if_wr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_register_rd.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/axil_register_wr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/arbiter.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/axi/rtl/priority_encoder.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_adapter.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_arb_mux.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_demux.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_fifo.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_fifo_adapter.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_pipeline_fifo.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/rtl/axis_register.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/irq_rate_limit.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_axi.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_axi_rd.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_axi_wr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_mux.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_mux_rd.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_mux_wr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_if_desc_mux.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_ram_demux_rd.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_ram_demux_wr.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_psdpram.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_client_axis_sink.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/dma_client_axis_source.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/pcie/rtl/pulse_merge.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/xgmii_baser_dec_64.v +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/rtl/xgmii_baser_enc_64.v XILINX_DEPS += ../interfaces/if_ctrl_reg.xml XILINX_DEPS += ../interfaces/if_ctrl_reg_rtl.xml +XILINX_DEPS += ../interfaces/if_csr.xml +XILINX_DEPS += ../interfaces/if_csr_rtl.xml XILINX_DEPS += ../interfaces/if_ptp.xml XILINX_DEPS += ../interfaces/if_ptp_rtl.xml XILINX_DEPS += ../interfaces/if_flow_control_tx.xml @@ -29,6 +126,8 @@ XILINX_DEPS += ../interfaces/if_qspi.xml XILINX_DEPS += ../interfaces/if_qspi_rtl.xml XILINX_DEPS += ../interfaces/if_qsfp.xml XILINX_DEPS += ../interfaces/if_qsfp_rtl.xml +XILINX_DEPS += ../interfaces/if_sfp.xml +XILINX_DEPS += ../interfaces/if_sfp_rtl.xml XILINX_DEPS += ../interfaces/if_i2c.xml XILINX_DEPS += ../interfaces/if_i2c_rtl.xml diff --git a/library/corundum/ethernet/ethernet_core_k26.v b/library/corundum/ethernet/ethernet_core_k26.v new file mode 100755 index 00000000000..1922f0c8cb6 --- /dev/null +++ b/library/corundum/ethernet/ethernet_core_k26.v @@ -0,0 +1,863 @@ +// SPDX-License-Identifier: BSD-2-Clause-Views +/* + * Copyright (c) 2023 The Regents of the University of California + * Copyright (c) 2024 Analog Devices, Inc. All rights reserved + */ +/* + * This file repackages Corundum MQNIC Core AXI with the sole purpose of + * providing it as an IP Core. + * The original file can be refereed at: + * https://github.com/ucsdsysnet/corundum/blob/master/fpga/common/rtl/mqnic_core_axi.v + */ + +`timescale 1ns/100ps + +module ethernet_core #( + + // Structural configuration + parameter IF_COUNT = 1, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + + parameter TDMA_BER_ENABLE = 0, + + parameter XGMII_DATA_WIDTH = 64, + parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, + parameter AXIS_DATA_WIDTH = XGMII_DATA_WIDTH, + parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, + parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1, + parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8), + parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT), + parameter AXIL_CSR_ENABLE = 0, + parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((SCHED_PER_IF+4+7)/8), + + // Statistics counter subsystem + parameter STAT_ENABLE = 0, + parameter STAT_DMA_ENABLE = 1, + parameter STAT_AXI_ENABLE = 1, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12, + + parameter PTP_PEROUT_COUNT = 1, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter PTP_TS_FMT_TOD = 0, + parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, + parameter TX_TAG_WIDTH = 16, + parameter PFC_ENABLE = 1, + parameter LFC_ENABLE = PFC_ENABLE, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64 +) ( + + // Clock and reset + input wire clk, + input wire rst, + + /* + * GPIO + */ + output wire [1:0] led, + output wire [1:0] sfp_led, + + /* + * Ethernet: SFP+ + */ + input wire sfp_rx_p, + input wire sfp_rx_n, + output wire sfp_tx_p, + output wire sfp_tx_n, + input wire sfp_mgt_refclk_p, + input wire sfp_mgt_refclk_n, + + output wire sfp_tx_disable, + input wire sfp_tx_fault, + input wire sfp_rx_los, + input wire sfp_mod_abs, + + input wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr, + input wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data, + input wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb, + input wire ctrl_reg_wr_en, + output wire ctrl_reg_wr_wait, + output wire ctrl_reg_wr_ack, + input wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr, + input wire ctrl_reg_rd_en, + output wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data, + output wire ctrl_reg_rd_wait, + output wire ctrl_reg_rd_ack, + + input wire [AXIL_CSR_ADDR_WIDTH-1:0] s_axil_csr_awaddr, + input wire [2:0] s_axil_csr_awprot, + input wire s_axil_csr_awvalid, + output wire s_axil_csr_awready, + input wire [AXIL_CTRL_DATA_WIDTH-1:0] s_axil_csr_wdata, + input wire [AXIL_CTRL_STRB_WIDTH-1:0] s_axil_csr_wstrb, + input wire s_axil_csr_wvalid, + output wire s_axil_csr_wready, + output wire [1:0] s_axil_csr_bresp, + output wire s_axil_csr_bvalid, + input wire s_axil_csr_bready, + input wire [AXIL_CSR_ADDR_WIDTH-1:0] s_axil_csr_araddr, + input wire [2:0] s_axil_csr_arprot, + input wire s_axil_csr_arvalid, + output wire s_axil_csr_arready, + output wire [AXIL_CTRL_DATA_WIDTH-1:0] s_axil_csr_rdata, + output wire [1:0] s_axil_csr_rresp, + output wire s_axil_csr_rvalid, + input wire s_axil_csr_rready, + + // PTP setup + + output wire ptp_clk, + output wire ptp_rst, + output wire ptp_sample_clk, + input wire ptp_td_sd, + input wire ptp_pps, + input wire ptp_pps_str, + input wire ptp_sync_locked, + input wire [63:0] ptp_sync_ts_rel, + input wire ptp_sync_ts_rel_step, + input wire [96:0] ptp_sync_ts_tod, + input wire ptp_sync_ts_tod_step, + input wire ptp_sync_pps, + input wire ptp_sync_pps_str, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, + + // XGMII interface + output wire [PORT_COUNT-1:0] eth_tx_clk, + output wire [PORT_COUNT-1:0] eth_tx_rst, + + output wire [PORT_COUNT-1:0] eth_tx_ptp_clk, + output wire [PORT_COUNT-1:0] eth_tx_ptp_rst, + input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts, + input wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step, + + output wire [PORT_COUNT-1:0] eth_rx_clk, + output wire [PORT_COUNT-1:0] eth_rx_rst, + input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts, + input wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step, + + input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] axis_eth_tx_tdata, + input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] axis_eth_tx_tkeep, + input wire [PORT_COUNT-1:0] axis_eth_tx_tvalid, + output wire [PORT_COUNT-1:0] axis_eth_tx_tready, + input wire [PORT_COUNT-1:0] axis_eth_tx_tlast, + input wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] axis_eth_tx_tuser, + + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts, + output wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag, + output wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid, + input wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready, + + input wire [PORT_COUNT-1:0] eth_tx_enable, + output wire [PORT_COUNT-1:0] eth_tx_status, + input wire [PORT_COUNT-1:0] eth_tx_lfc_en, + input wire [PORT_COUNT-1:0] eth_tx_lfc_req, + input wire [PORT_COUNT*8-1:0] eth_tx_pfc_en, + input wire [PORT_COUNT*8-1:0] eth_tx_pfc_req, + output wire [PORT_COUNT*8-1:0] eth_tx_fc_quanta_clk_en, + + output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] axis_eth_rx_tdata, + output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] axis_eth_rx_tkeep, + output wire [PORT_COUNT-1:0] axis_eth_rx_tvalid, + input wire [PORT_COUNT-1:0] axis_eth_rx_tready, + output wire [PORT_COUNT-1:0] axis_eth_rx_tlast, + output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] axis_eth_rx_tuser, + + input wire [PORT_COUNT-1:0] eth_rx_enable, + output wire [PORT_COUNT-1:0] eth_rx_status, + input wire [PORT_COUNT-1:0] eth_rx_lfc_en, + output wire [PORT_COUNT-1:0] eth_rx_lfc_req, + input wire [PORT_COUNT-1:0] eth_rx_lfc_ack, + input wire [PORT_COUNT*8-1:0] eth_rx_pfc_en, + output wire [PORT_COUNT*8-1:0] eth_rx_pfc_req, + input wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack, + output wire [PORT_COUNT-1:0] eth_rx_fc_quanta_clk_en, + + /* + * Statistics increment input + */ + output wire [STAT_INC_WIDTH-1:0] s_axis_stat_tdata, + output wire [STAT_ID_WIDTH-1:0] s_axis_stat_tid, + output wire s_axis_stat_tvalid, + input wire s_axis_stat_tready, + + inout wire sfp_i2c_scl, + inout wire sfp_i2c_sda +); + + wire sfp_iic_scl_i_w; + wire sfp_iic_scl_o_w; + wire sfp_iic_scl_t_w; + wire sfp_iic_sda_i_w; + wire sfp_iic_sda_o_w; + wire sfp_iic_sda_t_w; + + wire sfp_drp_clk; + wire sfp_drp_rst; + wire [23:0] sfp_drp_addr; + wire [15:0] sfp_drp_di; + wire sfp_drp_en; + wire sfp_drp_we; + wire [15:0] sfp_drp_do; + wire sfp_drp_rdy; + + localparam RB_BASE_ADDR = 16'h1000; + localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; + + localparam RB_DRP_SFP_BASE = RB_BASE_ADDR + 16'h20; + + reg sfp_i2c_scl_o_reg; + reg sfp_i2c_scl_t_reg; + reg sfp_i2c_sda_o_reg; + reg sfp_i2c_sda_t_reg; + + always @(posedge clk) begin + sfp_i2c_scl_o_reg <= sfp_iic_scl_o_w; + sfp_i2c_scl_t_reg <= sfp_iic_scl_t_w; + sfp_i2c_sda_o_reg <= sfp_iic_sda_o_w; + sfp_i2c_sda_t_reg <= sfp_iic_sda_t_w; + end + + // reg [(IRQ_COUNT*IRQ_STRETCH)-1:0] irq_stretch = {(IRQ_COUNT*IRQ_STRETCH){1'b0}}; + + wire clk_156mhz_int; + + wire clk_125mhz_mmcm_out; + + // Internal 125 MHz clock + wire clk_125mhz_int; + wire rst_125mhz_int; + + wire mmcm_rst = rst; + wire mmcm_locked; + wire mmcm_clkfb; + + assign sfp_drp_clk = clk_125mhz_int; + assign sfp_drp_rst = rst_125mhz_int; + + wire sfp_rx_block_lock; + wire sfp_gtpowergood; + + wire sfp_mgt_refclk; + wire sfp_mgt_refclk_int; + wire sfp_mgt_refclk_bufg; + + wire sfp_tx_clk_int; + wire sfp_tx_rst_int; + wire [63:0] sfp_txd_int; + wire [7:0] sfp_txc_int; + wire sfp_tx_prbs31_enable_int; + wire sfp_rx_clk_int; + wire sfp_rx_rst_int; + wire [63:0] sfp_rxd_int; + wire [7:0] sfp_rxc_int; + wire sfp_rx_prbs31_enable_int; + wire [6:0] sfp_rx_error_count_int; + + wire sfp_rx_status; + + wire sfp_rst; + + wire sfp_tx_fault_int; + wire sfp_rx_los_int; + wire sfp_mod_abs_int; + + sync_signal #( + .WIDTH(5), + .N(2) + ) sync_signal_inst ( + .clk(clk), + .in({sfp_tx_fault, sfp_rx_los, sfp_mod_abs, sfp_i2c_scl, sfp_i2c_sda}), + .out({sfp_tx_fault_int, sfp_rx_los_int, sfp_mod_abs_int, sfp_iic_scl_i_w, sfp_iic_sda_i_w})); + + assign sfp_i2c_scl = sfp_i2c_scl_t_reg ? 1'bz : sfp_i2c_scl_o_reg; + assign sfp_i2c_sda = sfp_i2c_sda_t_reg ? 1'bz : sfp_i2c_sda_o_reg; + + // MMCM instance + // 156.25 MHz in, 125 MHz out + // PFD range: 10 MHz to 500 MHz + // VCO range: 800 MHz to 1600 MHz + // M = 8, D = 1 sets Fvco = 1250 MHz + // Divide by 10 to get output frequency of 125 MHz + MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(10), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(8), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(6.4), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") + ) clk_mmcm_inst ( + .CLKIN1(clk_156mhz_int), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked)); + + BUFG #( + ) clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int)); + + sync_reset #( + .N(4) + ) sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int)); + + IBUFDS_GTE4 #( + ) ibufds_gte4_sfp_mgt_refclk_inst ( + .I (sfp_mgt_refclk_p), + .IB (sfp_mgt_refclk_n), + .CEB (1'b0), + .O (sfp_mgt_refclk), + .ODIV2 (sfp_mgt_refclk_int)); + + BUFG_GT #( + ) bufg_gt_sfp_mgt_refclk_inst ( + .CE (sfp_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (sfp_mgt_refclk_int), + .O (sfp_mgt_refclk_bufg)); + + sync_reset #( + .N(4) + ) + sfp_sync_reset_inst ( + .clk(sfp_mgt_refclk_bufg), + .rst(rst_125mhz_int), + .out(sfp_rst)); + + // TODO move out of the IP + eth_xcvr_phy_10g_gty_quad_wrapper #( + .COUNT(1), + .GT_GTH(1), + .PRBS31_ENABLE(1) + ) sfp_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(sfp_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(sfp_gtpowergood), + .xcvr_gtrefclk00_in(sfp_mgt_refclk), + .xcvr_qpll0pd_in(0), + .xcvr_qpll0reset_in(0), + .xcvr_qpll0pcierate_in(0), + .xcvr_gtrefclk01_in(0), + .xcvr_qpll1pd_in(0), + .xcvr_qpll1reset_in(0), + .xcvr_qpll1pcierate_in(0), + + /* + * DRP + */ + .drp_clk(sfp_drp_clk), + .drp_rst(sfp_drp_rst), + .drp_addr(sfp_drp_addr), + .drp_di(sfp_drp_di), + .drp_en(sfp_drp_en), + .drp_we(sfp_drp_we), + .drp_do(sfp_drp_do), + .drp_rdy(sfp_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp({sfp_tx_p}), + .xcvr_txn({sfp_tx_n}), + .xcvr_rxp({sfp_rx_p}), + .xcvr_rxn({sfp_rx_n}), + + /* + * PHY connections + */ + .phy_1_tx_clk(sfp_tx_clk_int), + .phy_1_tx_rst(sfp_tx_rst_int), + .phy_1_xgmii_txd(sfp_txd_int), + .phy_1_xgmii_txc(sfp_txc_int), + .phy_1_rx_clk(sfp_rx_clk_int), + .phy_1_rx_rst(sfp_rx_rst_int), + .phy_1_xgmii_rxd(sfp_rxd_int), + .phy_1_xgmii_rxc(sfp_rxc_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(sfp_rx_error_count_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(sfp_rx_block_lock), + .phy_1_rx_high_ber(), + .phy_1_rx_status(sfp_rx_status), + .phy_1_cfg_tx_prbs31_enable(sfp_tx_prbs31_enable_int), + .phy_1_cfg_rx_prbs31_enable(sfp_rx_prbs31_enable_int)); + + assign clk_156mhz_int = sfp_mgt_refclk_bufg; + + assign ptp_clk = sfp_mgt_refclk_bufg; + assign ptp_rst = sfp_rst; + assign ptp_sample_clk = clk_125mhz_int; + + assign sfp_led[0] = sfp_rx_status; + assign sfp_led[1] = 1'b0; + + wire [PORT_COUNT-1:0] port_xgmii_tx_clk; + wire [PORT_COUNT-1:0] port_xgmii_tx_rst; + wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; + wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; + + wire [PORT_COUNT-1:0] port_xgmii_rx_clk; + wire [PORT_COUNT-1:0] port_xgmii_rx_rst; + wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; + wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; + + mqnic_port_map_phy_xgmii #( + .PHY_COUNT(1), + .PORT_MASK(PORT_MASK), + .PORT_GROUP_SIZE(1), + + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) + ) + mqnic_port_map_phy_xgmii_inst ( + // towards PHY + .phy_xgmii_tx_clk({sfp_tx_clk_int}), + .phy_xgmii_tx_rst({sfp_tx_rst_int}), + .phy_xgmii_txd({sfp_txd_int}), + .phy_xgmii_txc({sfp_txc_int}), + .phy_tx_status(1'b1), + + .phy_xgmii_rx_clk({sfp_rx_clk_int}), + .phy_xgmii_rx_rst({sfp_rx_rst_int}), + .phy_xgmii_rxd({sfp_rxd_int}), + .phy_xgmii_rxc({sfp_rxc_int}), + .phy_rx_status({sfp_rx_status}), + + // towards MAC + .port_xgmii_tx_clk(port_xgmii_tx_clk), + .port_xgmii_tx_rst(port_xgmii_tx_rst), + .port_xgmii_txd(port_xgmii_txd), + .port_xgmii_txc(port_xgmii_txc), + .port_tx_status(eth_tx_status), + + .port_xgmii_rx_clk(port_xgmii_rx_clk), + .port_xgmii_rx_rst(port_xgmii_rx_rst), + .port_xgmii_rxd(port_xgmii_rxd), + .port_xgmii_rxc(port_xgmii_rxc), + .port_rx_status(eth_rx_status)); + + generate + genvar n; + + for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac + + assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; + assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; + assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; + assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; + + eth_mac_10g #( + .DATA_WIDTH(AXIS_DATA_WIDTH), + .KEEP_WIDTH(AXIS_KEEP_WIDTH), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TS_CTRL_IN_TUSER(0), + .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), + .TX_USER_WIDTH(AXIS_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_RX_USER_WIDTH), + .PFC_ENABLE(PFC_ENABLE), + .PAUSE_ENABLE(LFC_ENABLE) + ) eth_mac_inst ( + .tx_clk(port_xgmii_tx_clk[n]), + .tx_rst(port_xgmii_tx_rst[n]), + .rx_clk(port_xgmii_rx_clk[n]), + .rx_rst(port_xgmii_rx_rst[n]), + + /* + * AXI input + */ + .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), + .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), + .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), + .tx_axis_tready(axis_eth_tx_tready[n +: 1]), + .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), + .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]), + + /* + * AXI output + */ + .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), + .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), + .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), + .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), + .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]), + + /* + * XGMII interface + */ + .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + + /* + * PTP + */ + .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), + .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req(eth_tx_lfc_req[n +: 1]), + .tx_lfc_resend(1'b0), + .rx_lfc_en(eth_rx_lfc_en[n +: 1]), + .rx_lfc_req(eth_rx_lfc_req[n +: 1]), + .rx_lfc_ack(eth_rx_lfc_ack[n +: 1]), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]), + .tx_pfc_resend(1'b0), + .rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]), + .rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]), + .rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]), + + /* + * Pause interface + */ + .tx_lfc_pause_en(1'b1), + .tx_pause_req(1'b0), + .tx_pause_ack(), + + /* + * Status + */ + .tx_start_packet(), + .tx_error_underflow(), + .rx_start_packet(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .stat_tx_mcf(), + .stat_rx_mcf(), + .stat_tx_lfc_pkt(), + .stat_tx_lfc_xon(), + .stat_tx_lfc_xoff(), + .stat_tx_lfc_paused(), + .stat_tx_pfc_pkt(), + .stat_tx_pfc_xon(), + .stat_tx_pfc_xoff(), + .stat_tx_pfc_paused(), + .stat_rx_lfc_pkt(), + .stat_rx_lfc_xon(), + .stat_rx_lfc_xoff(), + .stat_rx_lfc_paused(), + .stat_rx_pfc_pkt(), + .stat_rx_pfc_xon(), + .stat_rx_pfc_xoff(), + .stat_rx_pfc_paused(), + + /* + * Configuration + */ + .cfg_ifg(8'd12), + .cfg_tx_enable(eth_tx_enable[n +: 1]), + .cfg_rx_enable(eth_rx_enable[n +: 1]), + .cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01), + .cfg_mcf_rx_check_eth_dst_mcast(1'b1), + .cfg_mcf_rx_eth_dst_ucast(48'd0), + .cfg_mcf_rx_check_eth_dst_ucast(1'b0), + .cfg_mcf_rx_eth_src(48'd0), + .cfg_mcf_rx_check_eth_src(1'b0), + .cfg_mcf_rx_eth_type(16'h8808), + .cfg_mcf_rx_opcode_lfc(16'h0001), + .cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]), + .cfg_mcf_rx_opcode_pfc(16'h0101), + .cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0), + .cfg_mcf_rx_forward(1'b0), + .cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]), + .cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01), + .cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C), + .cfg_tx_lfc_eth_type(16'h8808), + .cfg_tx_lfc_opcode(16'h0001), + .cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]), + .cfg_tx_lfc_quanta(16'hffff), + .cfg_tx_lfc_refresh(16'h7fff), + .cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01), + .cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C), + .cfg_tx_pfc_eth_type(16'h8808), + .cfg_tx_pfc_opcode(16'h0101), + .cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0), + .cfg_tx_pfc_quanta({8{16'hffff}}), + .cfg_tx_pfc_refresh({8{16'h7fff}}), + .cfg_rx_lfc_opcode(16'h0001), + .cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]), + .cfg_rx_pfc_opcode(16'h0101), + .cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0)); + end + + endgenerate + + generate + + if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(1), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(1)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) tdma_ber_inst ( + .clk(clk), + .rst(rst), + .phy_tx_clk({sfp_tx_clk_int}), + .phy_rx_clk({sfp_rx_clk_int}), + .phy_rx_error_count({sfp_rx_error_count_int}), + .phy_cfg_tx_prbs31_enable({sfp_cfg_tx_prbs31_enable_int}), + .phy_cfg_rx_prbs31_enable({sfp_cfg_rx_prbs31_enable_int}), + .s_axil_awaddr(s_axil_csr_awaddr), + .s_axil_awprot(s_axil_csr_awprot), + .s_axil_awvalid(s_axil_csr_awvalid), + .s_axil_awready(s_axil_csr_awready), + .s_axil_wdata(s_axil_csr_wdata), + .s_axil_wstrb(s_axil_csr_wstrb), + .s_axil_wvalid(s_axil_csr_wvalid), + .s_axil_wready(s_axil_csr_wready), + .s_axil_bresp(s_axil_csr_bresp), + .s_axil_bvalid(s_axil_csr_bvalid), + .s_axil_bready(s_axil_csr_bready), + .s_axil_araddr(s_axil_csr_araddr), + .s_axil_arprot(s_axil_csr_arprot), + .s_axil_arvalid(s_axil_csr_arvalid), + .s_axil_arready(s_axil_csr_arready), + .s_axil_rdata(s_axil_csr_rdata), + .s_axil_rresp(s_axil_csr_rresp), + .s_axil_rvalid(s_axil_csr_rvalid), + .s_axil_rready(s_axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step)); + + end else begin + + assign sfp_cfg_tx_prbs31_enable = 1'b0; + assign sfp_cfg_rx_prbs31_enable = 1'b0; + + end + endgenerate + + wire sfp_drp_reg_wr_wait; + wire sfp_drp_reg_wr_ack; + wire [AXIL_CTRL_DATA_WIDTH-1:0] sfp_drp_reg_rd_data; + wire sfp_drp_reg_rd_wait; + wire sfp_drp_reg_rd_ack; + + reg ctrl_reg_wr_ack_reg = 1'b0; + reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; + reg ctrl_reg_rd_ack_reg = 1'b0; + + reg sfp_tx_disable_reg = 1'b0; + + reg sfp_i2c_scl_o_reg = 1'b1; + reg sfp_i2c_sda_o_reg = 1'b1; + + assign ctrl_reg_wr_wait = sfp_drp_reg_wr_wait; + assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | sfp_drp_reg_wr_ack; + assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | sfp_drp_reg_rd_data; + assign ctrl_reg_rd_wait = sfp_drp_reg_rd_wait; + assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | sfp_drp_reg_rd_ack; + + assign sfp_tx_disable = sfp_tx_disable_reg; + + assign sfp_iic_scl_o_w = sfp_i2c_scl_o_reg; + assign sfp_iic_scl_t_w = sfp_i2c_scl_o_reg; + assign sfp_iic_sda_o_w = sfp_i2c_sda_o_reg; + assign sfp_iic_sda_t_w = sfp_i2c_sda_o_reg; + + always @(posedge clk) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; + ctrl_reg_rd_ack_reg <= 1'b0; + + if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin + // write operation + ctrl_reg_wr_ack_reg <= 1'b0; + case ({ctrl_reg_wr_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h0C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + sfp_i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + sfp_i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // XCVR GPIO + RBB+8'h1C: begin + // XCVR GPIO: control 0123 + if (ctrl_reg_wr_strb[0]) begin + sfp_tx_disable_reg <= ctrl_reg_wr_data[5]; + end + end + default: ctrl_reg_wr_ack_reg <= 1'b0; + endcase + end + + if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin + // read operation + ctrl_reg_rd_ack_reg <= 1'b1; + case ({ctrl_reg_rd_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header + RBB+8'h0C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= sfp_iic_scl_i_w; + ctrl_reg_rd_data_reg[1] <= sfp_i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= sfp_iic_sda_i_w; + ctrl_reg_rd_data_reg[9] <= sfp_i2c_sda_o_reg; + end + // XCVR GPIO + RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type + RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version + RBB+8'h18: ctrl_reg_rd_data_reg <= RB_DRP_SFP_BASE; // XCVR GPIO: Next header + RBB+8'h1C: begin + // XCVR GPIO: control 0123 + ctrl_reg_rd_data_reg[0] <= !sfp_mod_abs_int; + ctrl_reg_rd_data_reg[1] <= sfp_tx_fault_int; + ctrl_reg_rd_data_reg[2] <= sfp_rx_los_int; + ctrl_reg_rd_data_reg[5] <= sfp_tx_disable_reg; + end + default: ctrl_reg_rd_ack_reg <= 1'b0; + endcase + end + + if (rst) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_ack_reg <= 1'b0; + + sfp_tx_disable_reg <= 1'b0; + + sfp_i2c_scl_o_reg <= 1'b1; + sfp_i2c_sda_o_reg <= 1'b1; + end + end + + rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h02, 8'd0, 8'd1}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_SFP_BASE), + .RB_NEXT_PTR(0) + ) sfp_rb_drp_inst ( + .clk(clk), + .rst(rst), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(sfp_drp_reg_wr_wait), + .reg_wr_ack(sfp_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(sfp_drp_reg_rd_data), + .reg_rd_wait(sfp_drp_reg_rd_wait), + .reg_rd_ack(sfp_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(sfp_drp_clk), + .drp_rst(sfp_drp_rst), + .drp_addr(sfp_drp_addr), + .drp_di(sfp_drp_di), + .drp_en(sfp_drp_en), + .drp_we(sfp_drp_we), + .drp_do(sfp_drp_do), + .drp_rdy(sfp_drp_rdy)); + +endmodule diff --git a/library/corundum/ethernet/ethernet_ip.tcl b/library/corundum/ethernet/ethernet_ip.tcl index 6d20f4105e6..8f504f1393d 100644 --- a/library/corundum/ethernet/ethernet_ip.tcl +++ b/library/corundum/ethernet/ethernet_ip.tcl @@ -8,65 +8,78 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl global VIVADO_IP_LIBRARY +adi_ip_create ethernet + if [info exists ::env(BOARD)] { set board $::env(BOARD) - set board_lowercase [string tolower $board] - set ethernet_ip "ethernet_${board_lowercase}" - - adi_ip_create $ethernet_ip $board_lowercase - - cd ./$board_lowercase - if [string equal $board VCU118] { set_property part xcvu9p-flga2104-2L-e [current_project] - source "$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl" source "$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/ip/cmac_gty.tcl" - - # Corundum sources - adi_ip_files ethernet_core_vcu118 [list \ - "../ethernet_core_vcu118.v" \ - "$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/rtl/sync_signal.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/mqnic_port_map_mac_axis.v" \ - "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_gty_wrapper.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_gty_ch_wrapper.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/rb_drp.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_pad.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/mac_ts_insert.v" \ - ] - } elseif [string equal $board XCVU11P] { - set_property part xcvu11p-flgb2104-2-i [current_project] - - source "$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/ip/cmac_usplus.tcl" - source "$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/ip/cmac_gty.tcl" - - # Corundum sources - adi_ip_files ethernet_core_vcu118 [list \ - "../ethernet_core_vcu118.v" \ - "$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/rtl/sync_signal.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/mqnic_port_map_mac_axis.v" \ - "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_gty_wrapper.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_gty_ch_wrapper.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/rb_drp.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_pad.v" \ - "$ad_hdl_dir/../corundum/fpga/common/rtl/mac_ts_insert.v" \ - ] + } elseif [string equal $board K26] { + set_property part xck26-sfvc784-2LVI-i [current_project] + source "$ad_hdl_dir/../corundum/fpga/mqnic/KR260/fpga/ip/eth_xcvr_gth.tcl" } else { error "$board board is not supported!" } } else { - error "Missing BOARD environment variable definition from Makefile!" + error "Missing BOARD environment variable definition from makefile!" +} + +if [string equal $board VCU118] { +# Corundum sources +adi_ip_files ethernet [list \ + "ethernet_core_vcu118.v" \ + "$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/rtl/sync_signal.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/mqnic_port_map_mac_axis.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_gty_wrapper.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_gty_ch_wrapper.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/rb_drp.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/cmac_pad.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/mac_ts_insert.v" \ +] +} elseif [string equal $board K26] { +adi_ip_files ethernet [list \ + "ethernet_core_k26.v" \ + "$ad_hdl_dir/../corundum/fpga/mqnic/KR260/fpga/rtl/sync_signal.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/xgmii_baser_dec_64.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/xgmii_baser_enc_64.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_32.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_32.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/mqnic_port_map_phy_xgmii.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/rb_drp.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_mac_10g.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_64.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_64.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/lfsr.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/mac_ctrl_rx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/mac_ctrl_tx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_rx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_tx.v" \ +] +} else { + error "Missing board type" } -adi_ip_properties_lite $ethernet_ip +adi_ip_properties_lite ethernet +set_property company_url {https://analogdevicesinc.github.io/hdl/library/corundum} [ipx::current_core] set cc [ipx::current_core] -set_property display_name "Corundum Ethernet $board" $cc +set_property display_name "Corundum Ethernet" $cc set_property description "Corundum Ethernet Core IP" $cc -set_property company_url {https://analogdevicesinc.github.io/hdl/library/corundum} [ipx::current_core] # Remove all inferred interfaces and address spaces ipx::remove_all_bus_interface [ipx::current_core] @@ -100,40 +113,6 @@ adi_add_bus "axis_eth_rx" "master" \ adi_add_bus_clock "eth_rx_clk" "axis_eth_rx" "eth_rx_rst" -adi_if_infer_bus analog.com:interface:if_ctrl_reg slave ctrl_reg [list \ - "ctrl_reg_wr_addr ctrl_reg_wr_addr" \ - "ctrl_reg_wr_data ctrl_reg_wr_data" \ - "ctrl_reg_wr_strb ctrl_reg_wr_strb" \ - "ctrl_reg_wr_en ctrl_reg_wr_en" \ - "ctrl_reg_wr_wait ctrl_reg_wr_wait" \ - "ctrl_reg_wr_ack ctrl_reg_wr_ack" \ - "ctrl_reg_rd_addr ctrl_reg_rd_addr" \ - "ctrl_reg_rd_data ctrl_reg_rd_data" \ - "ctrl_reg_rd_en ctrl_reg_rd_en" \ - "ctrl_reg_rd_wait ctrl_reg_rd_wait" \ - "ctrl_reg_rd_ack ctrl_reg_rd_ack" \ -] - -adi_if_infer_bus analog.com:interface:if_flow_control_tx slave flow_control_tx [list \ - "tx_enable eth_tx_enable" \ - "tx_status eth_tx_status" \ - "tx_lfc_en eth_tx_lfc_en" \ - "tx_lfc_req eth_tx_lfc_req" \ - "tx_pfc_en eth_tx_pfc_en" \ - "tx_pfc_req eth_tx_pfc_req" \ -] - -adi_if_infer_bus analog.com:interface:if_flow_control_rx slave flow_control_rx [list \ - "rx_enable eth_rx_enable" \ - "rx_status eth_rx_status" \ - "rx_lfc_en eth_rx_lfc_en" \ - "rx_lfc_req eth_rx_lfc_req" \ - "rx_lfc_ack eth_rx_lfc_ack" \ - "rx_pfc_en eth_rx_pfc_en" \ - "rx_pfc_req eth_rx_pfc_req" \ - "rx_pfc_ack eth_rx_pfc_ack" \ -] - adi_if_infer_bus analog.com:interface:if_ethernet_ptp slave ethernet_ptp_tx [list \ "ptp_clk eth_tx_ptp_clk" \ "ptp_rst eth_tx_ptp_rst" \ @@ -148,6 +127,20 @@ adi_if_infer_bus analog.com:interface:if_ethernet_ptp slave ethernet_ptp_rx [lis "ptp_ts_step eth_rx_ptp_ts_step" \ ] +adi_if_infer_bus analog.com:interface:if_ctrl_reg slave ctrl_reg [list \ + "ctrl_reg_wr_addr ctrl_reg_wr_addr" \ + "ctrl_reg_wr_data ctrl_reg_wr_data" \ + "ctrl_reg_wr_strb ctrl_reg_wr_strb" \ + "ctrl_reg_wr_en ctrl_reg_wr_en" \ + "ctrl_reg_wr_wait ctrl_reg_wr_wait" \ + "ctrl_reg_wr_ack ctrl_reg_wr_ack" \ + "ctrl_reg_rd_addr ctrl_reg_rd_addr" \ + "ctrl_reg_rd_data ctrl_reg_rd_data" \ + "ctrl_reg_rd_en ctrl_reg_rd_en" \ + "ctrl_reg_rd_wait ctrl_reg_rd_wait" \ + "ctrl_reg_rd_ack ctrl_reg_rd_ack" \ +] + adi_if_infer_bus analog.com:interface:if_axis_tx_ptp slave axis_tx_ptp [list \ "ts axis_eth_tx_ptp_ts" \ "tag axis_eth_tx_ptp_ts_tag" \ @@ -155,6 +148,7 @@ adi_if_infer_bus analog.com:interface:if_axis_tx_ptp slave axis_tx_ptp [list \ "ready axis_eth_tx_ptp_ts_ready" \ ] +if [string equal $board VCU118] { adi_if_infer_bus analog.com:interface:if_qspi master qspi0 [list \ "dq_i qspi_0_dq_i" \ "dq_o qspi_0_dq_o" \ @@ -182,6 +176,26 @@ adi_if_infer_bus analog.com:interface:if_qsfp master qsfp [list \ "gtpowergood qsfp_gtpowergood" \ ] +adi_if_infer_bus analog.com:interface:if_flow_control_tx slave flow_control_tx [list \ + "tx_enable eth_tx_enable" \ + "tx_status eth_tx_status" \ + "tx_lfc_en eth_tx_lfc_en" \ + "tx_lfc_req eth_tx_lfc_req" \ + "tx_pfc_en eth_tx_pfc_en" \ + "tx_pfc_req eth_tx_pfc_req" \ +] + +adi_if_infer_bus analog.com:interface:if_flow_control_rx slave flow_control_rx [list \ + "rx_enable eth_rx_enable" \ + "rx_status eth_rx_status" \ + "rx_lfc_en eth_rx_lfc_en" \ + "rx_lfc_req eth_rx_lfc_req" \ + "rx_lfc_ack eth_rx_lfc_ack" \ + "rx_pfc_en eth_rx_pfc_en" \ + "rx_pfc_req eth_rx_pfc_req" \ + "rx_pfc_ack eth_rx_pfc_ack" \ +] + adi_if_infer_bus analog.com:interface:if_i2c master i2c [list \ "scl_i i2c_scl_i" \ "scl_o i2c_scl_o" \ @@ -190,219 +204,220 @@ adi_if_infer_bus analog.com:interface:if_i2c master i2c [list \ "sda_o i2c_sda_o" \ "sda_t i2c_sda_t" \ ] +} elseif [string equal $board K26] { + ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + set reset_intf_main [ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] + set reset_polarity_main [ipx::add_bus_parameter "POLARITY" $reset_intf_main] + set_property value "ACTIVE_HIGH" $reset_polarity_main + + ipx::infer_bus_interface ptp_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface ptp_sample_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + + ipx::infer_bus_interface eth_tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface eth_rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface sfp_tx_clk_int xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface sfp_rx_clk_int xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + + set reset_intf_ptp [ipx::infer_bus_interface ptp_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] + set reset_polarity_ptp [ipx::add_bus_parameter "POLARITY" $reset_intf_ptp] + set_property value "ACTIVE_HIGH" $reset_polarity_ptp + + set eth_tx_rst_intf [ipx::infer_bus_interface eth_tx_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] + set eth_tx_rst_polarity [ipx::add_bus_parameter "POLARITY" $eth_tx_rst_intf] + set_property value "ACTIVE_HIGH" $eth_tx_rst_polarity + set eth_rx_rst_intf [ipx::infer_bus_interface eth_rx_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] + set eth_rx_rst_polarity [ipx::add_bus_parameter "POLARITY" $eth_rx_rst_intf] + set_property value "ACTIVE_HIGH" $eth_rx_rst_polarity + adi_if_infer_bus analog.com:interface:if_flow_control_tx slave flow_control_tx [list \ + "tx_enable eth_tx_enable" \ + "tx_status eth_tx_status" \ + "tx_lfc_en eth_tx_lfc_en" \ + "tx_lfc_req eth_tx_lfc_req" \ + "tx_pfc_en eth_tx_pfc_en" \ + "tx_pfc_req eth_tx_pfc_req" \ + "tx_fc_quanta_clk_en eth_tx_fc_quanta_clk_en" \ + ] + + adi_if_infer_bus analog.com:interface:if_flow_control_rx slave flow_control_rx [list \ + "rx_enable eth_rx_enable" \ + "rx_status eth_rx_status" \ + "rx_lfc_en eth_rx_lfc_en" \ + "rx_lfc_req eth_rx_lfc_req" \ + "rx_lfc_ack eth_rx_lfc_ack" \ + "rx_pfc_en eth_rx_pfc_en" \ + "rx_pfc_req eth_rx_pfc_req" \ + "rx_pfc_ack eth_rx_pfc_ack" \ + "rx_fc_quanta_clk_en eth_rx_fc_quanta_clk_en" \ + ] + + adi_add_bus "m_axis_stat" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [ list \ + {"s_axis_stat_tdata" "TDATA"} \ + {"s_axis_stat_tid" "TID"} \ + {"s_axis_stat_tvalid" "TVALID"} \ + {"s_axis_stat_tready" "TREADY"} ] + + adi_if_infer_bus analog.com:interface:if_sfp master m_sfp [list \ + "rx_p sfp_rx_p" \ + "rx_n sfp_rx_n" \ + "tx_p sfp_tx_p" \ + "tx_n sfp_tx_n" \ + "mgt_refclk_p sfp_mgt_refclk_p" \ + "mgt_refclk_n sfp_mgt_refclk_n" \ + ] + + adi_add_bus "s_axil_csr" "master" \ + "xilinx.com:interface:aximm_rtl:1.0" \ + "xilinx.com:interface:aximm:1.0" \ + { + {"s_axil_csr_awaddr" "AWADDR"} \ + {"s_axil_csr_awprot" "AWPROT"} \ + {"s_axil_csr_awvalid" "AWVALID"} \ + {"s_axil_csr_awready" "AWREADY"} \ + {"s_axil_csr_wdata" "WDATA"} \ + {"s_axil_csr_wstrb" "WSTRB"} \ + {"s_axil_csr_wvalid" "WVALID"} \ + {"s_axil_csr_wready" "WREADY"} \ + {"s_axil_csr_bresp" "BRESP"} \ + {"s_axil_csr_bvalid" "BVALID"} \ + {"s_axil_csr_bready" "BREADY"} \ + {"s_axil_csr_araddr" "ARADDR"} \ + {"s_axil_csr_arprot" "ARPROT"} \ + {"s_axil_csr_arvalid" "ARVALID"} \ + {"s_axil_csr_arready" "ARREADY"} \ + {"s_axil_csr_rdata" "RDATA"} \ + {"s_axil_csr_rresp" "RRESP"} \ + {"s_axil_csr_rvalid" "RVALID"} \ + {"s_axil_csr_rready" "RREADY"} \ + } + + adi_if_infer_bus analog.com:interface:if_ptp slave ptp_clock [list \ + "ptp_td_sd ptp_td_sd" \ + "ptp_pps ptp_pps" \ + "ptp_pps_str ptp_pps_str" \ + "ptp_sync_locked ptp_sync_locked" \ + "ptp_sync_ts_rel ptp_sync_ts_rel" \ + "ptp_sync_ts_rel_step ptp_sync_ts_rel_step" \ + "ptp_sync_ts_tod ptp_sync_ts_tod" \ + "ptp_sync_ts_tod_step ptp_sync_ts_tod_step" \ + "ptp_sync_pps ptp_sync_pps" \ + "ptp_sync_pps_str ptp_sync_pps_str" \ + "ptp_perout_locked ptp_perout_locked" \ + "ptp_perout_error ptp_perout_error" \ + "ptp_perout_pulse ptp_perout_pulse" \ + ] +} ## Customize GUI page -# Remove the automatically generated GUI page -ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] -ipx::save_core $cc +if [string equal $board K26] { + # Remove the automatically generated GUI page + ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] + ipx::save_core $cc + + # Physical + ipgui::add_page -name {Physical} -component $cc -display_name {Physical} + set page0 [ipgui::get_pagespec -name "Physical" -component $cc] + + set group [ipgui::add_group -name "Structural configuration" -component $cc \ + -parent $page0 -display_name "Structural configuration"] + + ipgui::add_param -name "IF_COUNT" -component $cc -parent $page0 + set p [ipgui::get_guiparamspec -name "IF_COUNT" -component $cc] + ipgui::move_param -component $cc -order 0 $p -parent $group + set_property -dict [list \ + "display_name" "Interface count" \ + ] $p + + ipgui::add_param -name "PORTS_PER_IF" -component $cc -parent $page0 + set p [ipgui::get_guiparamspec -name "PORTS_PER_IF" -component $cc] + ipgui::move_param -component $cc -order 1 $p -parent $group + set_property -dict [list \ + "display_name" "Ports per interface" \ + ] $p + + ipgui::add_param -name "PORT_MASK" -component $cc -parent $page0 + set p [ipgui::get_guiparamspec -name "PORT_MASK" -component $cc] + ipgui::move_param -component $cc -order 2 $p -parent $group + set_property -dict [list \ + "display_name" "Port mask" \ + ] $p + + ipgui::add_page -name {PTP} -component $cc -display_name {PTP Setup} + set page1 [ipgui::get_pagespec -name "PTP" -component $cc] + + set group [ipgui::add_group -name "PTP-related configuration" -component $cc \ + -parent $page1 -display_name "PTP-related configuration"] + + ipgui::add_param -name "PTP_TS_ENABLE" -component $cc -parent $page1 + set p [ipgui::get_guiparamspec -name "PTP_TS_ENABLE" -component $cc] + ipgui::move_param -component $cc -order 0 $p -parent $group + set_property -dict [list \ + "display_name" "PTP Timestamp Enable" \ + ] $p + + ipgui::add_param -name "PTP_TS_FMT_TOD" -component $cc -parent $page1 + set p [ipgui::get_guiparamspec -name "PTP_TS_FMT_TOD" -component $cc] + ipgui::move_param -component $cc -order 1 $p -parent $group + set_property -dict [list \ + "display_name" "PTP_TS_FMT_TOD" \ + ] $p + + ipgui::add_param -name "TX_TAG_WIDTH" -component $cc -parent $page1 + set p [ipgui::get_guiparamspec -name "TX_TAG_WIDTH" -component $cc] + ipgui::move_param -component $cc -order 2 $p -parent $group + set_property -dict [list \ + "display_name" "TX_TAG_WIDTH" \ + ] $p + + ipgui::add_page -name {Ethernet} -component $cc -display_name {Ethernet Interface Configuration} + set page2 [ipgui::get_pagespec -name "Ethernet" -component $cc] + + set group [ipgui::add_group -name "ETH Interface configuration" -component $cc \ + -parent $page2 -display_name "ETH Interface configuration"] + + ipgui::add_param -name "ENABLE_PADDING" -component $cc -parent $page2 + set p [ipgui::get_guiparamspec -name "ENABLE_PADDING" -component $cc] + ipgui::move_param -component $cc -order 0 $p -parent $group + set_property -dict [list \ + "display_name" "ENABLE_PADDING" \ + ] $p + + ipgui::add_param -name "ENABLE_DIC" -component $cc -parent $page2 + set p [ipgui::get_guiparamspec -name "ENABLE_DIC" -component $cc] + ipgui::move_param -component $cc -order 1 $p -parent $group + set_property -dict [list \ + "display_name" "ENABLE_DIC" \ + ] $p + + ipgui::add_param -name "MIN_FRAME_LENGTH" -component $cc -parent $page2 + set p [ipgui::get_guiparamspec -name "MIN_FRAME_LENGTH" -component $cc] + ipgui::move_param -component $cc -order 2 $p -parent $group + set_property -dict [list \ + "display_name" "MIN_FRAME_LENGTH" \ + ] $p + + ipgui::add_param -name "PFC_ENABLE" -component $cc -parent $page2 + set p [ipgui::get_guiparamspec -name "PFC_ENABLE" -component $cc] + ipgui::move_param -component $cc -order 3 $p -parent $group + set_property -dict [list \ + "display_name" "PFC_ENABLE" \ + ] $p + + ipgui::add_param -name "AXIL_CSR_ENABLE" -component $cc -parent $page2 + set p [ipgui::get_guiparamspec -name "AXIL_CSR_ENABLE" -component $cc] + ipgui::move_param -component $cc -order 3 $p -parent $group + set_property -dict [list \ + "widget" "checkBox" \ + "display_name" "AXI4 Lite CSR enable" \ + ] $p + + adi_set_bus_dependency "s_axil_csr" "s_axil_csr" \ + "(spirit:decode(id('PARAM_VALUE.AXIL_CSR_ENABLE')) = 1)" -# Physical -ipgui::add_page -name {Physical} -component $cc -display_name {Physical} -set page0 [ipgui::get_pagespec -name "Physical" -component $cc] - -set group [ipgui::add_group -name "Structural configuration" -component $cc \ - -parent $page0 -display_name "Structural configuration"] - -ipgui::add_param -name "QSFP_CNT" -component $cc -parent $page0 -set p [ipgui::get_guiparamspec -name "QSFP_CNT" -component $cc] -ipgui::move_param -component $cc -order 0 $p -parent $group -set_property -dict [list \ - "display_name" "QSFP connector count" \ -] $p - -ipgui::add_param -name "IF_COUNT" -component $cc -parent $page0 -set p [ipgui::get_guiparamspec -name "IF_COUNT" -component $cc] -ipgui::move_param -component $cc -order 1 $p -parent $group -set_property -dict [list \ - "display_name" "Interface count" \ -] $p - -ipgui::add_param -name "PORTS_PER_IF" -component $cc -parent $page0 -set p [ipgui::get_guiparamspec -name "PORTS_PER_IF" -component $cc] -ipgui::move_param -component $cc -order 2 $p -parent $group -set_property -dict [list \ - "display_name" "Ports per interface" \ -] $p - -ipgui::add_param -name "SCHED_PER_IF" -component $cc -parent $page0 -set p [ipgui::get_guiparamspec -name "SCHED_PER_IF" -component $cc] -ipgui::move_param -component $cc -order 3 $p -parent $group -set_property -dict [list \ - "display_name" "Scheduler per interface" \ -] $p - -ipgui::add_param -name "PORT_MASK" -component $cc -parent $page0 -set p [ipgui::get_guiparamspec -name "PORT_MASK" -component $cc] -ipgui::move_param -component $cc -order 4 $p -parent $group -set_property -dict [list \ - "display_name" "Port mask" \ -] $p - -ipgui::add_param -name "PORT_COUNT" -component $cc -parent $page0 -set p [ipgui::get_guiparamspec -name "PORT_COUNT" -component $cc] -ipgui::move_param -component $cc -order 5 $p -parent $group -set_property -dict [list \ - "display_name" "Port count" \ - "tooltip" { IF_COUNT*PORTS_PER_IF } \ -] $p - -ipgui::add_page -name {PTP} -component $cc -display_name {PTP Setup} -set page1 [ipgui::get_pagespec -name "PTP" -component $cc] - -set group [ipgui::add_group -name "PTP-related configuration" -component $cc \ - -parent $page1 -display_name "PTP-related configuration"] - -ipgui::add_param -name "PTP_TS_ENABLE" -component $cc -parent $page1 -set p [ipgui::get_guiparamspec -name "PTP_TS_ENABLE" -component $cc] -ipgui::move_param -component $cc -order 0 $p -parent $group -set_property -dict [list \ - "widget" "checkBox" \ - "display_name" "PTP Timestamp Enable" \ -] $p - -ipgui::add_param -name "PTP_TS_FMT_TOD" -component $cc -parent $page1 -set p [ipgui::get_guiparamspec -name "PTP_TS_FMT_TOD" -component $cc] -ipgui::move_param -component $cc -order 1 $p -parent $group -set_property -dict [list \ - "display_name" "PTP_TS_FMT_TOD" \ -] $p - -ipgui::add_param -name "PTP_TS_WIDTH" -component $cc -parent $page1 -set p [ipgui::get_guiparamspec -name "PTP_TS_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 2 $p -parent $group -set_property -dict [list \ - "display_name" "PTP_TS_WIDTH" \ - "tooltip" { if {PTP_TS_FMT_TOD} {96} else {64} } \ -] $p - -ipgui::add_param -name "TX_TAG_WIDTH" -component $cc -parent $page1 -set p [ipgui::get_guiparamspec -name "TX_TAG_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 3 $p -parent $group -set_property -dict [list \ - "display_name" "TX_TAG_WIDTH" \ -] $p - -ipgui::add_page -name {Ethernet} -component $cc -display_name {Ethernet Interface Configuration} -set page2 [ipgui::get_pagespec -name "Ethernet" -component $cc] - -set group [ipgui::add_group -name "ETH Interface configuration" -component $cc \ - -parent $page2 -display_name "ETH Interface configuration"] - -ipgui::add_param -name "ETH_RX_CLK_FROM_TX" -component $cc -parent $page2 -set p [ipgui::get_guiparamspec -name "ETH_RX_CLK_FROM_TX" -component $cc] -ipgui::move_param -component $cc -order 0 $p -parent $group -set_property -dict [list \ - "widget" "checkBox" \ - "display_name" "Use TX clock for RX" \ -] $p - -ipgui::add_param -name "ETH_RS_FEC_ENABLE" -component $cc -parent $page2 -set p [ipgui::get_guiparamspec -name "ETH_RS_FEC_ENABLE" -component $cc] -ipgui::move_param -component $cc -order 1 $p -parent $group -set_property -dict [list \ - "widget" "checkBox" \ - "display_name" "Enable RS FEC" \ -] $p - -ipgui::add_param -name "AXIS_DATA_WIDTH" -component $cc -parent $page2 -set p [ipgui::get_guiparamspec -name "AXIS_DATA_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 2 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Stream data width" \ -] $p - -ipgui::add_param -name "AXIS_KEEP_WIDTH" -component $cc -parent $page2 -set p [ipgui::get_guiparamspec -name "AXIS_KEEP_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 3 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Stream keep width" \ - "tooltip" { AXIS_DATA_WIDTH/8 } \ -] $p - -ipgui::add_param -name "AXIS_TX_USER_WIDTH" -component $cc -parent $page2 -set p [ipgui::get_guiparamspec -name "AXIS_TX_USER_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 4 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Stream TX user width" \ - "tooltip" { TX_TAG_WIDTH + 1 } \ -] $p - -ipgui::add_param -name "AXIS_RX_USER_WIDTH" -component $cc -parent $page2 -set p [ipgui::get_guiparamspec -name "AXIS_RX_USER_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 5 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Stream RX user width" \ - "tooltip" { if {PTP_TS_ENABLE} {PTP_TS_WIDTH} else {0} + 1 } \ -] $p - -ipgui::add_page -name {AXILite} -component $cc -display_name {AXI lite interface configuration} -set page3 [ipgui::get_pagespec -name "AXILite" -component $cc] - -set group [ipgui::add_group -name "Ethernet control" -component $cc \ - -parent $page3 -display_name "Ethernet control"] - -ipgui::add_param -name "AXIL_CTRL_DATA_WIDTH" -component $cc -parent $page3 -set p [ipgui::get_guiparamspec -name "AXIL_CTRL_DATA_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 0 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Lite control data width" \ -] $p - -ipgui::add_param -name "AXIL_CTRL_ADDR_WIDTH" -component $cc -parent $page3 -set p [ipgui::get_guiparamspec -name "AXIL_CTRL_ADDR_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 1 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Lite control address width" \ -] $p - -ipgui::add_param -name "AXIL_CTRL_STRB_WIDTH" -component $cc -parent $page3 -set p [ipgui::get_guiparamspec -name "AXIL_CTRL_STRB_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 2 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Lite control strobe width" \ - "tooltip" { AXIL_CTRL_DATA_WIDTH/8 } \ -] $p - -set group [ipgui::add_group -name "Application control" -component $cc \ - -parent $page3 -display_name "Application control"] - -ipgui::add_param -name "ETH_RX_CLK_FROM_TX" -component $cc -parent $page3 -set p [ipgui::get_guiparamspec -name "ETH_RX_CLK_FROM_TX" -component $cc] -ipgui::move_param -component $cc -order 0 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Lite interface control address width" \ - "tooltip" { AXIL_CTRL_ADDR_WIDTH - log2(IF_COUNT) } \ -] $p - -ipgui::add_param -name "AXIL_CSR_ADDR_WIDTH" -component $cc -parent $page3 -set p [ipgui::get_guiparamspec -name "AXIL_CSR_ADDR_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 1 $p -parent $group -set_property -dict [list \ - "display_name" "AXI4 Lite CSR address width" \ - "tooltip" { AXIL_IF_CTRL_ADDR_WIDTH - 5 - log2({SCHED_PER_IF + 4 + 7} / 8) } \ -] $p - -ipgui::add_page -name {Scheduler} -component $cc -display_name {Scheduler configuration} -set page4 [ipgui::get_pagespec -name "Scheduler" -component $cc] - -set group [ipgui::add_group -name "Scheduler configuration" -component $cc \ - -parent $page4 -display_name "Scheduler configuration"] - -ipgui::add_param -name "TDMA_BER_ENABLE" -component $cc -parent $page4 -set p [ipgui::get_guiparamspec -name "TDMA_BER_ENABLE" -component $cc] -ipgui::move_param -component $cc -order 0 $p -parent $group -set_property -dict [list \ - "widget" "checkBox" \ - "display_name" "TDMA BER enable" \ -] $p - -ipgui::add_param -name "TDMA_INDEX_WIDTH" -component $cc -parent $page4 -set p [ipgui::get_guiparamspec -name "TDMA_INDEX_WIDTH" -component $cc] -ipgui::move_param -component $cc -order 1 $p -parent $group -set_property -dict [list \ - "display_name" "TDMA index width" \ -] $p +} ## Create and save the XGUI file ipx::create_xgui_files $cc diff --git a/library/corundum/interfaces/Makefile b/library/corundum/interfaces/Makefile index 3cd9fbddaa1..b248a04da90 100644 --- a/library/corundum/interfaces/Makefile +++ b/library/corundum/interfaces/Makefile @@ -14,6 +14,8 @@ M_VIVADO := vivado -mode batch -source XML_FLIST := if_ctrl_reg.xml XML_FLIST += if_ctrl_reg_rtl.xml +XML_FLIST += if_csr.xml +XML_FLIST += if_csr_rtl.xml XML_FLIST += if_ptp.xml XML_FLIST += if_ptp_rtl.xml XML_FLIST += if_flow_control_tx.xml @@ -32,6 +34,8 @@ XML_FLIST += if_qspi.xml XML_FLIST += if_qspi_rtl.xml XML_FLIST += if_qsfp.xml XML_FLIST += if_qsfp_rtl.xml +XML_FLIST += if_sfp.xml +XML_FLIST += if_sfp_rtl.xml XML_FLIST += if_i2c.xml XML_FLIST += if_i2c_rtl.xml XML_FLIST += if_axis_dma_desc.xml diff --git a/library/corundum/interfaces/interfaces_ip.tcl b/library/corundum/interfaces/interfaces_ip.tcl index aa6663cc16e..14e89a1bc4c 100644 --- a/library/corundum/interfaces/interfaces_ip.tcl +++ b/library/corundum/interfaces/interfaces_ip.tcl @@ -21,6 +21,27 @@ adi_if_ports input -1 ctrl_reg_rd_data none 0 adi_if_ports input 1 ctrl_reg_rd_wait none 0 adi_if_ports input 1 ctrl_reg_rd_ack none 0 +adi_if_define if_csr +adi_if_ports output -1 axil_csr_awaddr none 0 +adi_if_ports output -1 axil_csr_awprot none 0 +adi_if_ports output 1 axil_csr_awvalid none 0 +adi_if_ports input 1 axil_csr_awready none 0 +adi_if_ports output -1 axil_csr_wdata none 0 +adi_if_ports output -1 axil_csr_wstrb none 0 +adi_if_ports output 1 axil_csr_wvalid none 0 +adi_if_ports input 1 axil_csr_wready none 0 +adi_if_ports input -1 axil_csr_bresp none 0 +adi_if_ports input 1 axil_csr_bvalid none 0 +adi_if_ports output 1 axil_csr_bready none 0 +adi_if_ports output -1 axil_csr_araddr none 0 +adi_if_ports output -1 axil_csr_arprot none 0 +adi_if_ports output 1 axil_csr_arvalid none 0 +adi_if_ports input 1 axil_csr_arready none 0 +adi_if_ports input -1 axil_csr_rdata none 0 +adi_if_ports input -1 axil_csr_rresp none 0 +adi_if_ports input 1 axil_csr_rvalid none 0 +adi_if_ports output 1 axil_csr_rready none 0 + adi_if_define if_ptp adi_if_ports output 1 ptp_td_sd none 0 adi_if_ports output 1 ptp_pps none 0 @@ -96,6 +117,18 @@ adi_if_ports input -1 intl none 0 adi_if_ports output -1 lpmode none 0 adi_if_ports output -1 gtpowergood none 0 +adi_if_define if_sfp +adi_if_ports output -1 tx_p none 0 +adi_if_ports output -1 tx_n none 0 +adi_if_ports input -1 rx_p none 0 +adi_if_ports input -1 rx_n none 0 +adi_if_ports input -1 mgt_refclk_p none 0 +adi_if_ports input -1 mgt_refclk_n none 0 +adi_if_ports output -1 tx_disable none 0 +adi_if_ports input -1 tx_fault none 0 +adi_if_ports input -1 rx_los none 0 +adi_if_ports input -1 mod_abs none 0 + adi_if_define if_i2c adi_if_ports input 1 scl_i none 0 adi_if_ports output 1 scl_o none 0 diff --git a/library/corundum/scripts/corundum.tcl b/library/corundum/scripts/corundum.tcl index f4d1a10ff43..d89101adf81 100644 --- a/library/corundum/scripts/corundum.tcl +++ b/library/corundum/scripts/corundum.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -7,6 +7,7 @@ create_bd_cell -type hier corundum_hierarchy current_bd_instance /corundum_hierarchy create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_corundum +create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axil_application create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi @@ -15,257 +16,418 @@ create_bd_intf_pin -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi1 create_bd_intf_pin -mode Master -vlnv analog.com:interface:if_qsfp_rtl:1.0 qsfp create_bd_intf_pin -mode Master -vlnv analog.com:interface:if_i2c_rtl:1.0 i2c -create_bd_pin -dir O -from 0 -to 0 -type rst qsfp_rst -create_bd_pin -dir O fpga_boot -create_bd_pin -dir O -type clk qspi_clk -create_bd_pin -dir I -type rst ptp_rst -create_bd_pin -dir I -type clk qsfp_mgt_refclk -create_bd_pin -dir I -type clk qsfp_mgt_refclk_bufg -create_bd_pin -dir I -type clk clk_corundum -create_bd_pin -dir I -type clk clk_125mhz +create_bd_pin -dir I -type clk clk_corundum create_bd_pin -dir I -type rst rst_corundum -create_bd_pin -dir I -type rst rst_125mhz + +if [info exists ::env(BOARD)] { + set board $::env(BOARD) + if [string equal $board VCU118] { + create_bd_pin -dir O -from 0 -to 0 -type rst qsfp_rst + create_bd_pin -dir O fpga_boot + create_bd_pin -dir I -type clk qspi_clk + create_bd_pin -dir I -type rst ptp_rst + create_bd_pin -dir I -type clk qsfp_mgt_refclk + create_bd_pin -dir I -type clk qsfp_mgt_refclk_bufg + create_bd_pin -dir I -type clk ddr_clk + create_bd_pin -dir I -type clk hbm_clk + create_bd_pin -dir I -type rst ddr_rst + create_bd_pin -dir I -type rst hbm_rst + create_bd_pin -dir I ddr_status + create_bd_pin -dir I hbm_status + create_bd_pin -dir I -type clk clk_125mhz + create_bd_pin -dir I -type rst rst_125mhz + } else { + create_bd_pin -dir I sfp_rx_p + create_bd_pin -dir I sfp_rx_n + create_bd_pin -dir O sfp_tx_p + create_bd_pin -dir O sfp_tx_n + create_bd_pin -dir I sfp_mgt_refclk_p + create_bd_pin -dir I sfp_mgt_refclk_n + + create_bd_pin -dir O sfp_tx_disable + create_bd_pin -dir I sfp_tx_fault + create_bd_pin -dir I sfp_rx_los + create_bd_pin -dir I sfp_mod_abs + + create_bd_pin -dir O -from 1 -to 0 sfp_led + create_bd_pin -dir IO sfp_i2c_scl + create_bd_pin -dir IO sfp_i2c_sda + } +} else { + error "Missing BOARD environment variable definition from makefile!" +} create_bd_pin -dir O -type intr irq -ad_ip_instance corundum_core corundum_core [list \ - FPGA_ID $FPGA_ID \ - FW_ID $FW_ID \ - FW_VER $FW_VER \ - BOARD_ID $BOARD_ID \ - BOARD_VER $BOARD_VER \ - BUILD_DATE $BUILD_DATE \ - GIT_HASH $GIT_HASH \ - RELEASE_INFO $RELEASE_INFO \ - IF_COUNT $IF_COUNT \ - PORTS_PER_IF $PORTS_PER_IF \ - SCHED_PER_IF $SCHED_PER_IF \ - PORT_COUNT $PORT_COUNT \ - CLK_PERIOD_NS_NUM $CLK_PERIOD_NS_NUM \ - CLK_PERIOD_NS_DENOM $CLK_PERIOD_NS_DENOM \ - PTP_CLK_PERIOD_NS_NUM $PTP_CLK_PERIOD_NS_NUM \ - PTP_CLK_PERIOD_NS_DENOM $PTP_CLK_PERIOD_NS_DENOM \ - PTP_CLOCK_PIPELINE $PTP_CLOCK_PIPELINE \ - PTP_CLOCK_CDC_PIPELINE $PTP_CLOCK_CDC_PIPELINE \ - PTP_SEPARATE_TX_CLOCK $PTP_SEPARATE_TX_CLOCK \ - PTP_SEPARATE_RX_CLOCK $PTP_SEPARATE_RX_CLOCK \ - PTP_PORT_CDC_PIPELINE $PTP_PORT_CDC_PIPELINE \ - PTP_PEROUT_ENABLE $PTP_PEROUT_ENABLE \ - PTP_PEROUT_COUNT $PTP_PEROUT_COUNT \ - EVENT_QUEUE_OP_TABLE_SIZE $EVENT_QUEUE_OP_TABLE_SIZE \ - TX_QUEUE_OP_TABLE_SIZE $TX_QUEUE_OP_TABLE_SIZE \ - RX_QUEUE_OP_TABLE_SIZE $RX_QUEUE_OP_TABLE_SIZE \ - CQ_OP_TABLE_SIZE $CQ_OP_TABLE_SIZE \ - EQN_WIDTH $EQN_WIDTH \ - TX_QUEUE_INDEX_WIDTH $TX_QUEUE_INDEX_WIDTH \ - RX_QUEUE_INDEX_WIDTH $RX_QUEUE_INDEX_WIDTH \ - CQN_WIDTH $CQN_WIDTH \ - EQ_PIPELINE $EQ_PIPELINE \ - TX_QUEUE_PIPELINE $TX_QUEUE_PIPELINE \ - RX_QUEUE_PIPELINE $RX_QUEUE_PIPELINE \ - CQ_PIPELINE $CQ_PIPELINE \ - TX_DESC_TABLE_SIZE $TX_DESC_TABLE_SIZE \ - RX_DESC_TABLE_SIZE $RX_DESC_TABLE_SIZE \ - RX_INDIR_TBL_ADDR_WIDTH $RX_INDIR_TBL_ADDR_WIDTH \ - TX_SCHEDULER_OP_TABLE_SIZE $TX_SCHEDULER_OP_TABLE_SIZE \ - TX_SCHEDULER_PIPELINE $TX_SCHEDULER_PIPELINE \ - TDMA_INDEX_WIDTH $TDMA_INDEX_WIDTH \ - PTP_TS_ENABLE $PTP_TS_ENABLE \ - PTP_TS_FMT_TOD $PTP_TS_FMT_TOD \ - PTP_TS_WIDTH $PTP_TS_WIDTH \ - TX_CPL_ENABLE $TX_CPL_ENABLE \ - TX_CPL_FIFO_DEPTH $TX_CPL_FIFO_DEPTH \ - TX_TAG_WIDTH $TX_TAG_WIDTH \ - TX_CHECKSUM_ENABLE $TX_CHECKSUM_ENABLE \ - RX_HASH_ENABLE $RX_HASH_ENABLE \ - RX_CHECKSUM_ENABLE $RX_CHECKSUM_ENABLE \ - PFC_ENABLE $PFC_ENABLE \ - LFC_ENABLE $LFC_ENABLE \ - MAC_CTRL_ENABLE $MAC_CTRL_ENABLE \ - TX_FIFO_DEPTH $TX_FIFO_DEPTH \ - RX_FIFO_DEPTH $RX_FIFO_DEPTH \ - MAX_TX_SIZE $MAX_TX_SIZE \ - MAX_RX_SIZE $MAX_RX_SIZE \ - TX_RAM_SIZE $TX_RAM_SIZE \ - RX_RAM_SIZE $RX_RAM_SIZE \ - DDR_ENABLE $DDR_ENABLE \ - DDR_CH $DDR_CH \ - DDR_GROUP_SIZE $DDR_GROUP_SIZE \ - AXI_DDR_DATA_WIDTH $AXI_DDR_DATA_WIDTH \ - AXI_DDR_ADDR_WIDTH $AXI_DDR_ADDR_WIDTH \ - AXI_DDR_STRB_WIDTH $AXI_DDR_STRB_WIDTH \ - AXI_DDR_ID_WIDTH $AXI_DDR_ID_WIDTH \ - AXI_DDR_AWUSER_ENABLE $AXI_DDR_AWUSER_ENABLE \ - AXI_DDR_WUSER_ENABLE $AXI_DDR_WUSER_ENABLE \ - AXI_DDR_BUSER_ENABLE $AXI_DDR_BUSER_ENABLE \ - AXI_DDR_ARUSER_ENABLE $AXI_DDR_ARUSER_ENABLE \ - AXI_DDR_RUSER_ENABLE $AXI_DDR_RUSER_ENABLE \ - AXI_DDR_MAX_BURST_LEN $AXI_DDR_MAX_BURST_LEN \ - AXI_DDR_NARROW_BURST $AXI_DDR_NARROW_BURST \ - AXI_DDR_FIXED_BURST $AXI_DDR_FIXED_BURST \ - AXI_DDR_WRAP_BURST $AXI_DDR_WRAP_BURST \ - HBM_ENABLE $HBM_ENABLE \ - HBM_CH $HBM_CH \ - HBM_GROUP_SIZE $HBM_GROUP_SIZE \ - AXI_HBM_DATA_WIDTH $AXI_HBM_DATA_WIDTH \ - AXI_HBM_ADDR_WIDTH $AXI_HBM_ADDR_WIDTH \ - AXI_HBM_STRB_WIDTH $AXI_HBM_STRB_WIDTH \ - AXI_HBM_ID_WIDTH $AXI_HBM_ID_WIDTH \ - AXI_HBM_AWUSER_ENABLE $AXI_HBM_AWUSER_ENABLE \ - AXI_HBM_AWUSER_WIDTH $AXI_HBM_AWUSER_WIDTH \ - AXI_HBM_WUSER_ENABLE $AXI_HBM_WUSER_ENABLE \ - AXI_HBM_WUSER_WIDTH $AXI_HBM_WUSER_WIDTH \ - AXI_HBM_BUSER_ENABLE $AXI_HBM_BUSER_ENABLE \ - AXI_HBM_BUSER_WIDTH $AXI_HBM_BUSER_WIDTH \ - AXI_HBM_ARUSER_ENABLE $AXI_HBM_ARUSER_ENABLE \ - AXI_HBM_ARUSER_WIDTH $AXI_HBM_ARUSER_WIDTH \ - AXI_HBM_RUSER_ENABLE $AXI_HBM_RUSER_ENABLE \ - AXI_HBM_RUSER_WIDTH $AXI_HBM_RUSER_WIDTH \ - AXI_HBM_MAX_BURST_LEN $AXI_HBM_MAX_BURST_LEN \ - AXI_HBM_NARROW_BURST $AXI_HBM_NARROW_BURST \ - AXI_HBM_FIXED_BURST $AXI_HBM_FIXED_BURST \ - AXI_HBM_WRAP_BURST $AXI_HBM_WRAP_BURST \ - APP_ENABLE $APP_ENABLE \ - APP_ID $APP_ID \ - APP_CTRL_ENABLE $APP_CTRL_ENABLE \ - APP_DMA_ENABLE $APP_DMA_ENABLE \ - APP_AXIS_DIRECT_ENABLE $APP_AXIS_DIRECT_ENABLE \ - APP_AXIS_SYNC_ENABLE $APP_AXIS_SYNC_ENABLE \ - APP_AXIS_IF_ENABLE $APP_AXIS_IF_ENABLE \ - APP_STAT_ENABLE $APP_STAT_ENABLE \ - AXI_DATA_WIDTH $AXI_DATA_WIDTH \ - AXI_ADDR_WIDTH $AXI_ADDR_WIDTH \ - AXI_STRB_WIDTH $AXI_STRB_WIDTH \ - AXI_ID_WIDTH $AXI_ID_WIDTH \ - DMA_IMM_ENABLE $DMA_IMM_ENABLE \ - DMA_IMM_WIDTH $DMA_IMM_WIDTH \ - DMA_LEN_WIDTH $DMA_LEN_WIDTH \ - DMA_TAG_WIDTH $DMA_TAG_WIDTH \ - RAM_ADDR_WIDTH $RAM_ADDR_WIDTH \ - RAM_PIPELINE $RAM_PIPELINE \ - AXI_DMA_MAX_BURST_LEN $AXI_DMA_MAX_BURST_LEN \ - AXI_DMA_READ_USE_ID $AXI_DMA_READ_USE_ID \ - AXI_DMA_WRITE_USE_ID $AXI_DMA_WRITE_USE_ID \ - AXI_DMA_READ_OP_TABLE_SIZE $AXI_DMA_READ_OP_TABLE_SIZE \ - AXI_DMA_WRITE_OP_TABLE_SIZE $AXI_DMA_WRITE_OP_TABLE_SIZE \ - IRQ_COUNT $IRQ_COUNT \ - AXIL_CTRL_DATA_WIDTH $AXIL_CTRL_DATA_WIDTH \ - AXIL_CTRL_ADDR_WIDTH $AXIL_CTRL_ADDR_WIDTH \ - AXIL_CTRL_STRB_WIDTH $AXIL_CTRL_STRB_WIDTH \ - AXIL_IF_CTRL_ADDR_WIDTH $AXIL_IF_CTRL_ADDR_WIDTH \ - AXIL_CSR_ADDR_WIDTH $AXIL_CSR_ADDR_WIDTH \ - AXIL_CSR_PASSTHROUGH_ENABLE $AXIL_CSR_PASSTHROUGH_ENABLE \ - RB_NEXT_PTR $RB_NEXT_PTR \ - AXIL_APP_CTRL_DATA_WIDTH $AXIL_APP_CTRL_DATA_WIDTH \ - AXIL_APP_CTRL_ADDR_WIDTH $AXIL_APP_CTRL_ADDR_WIDTH \ - AXIL_APP_CTRL_STRB_WIDTH $AXIL_APP_CTRL_STRB_WIDTH \ - AXIS_DATA_WIDTH $AXIS_DATA_WIDTH \ - AXIS_KEEP_WIDTH $AXIS_KEEP_WIDTH \ - AXIS_SYNC_DATA_WIDTH $AXIS_SYNC_DATA_WIDTH \ - AXIS_IF_DATA_WIDTH $AXIS_IF_DATA_WIDTH \ - AXIS_TX_USER_WIDTH $AXIS_TX_USER_WIDTH \ - AXIS_RX_USER_WIDTH $AXIS_RX_USER_WIDTH \ - AXIS_RX_USE_READY $AXIS_RX_USE_READY \ - AXIS_TX_PIPELINE $AXIS_TX_PIPELINE \ - AXIS_TX_FIFO_PIPELINE $AXIS_TX_FIFO_PIPELINE \ - AXIS_TX_TS_PIPELINE $AXIS_TX_TS_PIPELINE \ - AXIS_RX_PIPELINE $AXIS_RX_PIPELINE \ - AXIS_RX_FIFO_PIPELINE $AXIS_RX_FIFO_PIPELINE \ - STAT_ENABLE $STAT_ENABLE \ - STAT_DMA_ENABLE $STAT_DMA_ENABLE \ - STAT_AXI_ENABLE $STAT_AXI_ENABLE \ - STAT_INC_WIDTH $STAT_INC_WIDTH \ - STAT_ID_WIDTH $STAT_ID_WIDTH \ - DMA_ADDR_WIDTH_APP $DMA_ADDR_WIDTH_APP \ - RAM_SEL_WIDTH_APP $RAM_SEL_WIDTH_APP \ - RAM_SEG_COUNT_APP $RAM_SEG_COUNT_APP \ - RAM_SEG_DATA_WIDTH_APP $RAM_SEG_DATA_WIDTH_APP \ - RAM_SEG_BE_WIDTH_APP $RAM_SEG_BE_WIDTH_APP \ - RAM_SEG_ADDR_WIDTH_APP $RAM_SEG_ADDR_WIDTH_APP \ - AXIS_SYNC_KEEP_WIDTH_APP $AXIS_SYNC_KEEP_WIDTH_APP \ - AXIS_SYNC_TX_USER_WIDTH_APP $AXIS_SYNC_TX_USER_WIDTH_APP \ - AXIS_SYNC_RX_USER_WIDTH_APP $AXIS_SYNC_RX_USER_WIDTH_APP \ - AXIS_IF_KEEP_WIDTH_APP $AXIS_IF_KEEP_WIDTH_APP \ - AXIS_IF_TX_ID_WIDTH_APP $AXIS_IF_TX_ID_WIDTH_APP \ - AXIS_IF_RX_ID_WIDTH_APP $AXIS_IF_RX_ID_WIDTH_APP \ - AXIS_IF_TX_DEST_WIDTH_APP $AXIS_IF_TX_DEST_WIDTH_APP \ - AXIS_IF_RX_DEST_WIDTH_APP $AXIS_IF_RX_DEST_WIDTH_APP \ - AXIS_IF_TX_USER_WIDTH_APP $AXIS_IF_TX_USER_WIDTH_APP \ - AXIS_IF_RX_USER_WIDTH_APP $AXIS_IF_RX_USER_WIDTH_APP \ -] - -set board [string tolower $::env(BOARD)] - -ad_ip_instance ethernet_${board} ethernet_core [list \ - TDMA_BER_ENABLE $TDMA_BER_ENABLE \ - QSFP_CNT $QSFP_CNT \ - IF_COUNT $IF_COUNT \ - PORTS_PER_IF $PORTS_PER_IF \ - SCHED_PER_IF $SCHED_PER_IF \ - PORT_COUNT $PORT_COUNT \ - PORT_MASK $PORT_MASK \ - PTP_TS_FMT_TOD $PTP_TS_FMT_TOD \ - PTP_TS_WIDTH $PTP_TS_WIDTH \ - TX_TAG_WIDTH $TX_TAG_WIDTH \ - TDMA_INDEX_WIDTH $TDMA_INDEX_WIDTH \ - PTP_TS_ENABLE $PTP_TS_ENABLE \ - AXIL_CTRL_DATA_WIDTH $AXIL_CTRL_DATA_WIDTH \ - AXIL_CTRL_ADDR_WIDTH $AXIL_CTRL_ADDR_WIDTH \ - AXIL_CTRL_STRB_WIDTH $AXIL_CTRL_STRB_WIDTH \ - AXIL_CSR_ADDR_WIDTH $AXIL_CSR_ADDR_WIDTH \ - AXIL_IF_CTRL_ADDR_WIDTH $AXIL_IF_CTRL_ADDR_WIDTH \ - ETH_RX_CLK_FROM_TX $ETH_RX_CLK_FROM_TX \ - ETH_RS_FEC_ENABLE $ETH_RS_FEC_ENABLE \ - AXIS_DATA_WIDTH $AXIS_DATA_WIDTH \ - AXIS_KEEP_WIDTH $AXIS_KEEP_WIDTH \ - AXIS_TX_USER_WIDTH $AXIS_TX_USER_WIDTH \ - AXIS_RX_USER_WIDTH $AXIS_RX_USER_WIDTH \ -] + + +if [string equal $board K26] { + ad_ip_instance corundum_core corundum_core [list \ + FPGA_ID $FPGA_ID \ + FW_ID $FW_ID \ + FW_VER $FW_VER \ + BOARD_ID $BOARD_ID \ + BOARD_VER $BOARD_VER \ + BUILD_DATE $BUILD_DATE \ + GIT_HASH $GIT_HASH \ + RELEASE_INFO $RELEASE_INFO \ + IF_COUNT $IF_COUNT \ + PORTS_PER_IF $PORTS_PER_IF \ + SCHED_PER_IF $SCHED_PER_IF \ + PORT_COUNT $PORT_COUNT \ + CLK_PERIOD_NS_NUM $CLK_PERIOD_NS_NUM \ + CLK_PERIOD_NS_DENOM $CLK_PERIOD_NS_DENOM \ + PTP_CLOCK_PIPELINE $PTP_CLOCK_PIPELINE \ + PTP_CLOCK_CDC_PIPELINE $PTP_CLOCK_CDC_PIPELINE \ + PTP_PORT_CDC_PIPELINE $PTP_PORT_CDC_PIPELINE \ + PTP_PEROUT_ENABLE $PTP_PEROUT_ENABLE \ + PTP_PEROUT_COUNT $PTP_PEROUT_COUNT \ + EVENT_QUEUE_OP_TABLE_SIZE $EVENT_QUEUE_OP_TABLE_SIZE \ + TX_QUEUE_OP_TABLE_SIZE $TX_QUEUE_OP_TABLE_SIZE \ + RX_QUEUE_OP_TABLE_SIZE $RX_QUEUE_OP_TABLE_SIZE \ + CQ_OP_TABLE_SIZE $CQ_OP_TABLE_SIZE \ + EQN_WIDTH $EQN_WIDTH \ + TX_QUEUE_INDEX_WIDTH $TX_QUEUE_INDEX_WIDTH \ + RX_QUEUE_INDEX_WIDTH $RX_QUEUE_INDEX_WIDTH \ + CQN_WIDTH $CQN_WIDTH \ + EQ_PIPELINE $EQ_PIPELINE \ + TX_QUEUE_PIPELINE $TX_QUEUE_PIPELINE \ + RX_QUEUE_PIPELINE $RX_QUEUE_PIPELINE \ + CQ_PIPELINE $CQ_PIPELINE \ + TX_DESC_TABLE_SIZE $TX_DESC_TABLE_SIZE \ + RX_DESC_TABLE_SIZE $RX_DESC_TABLE_SIZE \ + RX_INDIR_TBL_ADDR_WIDTH $RX_INDIR_TBL_ADDR_WIDTH \ + TX_SCHEDULER_OP_TABLE_SIZE $TX_SCHEDULER_OP_TABLE_SIZE \ + TX_SCHEDULER_PIPELINE $TX_SCHEDULER_PIPELINE \ + TDMA_INDEX_WIDTH $TDMA_INDEX_WIDTH \ + PTP_TS_ENABLE $PTP_TS_ENABLE \ + TX_CPL_FIFO_DEPTH $TX_CPL_FIFO_DEPTH \ + TX_CHECKSUM_ENABLE $TX_CHECKSUM_ENABLE \ + RX_HASH_ENABLE $RX_HASH_ENABLE \ + RX_CHECKSUM_ENABLE $RX_CHECKSUM_ENABLE \ + TX_FIFO_DEPTH $TX_FIFO_DEPTH \ + RX_FIFO_DEPTH $RX_FIFO_DEPTH \ + MAX_TX_SIZE $MAX_TX_SIZE \ + MAX_RX_SIZE $MAX_RX_SIZE \ + TX_RAM_SIZE $TX_RAM_SIZE \ + RX_RAM_SIZE $RX_RAM_SIZE \ + APP_ENABLE $APP_ENABLE \ + APP_ID $APP_ID \ + APP_CTRL_ENABLE $APP_CTRL_ENABLE \ + APP_DMA_ENABLE $APP_DMA_ENABLE \ + APP_AXIS_DIRECT_ENABLE $APP_AXIS_DIRECT_ENABLE \ + APP_AXIS_SYNC_ENABLE $APP_AXIS_SYNC_ENABLE \ + APP_AXIS_IF_ENABLE $APP_AXIS_IF_ENABLE \ + APP_STAT_ENABLE $APP_STAT_ENABLE \ + AXI_DATA_WIDTH $AXI_DATA_WIDTH \ + AXI_ADDR_WIDTH $AXI_ADDR_WIDTH \ + AXI_ID_WIDTH $AXI_ID_WIDTH \ + DMA_IMM_ENABLE $DMA_IMM_ENABLE \ + DMA_IMM_WIDTH $DMA_IMM_WIDTH \ + DMA_LEN_WIDTH $DMA_LEN_WIDTH \ + DMA_TAG_WIDTH $DMA_TAG_WIDTH \ + RAM_ADDR_WIDTH $RAM_ADDR_WIDTH \ + RAM_PIPELINE $RAM_PIPELINE \ + AXI_DMA_MAX_BURST_LEN $AXI_DMA_MAX_BURST_LEN \ + IRQ_COUNT $IRQ_COUNT \ + AXIL_CTRL_DATA_WIDTH $AXIL_CTRL_DATA_WIDTH \ + AXIL_CTRL_ADDR_WIDTH $AXIL_CTRL_ADDR_WIDTH \ + AXIL_APP_CTRL_DATA_WIDTH $AXIL_APP_CTRL_DATA_WIDTH \ + AXIL_APP_CTRL_ADDR_WIDTH $AXIL_APP_CTRL_ADDR_WIDTH \ + STAT_ENABLE $STAT_ENABLE \ + STAT_DMA_ENABLE $STAT_DMA_ENABLE \ + STAT_AXI_ENABLE $STAT_AXI_ENABLE \ + STAT_INC_WIDTH $STAT_INC_WIDTH \ + STAT_ID_WIDTH $STAT_ID_WIDTH + ] + + ad_ip_instance ethernet ethernet_core [list \ + IF_COUNT $IF_COUNT \ + PORTS_PER_IF $PORTS_PER_IF \ + PORT_MASK $PORT_MASK \ + PTP_TS_ENABLE $PTP_TS_ENABLE \ + ENABLE_PADDING $ENABLE_PADDING \ + ENABLE_DIC $ENABLE_DIC \ + MIN_FRAME_LENGTH $MIN_FRAME_LENGTH \ + PFC_ENABLE $PFC_ENABLE \ + ] +} else { + ad_ip_instance corundum_core corundum_core [list \ + FPGA_ID $FPGA_ID \ + FW_ID $FW_ID \ + FW_VER $FW_VER \ + BOARD_ID $BOARD_ID \ + BOARD_VER $BOARD_VER \ + BUILD_DATE $BUILD_DATE \ + GIT_HASH $GIT_HASH \ + RELEASE_INFO $RELEASE_INFO \ + IF_COUNT $IF_COUNT \ + PORTS_PER_IF $PORTS_PER_IF \ + SCHED_PER_IF $SCHED_PER_IF \ + PORT_COUNT $PORT_COUNT \ + CLK_PERIOD_NS_NUM $CLK_PERIOD_NS_NUM \ + CLK_PERIOD_NS_DENOM $CLK_PERIOD_NS_DENOM \ + PTP_CLK_PERIOD_NS_NUM $PTP_CLK_PERIOD_NS_NUM \ + PTP_CLK_PERIOD_NS_DENOM $PTP_CLK_PERIOD_NS_DENOM \ + PTP_CLOCK_PIPELINE $PTP_CLOCK_PIPELINE \ + PTP_CLOCK_CDC_PIPELINE $PTP_CLOCK_CDC_PIPELINE \ + PTP_SEPARATE_TX_CLOCK $PTP_SEPARATE_TX_CLOCK \ + PTP_SEPARATE_RX_CLOCK $PTP_SEPARATE_RX_CLOCK \ + PTP_PORT_CDC_PIPELINE $PTP_PORT_CDC_PIPELINE \ + PTP_PEROUT_ENABLE $PTP_PEROUT_ENABLE \ + PTP_PEROUT_COUNT $PTP_PEROUT_COUNT \ + EVENT_QUEUE_OP_TABLE_SIZE $EVENT_QUEUE_OP_TABLE_SIZE \ + TX_QUEUE_OP_TABLE_SIZE $TX_QUEUE_OP_TABLE_SIZE \ + RX_QUEUE_OP_TABLE_SIZE $RX_QUEUE_OP_TABLE_SIZE \ + CQ_OP_TABLE_SIZE $CQ_OP_TABLE_SIZE \ + EQN_WIDTH $EQN_WIDTH \ + TX_QUEUE_INDEX_WIDTH $TX_QUEUE_INDEX_WIDTH \ + RX_QUEUE_INDEX_WIDTH $RX_QUEUE_INDEX_WIDTH \ + CQN_WIDTH $CQN_WIDTH \ + EQ_PIPELINE $EQ_PIPELINE \ + TX_QUEUE_PIPELINE $TX_QUEUE_PIPELINE \ + RX_QUEUE_PIPELINE $RX_QUEUE_PIPELINE \ + CQ_PIPELINE $CQ_PIPELINE \ + TX_DESC_TABLE_SIZE $TX_DESC_TABLE_SIZE \ + RX_DESC_TABLE_SIZE $RX_DESC_TABLE_SIZE \ + RX_INDIR_TBL_ADDR_WIDTH $RX_INDIR_TBL_ADDR_WIDTH \ + TX_SCHEDULER_OP_TABLE_SIZE $TX_SCHEDULER_OP_TABLE_SIZE \ + TX_SCHEDULER_PIPELINE $TX_SCHEDULER_PIPELINE \ + TDMA_INDEX_WIDTH $TDMA_INDEX_WIDTH \ + PTP_TS_ENABLE $PTP_TS_ENABLE \ + PTP_TS_FMT_TOD $PTP_TS_FMT_TOD \ + PTP_TS_WIDTH $PTP_TS_WIDTH \ + TX_CPL_ENABLE $TX_CPL_ENABLE \ + TX_CPL_FIFO_DEPTH $TX_CPL_FIFO_DEPTH \ + TX_TAG_WIDTH $TX_TAG_WIDTH \ + TX_CHECKSUM_ENABLE $TX_CHECKSUM_ENABLE \ + RX_HASH_ENABLE $RX_HASH_ENABLE \ + RX_CHECKSUM_ENABLE $RX_CHECKSUM_ENABLE \ + PFC_ENABLE $PFC_ENABLE \ + LFC_ENABLE $LFC_ENABLE \ + MAC_CTRL_ENABLE $MAC_CTRL_ENABLE \ + TX_FIFO_DEPTH $TX_FIFO_DEPTH \ + RX_FIFO_DEPTH $RX_FIFO_DEPTH \ + MAX_TX_SIZE $MAX_TX_SIZE \ + MAX_RX_SIZE $MAX_RX_SIZE \ + TX_RAM_SIZE $TX_RAM_SIZE \ + RX_RAM_SIZE $RX_RAM_SIZE \ + DDR_ENABLE $DDR_ENABLE \ + DDR_CH $DDR_CH \ + DDR_GROUP_SIZE $DDR_GROUP_SIZE \ + AXI_DDR_DATA_WIDTH $AXI_DDR_DATA_WIDTH \ + AXI_DDR_ADDR_WIDTH $AXI_DDR_ADDR_WIDTH \ + AXI_DDR_STRB_WIDTH $AXI_DDR_STRB_WIDTH \ + AXI_DDR_ID_WIDTH $AXI_DDR_ID_WIDTH \ + AXI_DDR_AWUSER_ENABLE $AXI_DDR_AWUSER_ENABLE \ + AXI_DDR_WUSER_ENABLE $AXI_DDR_WUSER_ENABLE \ + AXI_DDR_BUSER_ENABLE $AXI_DDR_BUSER_ENABLE \ + AXI_DDR_ARUSER_ENABLE $AXI_DDR_ARUSER_ENABLE \ + AXI_DDR_RUSER_ENABLE $AXI_DDR_RUSER_ENABLE \ + AXI_DDR_MAX_BURST_LEN $AXI_DDR_MAX_BURST_LEN \ + AXI_DDR_NARROW_BURST $AXI_DDR_NARROW_BURST \ + AXI_DDR_FIXED_BURST $AXI_DDR_FIXED_BURST \ + AXI_DDR_WRAP_BURST $AXI_DDR_WRAP_BURST \ + HBM_ENABLE $HBM_ENABLE \ + HBM_CH $HBM_CH \ + HBM_GROUP_SIZE $HBM_GROUP_SIZE \ + AXI_HBM_DATA_WIDTH $AXI_HBM_DATA_WIDTH \ + AXI_HBM_ADDR_WIDTH $AXI_HBM_ADDR_WIDTH \ + AXI_HBM_STRB_WIDTH $AXI_HBM_STRB_WIDTH \ + AXI_HBM_ID_WIDTH $AXI_HBM_ID_WIDTH \ + AXI_HBM_AWUSER_ENABLE $AXI_HBM_AWUSER_ENABLE \ + AXI_HBM_AWUSER_WIDTH $AXI_HBM_AWUSER_WIDTH \ + AXI_HBM_WUSER_ENABLE $AXI_HBM_WUSER_ENABLE \ + AXI_HBM_WUSER_WIDTH $AXI_HBM_WUSER_WIDTH \ + AXI_HBM_BUSER_ENABLE $AXI_HBM_BUSER_ENABLE \ + AXI_HBM_BUSER_WIDTH $AXI_HBM_BUSER_WIDTH \ + AXI_HBM_ARUSER_ENABLE $AXI_HBM_ARUSER_ENABLE \ + AXI_HBM_ARUSER_WIDTH $AXI_HBM_ARUSER_WIDTH \ + AXI_HBM_RUSER_ENABLE $AXI_HBM_RUSER_ENABLE \ + AXI_HBM_RUSER_WIDTH $AXI_HBM_RUSER_WIDTH \ + AXI_HBM_MAX_BURST_LEN $AXI_HBM_MAX_BURST_LEN \ + AXI_HBM_NARROW_BURST $AXI_HBM_NARROW_BURST \ + AXI_HBM_FIXED_BURST $AXI_HBM_FIXED_BURST \ + AXI_HBM_WRAP_BURST $AXI_HBM_WRAP_BURST \ + APP_ENABLE $APP_ENABLE \ + APP_ID $APP_ID \ + APP_CTRL_ENABLE $APP_CTRL_ENABLE \ + APP_DMA_ENABLE $APP_DMA_ENABLE \ + APP_AXIS_DIRECT_ENABLE $APP_AXIS_DIRECT_ENABLE \ + APP_AXIS_SYNC_ENABLE $APP_AXIS_SYNC_ENABLE \ + APP_AXIS_IF_ENABLE $APP_AXIS_IF_ENABLE \ + APP_STAT_ENABLE $APP_STAT_ENABLE \ + AXI_DATA_WIDTH $AXI_DATA_WIDTH \ + AXI_ADDR_WIDTH $AXI_ADDR_WIDTH \ + AXI_STRB_WIDTH $AXI_STRB_WIDTH \ + AXI_ID_WIDTH $AXI_ID_WIDTH \ + DMA_IMM_ENABLE $DMA_IMM_ENABLE \ + DMA_IMM_WIDTH $DMA_IMM_WIDTH \ + DMA_LEN_WIDTH $DMA_LEN_WIDTH \ + DMA_TAG_WIDTH $DMA_TAG_WIDTH \ + RAM_ADDR_WIDTH $RAM_ADDR_WIDTH \ + RAM_PIPELINE $RAM_PIPELINE \ + AXI_DMA_MAX_BURST_LEN $AXI_DMA_MAX_BURST_LEN \ + AXI_DMA_READ_USE_ID $AXI_DMA_READ_USE_ID \ + AXI_DMA_WRITE_USE_ID $AXI_DMA_WRITE_USE_ID \ + AXI_DMA_READ_OP_TABLE_SIZE $AXI_DMA_READ_OP_TABLE_SIZE \ + AXI_DMA_WRITE_OP_TABLE_SIZE $AXI_DMA_WRITE_OP_TABLE_SIZE \ + IRQ_COUNT $IRQ_COUNT \ + AXIL_CTRL_DATA_WIDTH $AXIL_CTRL_DATA_WIDTH \ + AXIL_CTRL_ADDR_WIDTH $AXIL_CTRL_ADDR_WIDTH \ + AXIL_CTRL_STRB_WIDTH $AXIL_CTRL_STRB_WIDTH \ + AXIL_IF_CTRL_ADDR_WIDTH $AXIL_IF_CTRL_ADDR_WIDTH \ + AXIL_CSR_ADDR_WIDTH $AXIL_CSR_ADDR_WIDTH \ + AXIL_CSR_PASSTHROUGH_ENABLE $AXIL_CSR_PASSTHROUGH_ENABLE \ + RB_NEXT_PTR $RB_NEXT_PTR \ + AXIL_APP_CTRL_DATA_WIDTH $AXIL_APP_CTRL_DATA_WIDTH \ + AXIL_APP_CTRL_ADDR_WIDTH $AXIL_APP_CTRL_ADDR_WIDTH \ + AXIL_APP_CTRL_STRB_WIDTH $AXIL_APP_CTRL_STRB_WIDTH \ + AXIS_DATA_WIDTH $AXIS_DATA_WIDTH \ + AXIS_KEEP_WIDTH $AXIS_KEEP_WIDTH \ + AXIS_SYNC_DATA_WIDTH $AXIS_SYNC_DATA_WIDTH \ + AXIS_IF_DATA_WIDTH $AXIS_IF_DATA_WIDTH \ + AXIS_TX_USER_WIDTH $AXIS_TX_USER_WIDTH \ + AXIS_RX_USER_WIDTH $AXIS_RX_USER_WIDTH \ + AXIS_RX_USE_READY $AXIS_RX_USE_READY \ + AXIS_TX_PIPELINE $AXIS_TX_PIPELINE \ + AXIS_TX_FIFO_PIPELINE $AXIS_TX_FIFO_PIPELINE \ + AXIS_TX_TS_PIPELINE $AXIS_TX_TS_PIPELINE \ + AXIS_RX_PIPELINE $AXIS_RX_PIPELINE \ + AXIS_RX_FIFO_PIPELINE $AXIS_RX_FIFO_PIPELINE \ + STAT_ENABLE $STAT_ENABLE \ + STAT_DMA_ENABLE $STAT_DMA_ENABLE \ + STAT_AXI_ENABLE $STAT_AXI_ENABLE \ + STAT_INC_WIDTH $STAT_INC_WIDTH \ + STAT_ID_WIDTH $STAT_ID_WIDTH \ + DMA_ADDR_WIDTH_APP $DMA_ADDR_WIDTH_APP \ + RAM_SEL_WIDTH_APP $RAM_SEL_WIDTH_APP \ + RAM_SEG_COUNT_APP $RAM_SEG_COUNT_APP \ + RAM_SEG_DATA_WIDTH_APP $RAM_SEG_DATA_WIDTH_APP \ + RAM_SEG_BE_WIDTH_APP $RAM_SEG_BE_WIDTH_APP \ + RAM_SEG_ADDR_WIDTH_APP $RAM_SEG_ADDR_WIDTH_APP \ + AXIS_SYNC_KEEP_WIDTH_APP $AXIS_SYNC_KEEP_WIDTH_APP \ + AXIS_SYNC_TX_USER_WIDTH_APP $AXIS_SYNC_TX_USER_WIDTH_APP \ + AXIS_SYNC_RX_USER_WIDTH_APP $AXIS_SYNC_RX_USER_WIDTH_APP \ + AXIS_IF_KEEP_WIDTH_APP $AXIS_IF_KEEP_WIDTH_APP \ + AXIS_IF_TX_ID_WIDTH_APP $AXIS_IF_TX_ID_WIDTH_APP \ + AXIS_IF_RX_ID_WIDTH_APP $AXIS_IF_RX_ID_WIDTH_APP \ + AXIS_IF_TX_DEST_WIDTH_APP $AXIS_IF_TX_DEST_WIDTH_APP \ + AXIS_IF_RX_DEST_WIDTH_APP $AXIS_IF_RX_DEST_WIDTH_APP \ + AXIS_IF_TX_USER_WIDTH_APP $AXIS_IF_TX_USER_WIDTH_APP \ + AXIS_IF_RX_USER_WIDTH_APP $AXIS_IF_RX_USER_WIDTH_APP \ + ] + + ad_ip_instance ethernet ethernet_core [list \ + TDMA_BER_ENABLE $TDMA_BER_ENABLE \ + QSFP_CNT $QSFP_CNT \ + IF_COUNT $IF_COUNT \ + PORTS_PER_IF $PORTS_PER_IF \ + SCHED_PER_IF $SCHED_PER_IF \ + PORT_COUNT $PORT_COUNT \ + PORT_MASK $PORT_MASK \ + PTP_TS_FMT_TOD $PTP_TS_FMT_TOD \ + PTP_TS_WIDTH $PTP_TS_WIDTH \ + TX_TAG_WIDTH $TX_TAG_WIDTH \ + TDMA_INDEX_WIDTH $TDMA_INDEX_WIDTH \ + PTP_TS_ENABLE $PTP_TS_ENABLE \ + AXIL_CTRL_DATA_WIDTH $AXIL_CTRL_DATA_WIDTH \ + AXIL_CTRL_ADDR_WIDTH $AXIL_CTRL_ADDR_WIDTH \ + AXIL_CTRL_STRB_WIDTH $AXIL_CTRL_STRB_WIDTH \ + AXIL_CSR_ADDR_WIDTH $AXIL_CSR_ADDR_WIDTH \ + AXIL_IF_CTRL_ADDR_WIDTH $AXIL_IF_CTRL_ADDR_WIDTH \ + ETH_RX_CLK_FROM_TX $ETH_RX_CLK_FROM_TX \ + ETH_RS_FEC_ENABLE $ETH_RS_FEC_ENABLE \ + AXIS_DATA_WIDTH $AXIS_DATA_WIDTH \ + AXIS_KEEP_WIDTH $AXIS_KEEP_WIDTH \ + AXIS_TX_USER_WIDTH $AXIS_TX_USER_WIDTH \ + AXIS_RX_USER_WIDTH $AXIS_RX_USER_WIDTH \ + STAT_ID_WIDTH $STAT_ID_WIDTH + ] +} ad_connect corundum_core/s_axil_ctrl s_axil_corundum ad_connect corundum_core/m_axis_tx ethernet_core/axis_eth_tx ad_connect corundum_core/s_axis_rx ethernet_core/axis_eth_rx -ad_connect corundum_core/ctrl_reg ethernet_core/ctrl_reg ad_connect corundum_core/flow_control_tx ethernet_core/flow_control_tx ad_connect corundum_core/flow_control_rx ethernet_core/flow_control_rx + ad_connect corundum_core/ethernet_ptp_tx ethernet_core/ethernet_ptp_tx ad_connect corundum_core/ethernet_ptp_rx ethernet_core/ethernet_ptp_rx ad_connect corundum_core/axis_tx_ptp ethernet_core/axis_tx_ptp -ad_connect corundum_core/m_axi m_axi +ad_connect corundum_core/rx_clk ethernet_core/eth_rx_clk +ad_connect corundum_core/rx_rst ethernet_core/eth_rx_rst +ad_connect corundum_core/tx_clk ethernet_core/eth_tx_clk +ad_connect corundum_core/tx_rst ethernet_core/eth_tx_rst -ad_connect corundum_core/s_axis_stat_tvalid GND +ad_connect corundum_core/m_axi m_axi ad_connect corundum_core/clk clk_corundum ad_connect corundum_core/rst rst_corundum -ad_connect corundum_core/tx_clk ethernet_core/eth_tx_clk -ad_connect corundum_core/tx_rst ethernet_core/eth_tx_rst -ad_connect corundum_core/rx_clk ethernet_core/eth_rx_clk -ad_connect corundum_core/rx_rst ethernet_core/eth_rx_rst -ad_connect corundum_core/ptp_clk qsfp_mgt_refclk_bufg -ad_connect corundum_core/ptp_rst ptp_rst -ad_connect corundum_core/ptp_sample_clk clk_125mhz ad_connect corundum_core/irq irq ad_connect ethernet_core/clk clk_corundum ad_connect ethernet_core/rst rst_corundum -ad_connect ethernet_core/clk_125mhz clk_125mhz -ad_connect ethernet_core/rst_125mhz rst_125mhz -ad_connect ethernet_core/qsfp_drp_clk clk_125mhz -ad_connect ethernet_core/qsfp_drp_rst rst_125mhz -ad_connect ethernet_core/qsfp_mgt_refclk qsfp_mgt_refclk -ad_connect ethernet_core/qsfp_mgt_refclk_bufg qsfp_mgt_refclk_bufg -ad_connect ethernet_core/qsfp_rst qsfp_rst -ad_connect ethernet_core/fpga_boot fpga_boot -ad_connect ethernet_core/qspi_clk qspi_clk - -ad_connect ethernet_core/qspi0 qspi0 -ad_connect ethernet_core/qspi1 qspi1 -ad_connect ethernet_core/qsfp qsfp -ad_connect ethernet_core/i2c i2c + + +if [string equal $board K26] { + ad_connect ethernet_core/sfp_led sfp_led + + ad_connect ethernet_core/sfp_rx_p sfp_rx_p + ad_connect ethernet_core/sfp_rx_n sfp_rx_n + ad_connect ethernet_core/sfp_tx_p sfp_tx_p + ad_connect ethernet_core/sfp_tx_n sfp_tx_n + ad_connect ethernet_core/sfp_mgt_refclk_p sfp_mgt_refclk_p + ad_connect ethernet_core/sfp_mgt_refclk_n sfp_mgt_refclk_n + + ad_connect ethernet_core/sfp_tx_disable sfp_tx_disable + ad_connect ethernet_core/sfp_mod_abs sfp_mod_abs + ad_connect ethernet_core/sfp_rx_los sfp_rx_los + ad_connect ethernet_core/sfp_tx_fault sfp_tx_fault + + ad_connect ethernet_core/sfp_i2c_scl sfp_i2c_scl + ad_connect ethernet_core/sfp_i2c_sda sfp_i2c_sda + + ad_connect ethernet_core/ptp_clock corundum_core/ptp_clock + ad_connect corundum_core/ptp_clk ethernet_core/ptp_clk + ad_connect corundum_core/ptp_rst ethernet_core/ptp_rst + ad_connect corundum_core/ptp_sample_clk ethernet_core/ptp_sample_clk + ad_connect corundum_core/s_axis_stat ethernet_core/m_axis_stat +} else { + ad_connect ethernet_core/clk_125mhz clk_125mhz + ad_connect ethernet_core/rst_125mhz rst_125mhz + ad_connect ethernet_core/qsfp_drp_clk clk_125mhz + ad_connect ethernet_core/qsfp_drp_rst rst_125mhz + ad_connect ethernet_core/qsfp_mgt_refclk qsfp_mgt_refclk + ad_connect ethernet_core/qsfp_mgt_refclk_bufg qsfp_mgt_refclk_bufg + ad_connect ethernet_core/qsfp_rst qsfp_rst + ad_connect ethernet_core/fpga_boot fpga_boot + ad_connect ethernet_core/qspi_clk qspi_clk + + ad_connect ethernet_core/qspi0 qspi0 + ad_connect ethernet_core/qspi1 qspi1 + ad_connect ethernet_core/qsfp qsfp + ad_connect ethernet_core/i2c i2c + + ad_connect corundum_core/ptp_clk qsfp_mgt_refclk_bufg + ad_connect corundum_core/ptp_rst ptp_rst + ad_connect corundum_core/ptp_sample_clk clk_125mhz + + ad_connect corundum_core/hbm_clk hbm_clk + ad_connect corundum_core/hbm_rst hbm_rst + ad_connect corundum_core/ddr_clk ddr_clk + ad_connect corundum_core/ddr_rst ddr_rst + ad_connect corundum_core/ddr_status ddr_status + ad_connect corundum_core/hbm_status hbm_status + + ad_connect corundum_core/s_axis_stat_tvalid GND +} + +ad_connect ethernet_core/ctrl_reg corundum_core/ctrl_reg if {$APP_ENABLE == 1} { ad_ip_instance application_core application_core [list \ @@ -385,7 +547,7 @@ if {$APP_ENABLE == 1} { ad_connect application_core/ptp_clock corundum_core/ptp_clock_app ad_connect application_core/s_axil_ctrl s_axil_application - + ad_connect application_core/input_axis_tvalid input_axis_tvalid ad_connect application_core/input_axis_tdata input_axis_tdata ad_connect application_core/input_axis_tready input_axis_tready @@ -448,7 +610,7 @@ if {$APP_ENABLE == 1} { if {$APP_AXIS_IF_ENABLE} { ad_connect application_core/m_axis_if_tx corundum_core/m_axis_if_tx_app ad_connect application_core/s_axis_if_tx corundum_core/s_axis_if_tx_app - + ad_connect application_core/m_axis_if_rx corundum_core/m_axis_if_rx_app ad_connect application_core/s_axis_if_rx corundum_core/s_axis_if_rx_app @@ -483,24 +645,25 @@ if {$APP_ENABLE == 1} { if {$APP_STAT_ENABLE} { ad_connect application_core/m_axis_stat corundum_core/m_axis_stat_app } + } current_bd_instance / -ad_ip_instance proc_sys_reset corundum_rstgen [list \ - C_EXT_RST_WIDTH 1 \ - C_AUX_RESET_HIGH.VALUE_SRC USER \ - C_AUX_RESET_HIGH 1 \ -] - -ad_connect corundum_hierarchy/rst_corundum corundum_rstgen/peripheral_reset - -if {![string equal $CPU Zynq]} { - ad_ip_instance axi_gpio corundum_gpio_reset [list \ - C_ALL_OUTPUTS 1 \ - C_DOUT_DEFAULT 0x00000000 \ - C_GPIO_WIDTH 1 \ +if [string equal $board VCU118] { + ad_ip_instance proc_sys_reset corundum_rstgen [list \ + C_EXT_RST_WIDTH 1 \ + C_AUX_RESET_HIGH.VALUE_SRC USER \ + C_AUX_RESET_HIGH 1 \ ] - ad_connect corundum_gpio_reset/gpio_io_o corundum_rstgen/aux_reset_in -} + ad_connect corundum_hierarchy/rst_corundum corundum_rstgen/peripheral_reset + + if {![string equal $CPU Zynq]} { + ad_ip_instance axi_gpio corundum_gpio_reset [list \ + C_ALL_OUTPUTS 1 \ + C_DOUT_DEFAULT 0x00000000 \ + C_GPIO_WIDTH 1 \ + ] + } +} \ No newline at end of file diff --git a/library/corundum/scripts/corundum_k26_cfg.tcl b/library/corundum/scripts/corundum_k26_cfg.tcl new file mode 100755 index 00000000000..8bd117989b0 --- /dev/null +++ b/library/corundum/scripts/corundum_k26_cfg.tcl @@ -0,0 +1,153 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" +set tag_ver 0.0.1 + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +# FW and board IDs +set fpga_id [expr 0x4A49093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x9104] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# FW ID block +set FPGA_ID [format "32'h%08x" $fpga_id] +set FW_ID [format "32'h%08x" $fw_id] +set FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +set BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +set BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +set BUILD_DATE "32'd${build_date}" +set GIT_HASH "32'h${git_hash}" +set RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +set TDMA_BER_ENABLE "0" + +# Structural configuration +set IF_COUNT "1" +set PORTS_PER_IF "1" +set PORT_COUNT "1" +set SCHED_PER_IF $PORTS_PER_IF +set PORT_MASK "0" + +# Clock configuration +set CLK_PERIOD_NS_NUM "4" +set CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +set PTP_CLOCK_PIPELINE "0" +set PTP_CLOCK_CDC_PIPELINE "0" +set PTP_PORT_CDC_PIPELINE "0" +set PTP_PEROUT_ENABLE "1" +set PTP_PEROUT_COUNT "1" + +# Queue manager configuration +set EVENT_QUEUE_OP_TABLE_SIZE "32" +set TX_QUEUE_OP_TABLE_SIZE "32" +set RX_QUEUE_OP_TABLE_SIZE "32" +set CQ_OP_TABLE_SIZE "32" +set EQN_WIDTH "2" +set TX_QUEUE_INDEX_WIDTH "5" +set RX_QUEUE_INDEX_WIDTH "5" +set CQN_WIDTH [expr max($TX_QUEUE_INDEX_WIDTH, $RX_QUEUE_INDEX_WIDTH) + 1] +set TX_QUEUE_PIPELINE [expr 3 + max($TX_QUEUE_INDEX_WIDTH - 12, 0)] +set RX_QUEUE_PIPELINE [expr 3 + max($RX_QUEUE_INDEX_WIDTH - 12, 0)] +set EQ_PIPELINE "3" +set CQ_PIPELINE [expr 3 + max($CQN_WIDTH - 12, 0)] + +# TX and RX engine configuration +set TX_DESC_TABLE_SIZE "32" +set RX_DESC_TABLE_SIZE "32" +set RX_INDIR_TBL_ADDR_WIDTH [expr min($RX_QUEUE_INDEX_WIDTH, 8)] + +# Scheduler configuration +set TX_SCHEDULER_OP_TABLE_SIZE $TX_DESC_TABLE_SIZE +set TX_SCHEDULER_PIPELINE $TX_QUEUE_PIPELINE +set TDMA_INDEX_WIDTH "6" + +# Interface configuration +set PTP_TS_ENABLE "1" +set TX_CPL_FIFO_DEPTH "32" +set TX_CHECKSUM_ENABLE "1" +set RX_HASH_ENABLE "1" +set RX_CHECKSUM_ENABLE "1" +set PFC_ENABLE "1" +set LFC_ENABLE $PFC_ENABLE +set ENABLE_PADDING "1" +set ENABLE_DIC "1" +set MIN_FRAME_LENGTH "64" +set TX_FIFO_DEPTH "32768" +set RX_FIFO_DEPTH "65536" +set MAX_TX_SIZE "9214" +set MAX_RX_SIZE "9214" +set TX_RAM_SIZE "32768" +set RX_RAM_SIZE "32768" + +# Application block configuration +set APP_ID "32'h00000000" +set APP_ENABLE "0" +set APP_CTRL_ENABLE "0" +set APP_DMA_ENABLE "0" +set APP_AXIS_DIRECT_ENABLE "0" +set APP_AXIS_SYNC_ENABLE "0" +set APP_AXIS_IF_ENABLE "0" +set APP_STAT_ENABLE "0" + +# AXI DMA interface configuration +# dict set params AXI_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $s_axi_dma] +set AXI_ADDR_WIDTH 64 +set AXI_ID_WIDTH 8 + +# DMA interface configuration +set DMA_IMM_ENABLE "0" +set DMA_IMM_WIDTH "32" +set DMA_LEN_WIDTH "16" +set DMA_TAG_WIDTH "16" +set RAM_ADDR_WIDTH [expr int(ceil(log(max($TX_RAM_SIZE, $RX_RAM_SIZE))/log(2)))] +set RAM_PIPELINE "2" +# NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface +# pin) yields 256 for the maximum burst length, instead of 16, which is +# the actually supported length (due to ZynqMP using AXI3 internally). +#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_dma] +set AXI_DMA_MAX_BURST_LEN "16" + +# AXI lite interface configuration (control) +set AXIL_CTRL_DATA_WIDTH 32 +set AXIL_CTRL_ADDR_WIDTH 24 + +# AXI lite interface configuration (application control) +set AXIL_APP_CTRL_DATA_WIDTH 32 +set AXIL_APP_CTRL_ADDR_WIDTH 24 + +set AXI_DATA_WIDTH 128 +set AXI_ADDR_WIDTH 64 +set AXI_ID_WIDTH 8 + +# Interrupt configuration +set IRQ_COUNT "8" +set IRQ_STRETCH "10" + +# Ethernet interface configuration +set AXIS_ETH_TX_PIPELINE "0" +set AXIS_ETH_TX_FIFO_PIPELINE "2" +set AXIS_ETH_TX_TS_PIPELINE "0" +set AXIS_ETH_RX_PIPELINE "0" +set AXIS_ETH_RX_FIFO_PIPELINE "2" + +# Statistics counter subsystem +set STAT_ENABLE "0" +set STAT_DMA_ENABLE "0" +set STAT_AXI_ENABLE "0" +set STAT_INC_WIDTH "24" +set STAT_ID_WIDTH "12" \ No newline at end of file diff --git a/projects/ad_gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl b/projects/ad_gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl index b3732b6a0c3..c81c1b2fdde 100644 --- a/projects/ad_gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl +++ b/projects/ad_gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl @@ -4,6 +4,8 @@ ############################################################################### source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/library/corundum/scripts/corundum_ad_gmsl2eth_sl_cfg.tcl +source $ad_hdl_dir/library/corundum/scripts/corundum.tcl # GMSL create_bd_port -dir I ap_rstn_frmbuf_0 @@ -42,6 +44,9 @@ create_bd_port -dir I sfp_tx_fault create_bd_port -dir I sfp_rx_los create_bd_port -dir I sfp_mod_abs +create_bd_port -dir IO sfp_i2c_scl +create_bd_port -dir IO sfp_i2c_sda + create_bd_port -dir O ref_clk0 create_bd_port -dir O -from 1 -to 0 led @@ -448,154 +453,7 @@ ad_cpu_interrupt ps-5 mb-5 v_frmbuf_7/interrupt # Corundum NIC -ad_ip_instance corundum corundum - -# collect build information -set build_date [clock seconds] -set git_hash 00000000 -catch { - set git_hash [exec git rev-parse --short=8 HEAD] -} -set tag_ver 0.0.0 - -# FW and board IDs -set fpga_id [expr 0x4A49093] -set fw_id [expr 0x00000000] -set fw_ver $tag_ver -set board_vendor_id [expr 0x10ee] -set board_device_id [expr 0x9104] -set board_ver 1.0 -set release_info [expr 0x00000000] - -# General variables -set IRQ_SIZE 8 -set PORTS_PER_IF "1" -set TX_QUEUE_INDEX_WIDTH "5" -set RX_QUEUE_INDEX_WIDTH "5" -set CQN_WIDTH [expr max($TX_QUEUE_INDEX_WIDTH, $RX_QUEUE_INDEX_WIDTH) + 1] -set TX_QUEUE_PIPELINE [expr 3 + max($TX_QUEUE_INDEX_WIDTH - 12, 0)] -set RX_QUEUE_PIPELINE [expr 3 + max($RX_QUEUE_INDEX_WIDTH - 12, 0)] -set TX_DESC_TABLE_SIZE "32" -set RX_DESC_TABLE_SIZE "32" -set TX_RAM_SIZE "32768" -set RX_RAM_SIZE "32768" - -# FW ID block -ad_ip_parameter corundum CONFIG.FPGA_ID [format "32'h%08x" $fpga_id] -ad_ip_parameter corundum CONFIG.FW_ID [format "32'h%08x" $fw_id] -ad_ip_parameter corundum CONFIG.FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] -ad_ip_parameter corundum CONFIG.BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] -ad_ip_parameter corundum CONFIG.BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] -ad_ip_parameter corundum CONFIG.BUILD_DATE "32'd${build_date}" -ad_ip_parameter corundum CONFIG.GIT_HASH "32'h${git_hash}" -ad_ip_parameter corundum CONFIG.RELEASE_INFO [format "32'h%08x" $release_info] - -# Board configuration -ad_ip_parameter corundum CONFIG.TDMA_BER_ENABLE "0" - -# Structural configuration -ad_ip_parameter corundum CONFIG.IF_COUNT "1" -ad_ip_parameter corundum CONFIG.PORTS_PER_IF $PORTS_PER_IF -ad_ip_parameter corundum CONFIG.SCHED_PER_IF $PORTS_PER_IF -ad_ip_parameter corundum CONFIG.PORT_MASK "0" - -# Clock configuration -ad_ip_parameter corundum CONFIG.CLK_PERIOD_NS_NUM "4" -ad_ip_parameter corundum CONFIG.CLK_PERIOD_NS_DENOM "1" - -# PTP configuration -ad_ip_parameter corundum CONFIG.PTP_CLOCK_PIPELINE "0" -ad_ip_parameter corundum CONFIG.PTP_CLOCK_CDC_PIPELINE "0" -ad_ip_parameter corundum CONFIG.PTP_PORT_CDC_PIPELINE "0" -ad_ip_parameter corundum CONFIG.PTP_PEROUT_ENABLE "1" -ad_ip_parameter corundum CONFIG.PTP_PEROUT_COUNT "1" - -# Queue manager configuration -ad_ip_parameter corundum CONFIG.EVENT_QUEUE_OP_TABLE_SIZE "32" -ad_ip_parameter corundum CONFIG.TX_QUEUE_OP_TABLE_SIZE "32" -ad_ip_parameter corundum CONFIG.RX_QUEUE_OP_TABLE_SIZE "32" -ad_ip_parameter corundum CONFIG.CQ_OP_TABLE_SIZE "32" -ad_ip_parameter corundum CONFIG.EQN_WIDTH "2" -ad_ip_parameter corundum CONFIG.TX_QUEUE_INDEX_WIDTH $TX_QUEUE_INDEX_WIDTH -ad_ip_parameter corundum CONFIG.RX_QUEUE_INDEX_WIDTH $RX_QUEUE_INDEX_WIDTH -ad_ip_parameter corundum CONFIG.CQN_WIDTH $CQN_WIDTH -ad_ip_parameter corundum CONFIG.EQ_PIPELINE "3" -ad_ip_parameter corundum CONFIG.TX_QUEUE_PIPELINE $TX_QUEUE_PIPELINE -ad_ip_parameter corundum CONFIG.RX_QUEUE_PIPELINE $RX_QUEUE_PIPELINE -ad_ip_parameter corundum CONFIG.CQ_PIPELINE [expr 3 + max($CQN_WIDTH - 12, 0)] - -# TX and RX engine configuration -ad_ip_parameter corundum CONFIG.TX_DESC_TABLE_SIZE $TX_DESC_TABLE_SIZE -ad_ip_parameter corundum CONFIG.RX_DESC_TABLE_SIZE $RX_DESC_TABLE_SIZE -ad_ip_parameter corundum CONFIG.RX_INDIR_TBL_ADDR_WIDTH [expr min($RX_QUEUE_INDEX_WIDTH, 8)] - -# Scheduler configuration -ad_ip_parameter corundum CONFIG.TX_SCHEDULER_OP_TABLE_SIZE $TX_DESC_TABLE_SIZE -ad_ip_parameter corundum CONFIG.TX_SCHEDULER_PIPELINE $TX_QUEUE_PIPELINE -ad_ip_parameter corundum CONFIG.TDMA_INDEX_WIDTH "6" - -# Interface configuration -ad_ip_parameter corundum CONFIG.PTP_TS_ENABLE "1" -ad_ip_parameter corundum CONFIG.TX_CPL_FIFO_DEPTH "32" -ad_ip_parameter corundum CONFIG.TX_CHECKSUM_ENABLE "1" -ad_ip_parameter corundum CONFIG.RX_HASH_ENABLE "1" -ad_ip_parameter corundum CONFIG.RX_CHECKSUM_ENABLE "1" -ad_ip_parameter corundum CONFIG.TX_FIFO_DEPTH "32768" -ad_ip_parameter corundum CONFIG.RX_FIFO_DEPTH "32768" -ad_ip_parameter corundum CONFIG.MAX_TX_SIZE "9214" -ad_ip_parameter corundum CONFIG.MAX_RX_SIZE "9214" -ad_ip_parameter corundum CONFIG.TX_RAM_SIZE $TX_RAM_SIZE -ad_ip_parameter corundum CONFIG.RX_RAM_SIZE $RX_RAM_SIZE - -# Application block configuration -ad_ip_parameter corundum CONFIG.APP_ID "32'h00000000" -ad_ip_parameter corundum CONFIG.APP_ENABLE "0" -ad_ip_parameter corundum CONFIG.APP_CTRL_ENABLE "1" -ad_ip_parameter corundum CONFIG.APP_DMA_ENABLE "1" -ad_ip_parameter corundum CONFIG.APP_AXIS_DIRECT_ENABLE "1" -ad_ip_parameter corundum CONFIG.APP_AXIS_SYNC_ENABLE "1" -ad_ip_parameter corundum CONFIG.APP_AXIS_IF_ENABLE "1" -ad_ip_parameter corundum CONFIG.APP_STAT_ENABLE "1" - -# AXI DMA interface configuration -ad_ip_parameter corundum CONFIG.AXI_DATA_WIDTH [get_property CONFIG.PSU__SAXIGP0__DATA_WIDTH [get_bd_cells sys_ps8]] -ad_ip_parameter corundum CONFIG.AXI_ADDR_WIDTH 64 -ad_ip_parameter corundum CONFIG.AXI_ID_WIDTH 6 - -# DMA interface configuration -ad_ip_parameter corundum CONFIG.DMA_IMM_ENABLE "0" -ad_ip_parameter corundum CONFIG.DMA_IMM_WIDTH "32" -ad_ip_parameter corundum CONFIG.DMA_LEN_WIDTH "16" -ad_ip_parameter corundum CONFIG.DMA_TAG_WIDTH "16" -ad_ip_parameter corundum CONFIG.RAM_ADDR_WIDTH [expr int(ceil(log(max($TX_RAM_SIZE, $RX_RAM_SIZE))/log(2)))] -ad_ip_parameter corundum CONFIG.RAM_PIPELINE "2" -ad_ip_parameter corundum CONFIG.AXI_DMA_MAX_BURST_LEN 16 - -# AXI lite interface configuration (control) -ad_ip_parameter corundum CONFIG.AXIL_CTRL_DATA_WIDTH 32 -ad_ip_parameter corundum CONFIG.AXIL_CTRL_ADDR_WIDTH 24 - -# AXI lite interface configuration (application control) -ad_ip_parameter corundum CONFIG.AXIL_APP_CTRL_DATA_WIDTH 32 -ad_ip_parameter corundum CONFIG.AXIL_APP_CTRL_ADDR_WIDTH 24 - -# Interrupt configuration -ad_ip_parameter corundum CONFIG.IRQ_COUNT $IRQ_SIZE -ad_ip_parameter corundum CONFIG.IRQ_STRETCH "10" - -# Ethernet interface configuration -ad_ip_parameter corundum CONFIG.AXIS_ETH_TX_PIPELINE "0" -ad_ip_parameter corundum CONFIG.AXIS_ETH_TX_FIFO_PIPELINE "2" -ad_ip_parameter corundum CONFIG.AXIS_ETH_TX_TS_PIPELINE "0" -ad_ip_parameter corundum CONFIG.AXIS_ETH_RX_PIPELINE "0" -ad_ip_parameter corundum CONFIG.AXIS_ETH_RX_FIFO_PIPELINE "2" - -# Statistics counter subsystem -ad_ip_parameter corundum CONFIG.STAT_ENABLE "1" -ad_ip_parameter corundum CONFIG.STAT_DMA_ENABLE "1" -ad_ip_parameter corundum CONFIG.STAT_AXI_ENABLE "1" -ad_ip_parameter corundum CONFIG.STAT_INC_WIDTH "24" -ad_ip_parameter corundum CONFIG.STAT_ID_WIDTH "12" +#ad_ip_instance corundum corundum ad_ip_instance clk_wiz clk10_gen ad_ip_parameter clk10_gen CONFIG.CLKIN1_UI_JITTER {0} @@ -607,42 +465,51 @@ ad_ip_parameter clk10_gen CONFIG.PRIM_SOURCE {Global_buffer} ad_ip_parameter clk10_gen CONFIG.RESET_TYPE {ACTIVE_LOW} ad_ip_parameter clk10_gen CONFIG.USE_LOCKED {false} -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 sfp_iic -ad_connect sfp_iic corundum/iic +ad_ip_instance clk_wiz clk125_gen +ad_ip_parameter clk125_gen CONFIG.CLKIN1_UI_JITTER {0} +ad_ip_parameter clk125_gen CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE {50.000} +ad_ip_parameter clk125_gen CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000} +ad_ip_parameter clk125_gen CONFIG.CLKOUT1_REQUESTED_PHASE {0.000} +ad_ip_parameter clk125_gen CONFIG.PRIMITIVE {PLL} +ad_ip_parameter clk125_gen CONFIG.PRIM_SOURCE {Global_buffer} +ad_ip_parameter clk125_gen CONFIG.RESET_TYPE {ACTIVE_LOW} +ad_ip_parameter clk125_gen CONFIG.USE_LOCKED {false} + +ad_ip_instance proc_sys_reset sys_125m_rstgen +ad_connect sys_125m_rstgen/slowest_sync_clk clk125_gen/clk_out1 +ad_connect sys_125m_rstgen/ext_reset_in $sys_dma_resetn -ad_connect led corundum/led -ad_connect sfp_led corundum/sfp_led +ad_connect sfp_i2c_scl corundum_hierarchy/sfp_i2c_scl +ad_connect sfp_i2c_sda corundum_hierarchy/sfp_i2c_sda -set_property verilog_define {APP_CUSTOM_PORTS_ENABLE APP_CUSTOM_PARAMS_ENABLE} [get_filesets sources_1] +connect_bd_net [get_bd_ports led] [get_bd_pins corundum_hierarchy/ethernet_core/led] +ad_connect corundum_hierarchy/clk_corundum $sys_dma_clk +ad_connect corundum_hierarchy/rst_corundum $sys_dma_reset ad_connect clk10_gen/clk_in1 $sys_dma_clk ad_connect clk10_gen/resetn $sys_dma_resetn +ad_connect clk125_gen/clk_in1 $sys_dma_clk +ad_connect clk125_gen/resetn $sys_dma_resetn -ad_connect corundum/clk $sys_dma_clk -ad_connect corundum/rst $sys_dma_reset - -ad_connect corundum/sfp_rx_p sfp_rx_p -ad_connect corundum/sfp_rx_n sfp_rx_n -ad_connect corundum/sfp_tx_p sfp_tx_p -ad_connect corundum/sfp_tx_n sfp_tx_n -ad_connect corundum/sfp_mgt_refclk_p sfp_mgt_refclk_p -ad_connect corundum/sfp_mgt_refclk_n sfp_mgt_refclk_n +ad_connect corundum_hierarchy/sfp_rx_p sfp_rx_p +ad_connect corundum_hierarchy/sfp_rx_n sfp_rx_n +ad_connect corundum_hierarchy/sfp_tx_p sfp_tx_p +ad_connect corundum_hierarchy/sfp_tx_n sfp_tx_n +ad_connect corundum_hierarchy/sfp_mgt_refclk_p sfp_mgt_refclk_p +ad_connect corundum_hierarchy/sfp_mgt_refclk_n sfp_mgt_refclk_n -ad_connect corundum/sfp_tx_disable sfp_tx_disable -ad_connect corundum/sfp_mod_abs sfp_mod_abs -ad_connect corundum/sfp_rx_los sfp_rx_los -ad_connect corundum/sfp_tx_fault sfp_tx_fault +ad_connect corundum_hierarchy/sfp_tx_disable sfp_tx_disable +ad_connect corundum_hierarchy/sfp_mod_abs sfp_mod_abs +ad_connect corundum_hierarchy/sfp_rx_los sfp_rx_los +ad_connect corundum_hierarchy/sfp_tx_fault sfp_tx_fault ad_connect clk10_gen/clk_out1 ref_clk0 -set fifo_num_bytes 4 -set fifo_tdest_width 4 -set fifo_tuser_width 2 - set axi_clk_freq [get_property CONFIG.FREQ_HZ [get_bd_pins sys_ps8/pl_clk1]] -set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum/m_axi_dma] -set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum/s_axil_app_ctrl] -set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum/s_axil_ctrl] +set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum_hierarchy/m_axi] +set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins /corundum_hierarchy/corundum_core/m_axi] +set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins corundum_hierarchy/s_axil_corundum] +set_property CONFIG.FREQ_HZ $axi_clk_freq [get_bd_intf_pins /corundum_hierarchy/corundum_core/s_axil_ctrl] ad_ip_instance axi_interconnect smartconnect_corundum ad_ip_parameter smartconnect_corundum CONFIG.NUM_MI 2 @@ -661,8 +528,7 @@ ad_connect smartconnect_corundum/S00_ACLK $sys_dma_clk ad_connect smartconnect_corundum/M00_ACLK $sys_dma_clk ad_connect smartconnect_corundum/M01_ACLK $sys_dma_clk -ad_connect smartconnect_corundum/M00_AXI corundum/s_axil_ctrl -ad_connect smartconnect_corundum/M01_AXI corundum/s_axil_app_ctrl +ad_connect smartconnect_corundum/M00_AXI corundum_hierarchy/s_axil_corundum ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 1 ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP0__DATA_WIDTH 32 @@ -670,22 +536,19 @@ ad_connect smartconnect_corundum/S00_AXI sys_ps8/M_AXI_HPM0_FPD ad_connect sys_ps8/maxihpm0_fpd_aclk $sys_dma_clk assign_bd_address -offset 0xA000_0000 [get_bd_addr_segs \ - corundum/s_axil_ctrl/Reg -] -target_address_space sys_ps8/Data -assign_bd_address -offset 0xA800_0000 [get_bd_addr_segs \ - corundum/s_axil_app_ctrl/Reg + corundum_hierarchy/corundum_core/s_axil_ctrl/Reg ] -target_address_space sys_ps8/Data ad_ip_instance util_reduced_logic util_reduced_logic_0 ad_ip_parameter util_reduced_logic_0 CONFIG.C_OPERATION {or} -ad_ip_parameter util_reduced_logic_0 CONFIG.C_SIZE $IRQ_SIZE +ad_ip_parameter util_reduced_logic_0 CONFIG.C_SIZE {8} -ad_connect util_reduced_logic_0/Op1 corundum/core_irq +ad_connect util_reduced_logic_0/Op1 corundum_hierarchy/irq ad_cpu_interrupt ps-4 mb-4 util_reduced_logic_0/Res ad_mem_hpc0_interconnect $sys_dma_clk sys_ps8/S_AXI_HPC0_FPD -ad_mem_hpc0_interconnect $sys_dma_clk corundum/m_axi_dma +ad_mem_hpc0_interconnect $sys_dma_clk corundum_hierarchy/m_axi assign_bd_address [get_bd_addr_segs { \ sys_ps8/SAXIGP0/HPC0_LPS_OCM \ diff --git a/projects/ad_gmsl2eth_sl/k26/Makefile b/projects/ad_gmsl2eth_sl/k26/Makefile index fb57c4a9f07..e79c1ff1585 100644 --- a/projects/ad_gmsl2eth_sl/k26/Makefile +++ b/projects/ad_gmsl2eth_sl/k26/Makefile @@ -12,20 +12,30 @@ M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/corundum/scripts/corundum_ad_gmsl2eth_sl_cfg.tcl +M_DEPS += ../../../library/corundum/scripts/corundum.tcl + + EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/rb_drp.tcl EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_port.tcl -EXTERNAL_DEPS += ../../../../corundum/fpga/mqnic/KR260/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl -EXTERNAL_DEPS += ../../../../corundum/fpga/mqnic/KR260/fpga/lib/axis/syn/vivado/sync_reset.tcl -EXTERNAL_DEPS += ../../../../corundum/fpga/mqnic/KR260/fpga/lib/axis/syn/vivado/axis_async_fifo.tcl +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl +EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/tdma_ber_ch.tcl LIB_DEPS += axi_clkgen LIB_DEPS += axi_sysid LIB_DEPS += axi_pwm_gen -LIB_DEPS += corundum +#LIB_DEPS += corundum +LIB_DEPS += corundum/corundum_core +LIB_DEPS += corundum/ethernet LIB_DEPS += sysid_rom +export BOARD := K26 + include ../../scripts/project-xilinx.mk diff --git a/projects/ad_gmsl2eth_sl/k26/system_project.tcl b/projects/ad_gmsl2eth_sl/k26/system_project.tcl index 6a8f28c1923..4f7a9355675 100644 --- a/projects/ad_gmsl2eth_sl/k26/system_project.tcl +++ b/projects/ad_gmsl2eth_sl/k26/system_project.tcl @@ -17,9 +17,11 @@ adi_project_files ad_gmsl2eth_sl_k26 [list \ "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl" \ "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl" \ "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_port.tcl" \ - "$ad_hdl_dir/../corundum/fpga/mqnic/KR260/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl" \ - "$ad_hdl_dir/../corundum/fpga/mqnic/KR260/fpga/lib/axis/syn/vivado/sync_reset.tcl" \ - "$ad_hdl_dir/../corundum/fpga/mqnic/KR260/fpga/lib/axis/syn/vivado/axis_async_fifo.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl" \ "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/tdma_ber_ch.tcl" \ "$ad_hdl_dir/library/common/ad_iobuf.v" ] diff --git a/projects/ad_gmsl2eth_sl/k26/system_top.v b/projects/ad_gmsl2eth_sl/k26/system_top.v index 94cde87be9c..f4a0c11e626 100644 --- a/projects/ad_gmsl2eth_sl/k26/system_top.v +++ b/projects/ad_gmsl2eth_sl/k26/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -26,7 +26,7 @@ // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // @@ -181,15 +181,15 @@ module system_top ( .sfp_tx_n (sfp_tx_n), .sfp_tx_p (sfp_tx_p), .sfp_tx_disable (sfp_tx_disable), - .sfp_tx_fault(sfp_tx_fault), - .sfp_rx_los(sfp_rx_los), - .sfp_mod_abs(sfp_mod_abs), - .sfp_iic_scl_io(sfp_i2c_scl), - .sfp_iic_sda_io(sfp_i2c_sda), - .tca_iic_scl_io(tca_i2c_scl), - .tca_iic_sda_io(tca_i2c_sda), - .led(), - .sfp_led(sfp_led), + .sfp_tx_fault (sfp_tx_fault), + .sfp_rx_los (sfp_rx_los), + .sfp_mod_abs (sfp_mod_abs), + .sfp_i2c_scl (sfp_i2c_scl), + .sfp_i2c_sda (sfp_i2c_sda), + .tca_iic_scl_io (tca_i2c_scl), + .tca_iic_sda_io (tca_i2c_sda), + .led (), + .sfp_led (sfp_led), .spi0_csn (ad9545_cs), .spi0_miso (ad9545_miso), .spi0_mosi (ad9545_mosi),