diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl b/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl index 0ab3092c71b..7b1a64ae4af 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -34,8 +34,8 @@ proc p_elaboration {} { # clock and reset interface - ad_interface clock clk input 1 - ad_interface reset reset_n input 1 if_clk + ad_interface clock clk input 1 + ad_interface reset-n reset_n input 1 if_clk add_interface sdo axi4stream end add_interface_port sdo sdo_ready tready output 1 diff --git a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_hw.tcl b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_hw.tcl index 0d5eddfaf70..036fa88deb0 100644 --- a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_hw.tcl +++ b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -66,7 +66,7 @@ proc p_elaboration {} { set if_clk if_clk } - ad_interface reset reset_n output 1 $if_clk + ad_interface reset-n reset_n output 1 $if_clk ad_interface signal offload_trigger input 1 if_pwm diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl index 8f9e2f5d450..e96c981a925 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -52,7 +52,7 @@ proc p_elaboration {} { # Microprocessor interface ad_interface clock up_clk input 1 - ad_interface reset up_rstn input 1 if_up_clk + ad_interface reset-n up_rstn input 1 if_up_clk ad_interface signal up_wreq input 1 ad_interface signal up_wack output 1 ad_interface signal up_waddr input 14 @@ -115,8 +115,8 @@ proc p_elaboration {} { # SPI Engine interfaces - ad_interface clock spi_clk input 1 - ad_interface reset spi_resetn output 1 if_spi_clk + ad_interface clock spi_clk input 1 + ad_interface reset-n spi_resetn output 1 if_spi_clk add_interface cmd axi4stream start add_interface_port cmd cmd_ready tready input 1 diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl index 85385a42a0c..96e1d1cbfe2 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -32,7 +32,7 @@ proc p_elaboration {} { # clock and reset interface ad_interface clock clk input 1 - ad_interface reset resetn input 1 if_clk + ad_interface reset-n resetn input 1 if_clk ad_interface signal active output 1 diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl index a64057fee69..888980195b3 100644 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl @@ -23,8 +23,8 @@ proc p_elaboration {} { # clock and reset interface - ad_interface clock clk input 1 - ad_interface reset resetn input 1 if_clk + ad_interface clock clk input 1 + ad_interface reset-n resetn input 1 if_clk # interconnect direction interface diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl index 86fb0008b83..07c15d4d510 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl @@ -32,7 +32,6 @@ proc p_elaboration {} { # control interface ad_interface clock ctrl_clk input 1 - ad_interface reset spi_resetn input 1 if_spi_clk add_interface ctrl_cmd_wr conduit end add_interface_port ctrl_cmd_wr ctrl_cmd_wr_en wre input 1 @@ -69,8 +68,8 @@ proc p_elaboration {} { # SPI Engine interfaces - ad_interface clock spi_clk input 1 - ad_interface resetn spi_resetn input 1 if_spi_clk + ad_interface clock spi_clk input 1 + ad_interface reset-n spi_resetn input 1 if_spi_clk ad_interface signal trigger input 1 if_pwm diff --git a/library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl b/library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl index 38d44d5c401..d062f58a46c 100644 --- a/library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl +++ b/library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ################################################################################# @@ -27,8 +27,8 @@ proc p_elaboration {} { # clock and reset interface - ad_interface clock clk input 1 - ad_interface reset resetn input 1 if_clk + ad_interface clock clk input 1 + ad_interface reset-n resetn input 1 if_clk ad_interface signal spi_active input 1 active ad_interface signal data_ready output 1 if_pwm diff --git a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl index a3930001aec..30623af5e6e 100644 --- a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl +++ b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl @@ -35,18 +35,6 @@ add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} -# bridges - -add_instance clock_bridge_0 altera_clock_bridge -set_instance_parameter_value clock_bridge_0 {EXPLICIT_CLOCK_RATE} {0.0} -set_instance_parameter_value clock_bridge_0 {NUM_CLOCK_OUTPUTS} {1} - -add_instance reset_bridge_0 altera_reset_bridge -set_instance_parameter_value reset_bridge_0 {ACTIVE_LOW_RESET} {1} -set_instance_parameter_value reset_bridge_0 {NUM_RESET_OUTPUTS} {1} -set_instance_parameter_value reset_bridge_0 {SYNCHRONOUS_EDGES} {none} -set_instance_parameter_value reset_bridge_0 {USE_RESET_REQUEST} {0} - # spi_engine_offload add_instance spi_engine_offload_0 spi_engine_offload @@ -62,22 +50,15 @@ add_interface ad4170_spi_cs conduit end add_interface ad4170_spi_sdi conduit end add_interface ad4170_spi_sdo conduit end add_interface ad4170_spi_trigger conduit end -add_interface ad4170_spi_resetn reset source set_interface_property ad4170_spi_cs EXPORT_OF spi_engine_execution_0.if_cs set_interface_property ad4170_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk set_interface_property ad4170_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi set_interface_property ad4170_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo set_interface_property ad4170_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger -set_interface_property ad4170_spi_resetn EXPORT_OF reset_bridge_0.out_reset - -add_connection axi_spi_engine_0.if_spi_resetn reset_bridge_0.in_reset # clocks -add_interface ad4170_spi_clk clock source -set_interface_property ad4170_spi_clk EXPORT_OF clock_bridge_0.out_clk - add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock add_connection sys_clk.clk axi_dmac_0.s_axi_clock @@ -88,7 +69,6 @@ add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock -add_connection sys_dma_clk.clk clock_bridge_0.in_clk # resets diff --git a/projects/ad4170_asdz/de10nano/system_top.v b/projects/ad4170_asdz/de10nano/system_top.v index 546a737ca87..95f5d3385ed 100755 --- a/projects/ad4170_asdz/de10nano/system_top.v +++ b/projects/ad4170_asdz/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -147,9 +147,6 @@ module system_top ( wire i2c0_scl_in_clk; wire spi_trigger; - wire spi_clk_s; - wire spi_resetn; - wire spi_trigger_ed; // adc control gpio assign @@ -160,6 +157,8 @@ module system_top ( assign gpio_i[33:32] = ad4170_dig_aux[1:0]; + assign spi_trigger = ~gpio_i[32]; + // bd gpio assign gpio_i[13:8] = gpio_bd_i[5:0]; @@ -191,22 +190,6 @@ module system_top ( .o(i2c0_sda), .io(hdmi_i2c_sda)); - sync_bits #( - .ASYNC_CLK(1) - ) i_sync_bits ( - .in_bits (gpio_i[32]), - .out_resetn (~spi_resetn), - .out_clk (spi_clk_s), - .out_bits (spi_trigger_ed)); - - ad_edge_detect#( - .EDGE(1) - ) i_ad_edge_detect ( - .clk (spi_clk_s), - .rst (1'b0), - .signal_in (spi_trigger_ed), - .signal_out (spi_trigger)); - system_bd i_system_bd ( .sys_clk_clk (sys_clk), .sys_hps_h2f_reset_reset_n (sys_resetn), @@ -283,8 +266,6 @@ module system_top ( .ad4170_spi_sdi_sdi (ad4170_spi_miso), .ad4170_spi_sdo_sdo (ad4170_spi_mosi), .ad4170_spi_trigger_if_pwm (spi_trigger), - .ad4170_spi_resetn_reset_n (spi_resetn), - .ad4170_spi_clk_clk (spi_clk_s), .sys_spi_MISO (1'b0), .sys_spi_MOSI (), .sys_spi_SCLK (), diff --git a/projects/ad469x_evb/common/ad469x_qsys.tcl b/projects/ad469x_evb/common/ad469x_qsys.tcl index 9f65c2bf607..fb397970fd3 100644 --- a/projects/ad469x_evb/common/ad469x_qsys.tcl +++ b/projects/ad469x_evb/common/ad469x_qsys.tcl @@ -35,18 +35,6 @@ add_instance spi_engine_interconnect_0 spi_engine_interconnect set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32} set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1} -# bridges - -add_instance clock_bridge_0 altera_clock_bridge -set_instance_parameter_value clock_bridge_0 {EXPLICIT_CLOCK_RATE} {0.0} -set_instance_parameter_value clock_bridge_0 {NUM_CLOCK_OUTPUTS} {1} - -add_instance reset_bridge_0 altera_reset_bridge -set_instance_parameter_value reset_bridge_0 {ACTIVE_LOW_RESET} {1} -set_instance_parameter_value reset_bridge_0 {NUM_RESET_OUTPUTS} {1} -set_instance_parameter_value reset_bridge_0 {SYNCHRONOUS_EDGES} {none} -set_instance_parameter_value reset_bridge_0 {USE_RESET_REQUEST} {0} - # spi_engine_offload add_instance spi_engine_offload_0 spi_engine_offload @@ -111,7 +99,6 @@ add_interface ad469x_spi_sdi conduit end add_interface ad469x_spi_sdo conduit end add_interface ad469x_spi_trigger conduit end add_interface ad469x_spi_cnv conduit end -add_interface ad469x_spi_resetn reset source set_interface_property ad469x_spi_cs EXPORT_OF spi_engine_execution_0.if_cs set_interface_property ad469x_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk @@ -119,16 +106,9 @@ set_interface_property ad469x_spi_sdi EXPORT_OF spi_engine_execution_0.if_sd set_interface_property ad469x_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo set_interface_property ad469x_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger set_interface_property ad469x_spi_cnv EXPORT_OF ad469x_trigger_gen.if_pwm_0 -set_interface_property ad469x_spi_resetn EXPORT_OF reset_bridge_0.out_reset - -add_connection axi_spi_engine_0.if_spi_resetn reset_bridge_0.in_reset # clocks -add_interface ad469x_spi_clk clock source -set_interface_property ad469x_spi_clk EXPORT_OF clock_bridge_0.out_clk - - add_connection sys_clk.clk spi_clk_pll.refclk add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk add_connection sys_clk.clk ad469x_trigger_gen.s_axi_clock diff --git a/projects/ad469x_evb/de10nano/system_top.v b/projects/ad469x_evb/de10nano/system_top.v index acdde54ea10..ce1c43e27a7 100644 --- a/projects/ad469x_evb/de10nano/system_top.v +++ b/projects/ad469x_evb/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2024 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -156,14 +156,12 @@ module system_top #( wire ad469x_spi_cs_s; wire spi_trigger; - wire spi_clk_s; - wire spi_resetn; - wire spi_trigger_ed; wire dma_xfer_req; assign ad469x_spi_cnv = (SPI_4WIRE == 0) ? ad469x_spi_cnv_s : ad469x_spi_cs_s; assign ad469x_spi_cs = ad469x_spi_cs_s; assign ad469x_spi_cnv_s = (spi_pwm & dma_xfer_req) | gpio_o[35]; + assign spi_trigger = ~ad469x_busy_alt_gp0; // adc control gpio assign @@ -206,22 +204,6 @@ module system_top #( .o(i2c0_sda), .io(hdmi_i2c_sda)); - sync_bits #( - .ASYNC_CLK(1) - ) i_sync_bits ( - .in_bits (ad469x_busy_alt_gp0), - .out_resetn (~spi_resetn), - .out_clk (spi_clk_s), - .out_bits (spi_trigger_ed)); - - ad_edge_detect#( - .EDGE(1) - ) i_ad_edge_detect ( - .clk (spi_clk_s), - .rst (1'b0), - .signal_in (spi_trigger_ed), - .signal_out (spi_trigger)); - system_bd i_system_bd ( .sys_clk_clk (sys_clk), .sys_hps_h2f_reset_reset_n (sys_resetn), @@ -297,8 +279,6 @@ module system_top #( .ad469x_spi_sclk_clk (ad469x_spi_sclk), .ad469x_spi_sdi_sdi (ad469x_spi_sdi), .ad469x_spi_sdo_sdo (ad469x_spi_sdo), - .ad469x_spi_resetn_reset_n (spi_resetn), - .ad469x_spi_clk_clk (spi_clk_s), .ad469x_spi_cnv_if_pwm (spi_pwm), .ad469x_spi_trigger_if_pwm(spi_trigger), .dma_xfer_req_xfer_req(dma_xfer_req),