From b39be617e29f73a62dcadb5b5610fbec5f4ed8c0 Mon Sep 17 00:00:00 2001 From: PopPaul2021 Date: Thu, 3 Jul 2025 09:07:49 +0300 Subject: [PATCH 1/5] library:data_offload: Expose the ASYNC_CLK When the data offload souruce and destination clock are connected to the same source there is a DRC error. By exposing the ASYNC_CLK parameter and setting it to 0 in this use-case the issue is solved. Signed-off-by: PopPaul2021 --- library/data_offload/data_offload.v | 7 ++++--- library/data_offload/data_offload_ip.tcl | 11 +++++++++-- projects/common/xilinx/data_offload_bd.tcl | 6 ++++-- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/library/data_offload/data_offload.v b/library/data_offload/data_offload.v index 5fc30db3046..ae6009c9123 100644 --- a/library/data_offload/data_offload.v +++ b/library/data_offload/data_offload.v @@ -49,7 +49,8 @@ module data_offload #( parameter AUTO_BRINGUP = 1, parameter SYNC_EXT_ADD_INTERNAL_CDC = 1, - parameter HAS_BYPASS = 1 + parameter HAS_BYPASS = 1, + parameter ASYNC_CLK = 1 ) ( // AXI4 Slave for configuration @@ -252,7 +253,7 @@ module data_offload #( .S_DATA_WIDTH (SRC_DATA_WIDTH), .ADDRESS_WIDTH (SRC_ADDR_WIDTH_BYPASS), .M_DATA_WIDTH (DST_DATA_WIDTH), - .ASYNC_CLK (1) + .ASYNC_CLK (ASYNC_CLK) ) i_bypass_fifo ( .m_axis_aclk (m_axis_aclk), .m_axis_aresetn (dst_rstn), @@ -352,7 +353,7 @@ module data_offload #( util_axis_fifo #( .DATA_WIDTH(MEM_SIZE_LOG2), .ADDRESS_WIDTH(0), - .ASYNC_CLK(1) + .ASYNC_CLK(ASYNC_CLK) ) i_measured_length_cdc ( .s_axis_aclk(s_axis_aclk), .s_axis_aresetn(s_axis_aresetn), diff --git a/library/data_offload/data_offload_ip.tcl b/library/data_offload/data_offload_ip.tcl index c1373c06ce9..d3149f7666b 100644 --- a/library/data_offload/data_offload_ip.tcl +++ b/library/data_offload/data_offload_ip.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -187,17 +187,20 @@ foreach {k v} { \ "HAS_BYPASS" "true" \ "DST_CYCLIC_EN" "true" \ "SYNC_EXT_ADD_INTERNAL_CDC" "true" \ + "ASYNC_CLK" "true" \ } { \ set_property -dict [list \ "value_format" "bool" \ "value_format" "bool" \ "value" $v \ + "value_format" "bool" \ ] \ [ipx::get_user_parameters $k -of_objects $cc] set_property -dict [list \ "value_format" "bool" \ "value_format" "bool" \ "value" $v \ + "value_format" "bool" \ ] \ [ipx::get_hdl_parameters $k -of_objects $cc] } @@ -277,8 +280,12 @@ set_property -dict [list \ "display_name" "Generate CDC Circuit for sync_ext" \ ] [ipgui::get_guiparamspec -name "SYNC_EXT_ADD_INTERNAL_CDC" -component $cc] +ipgui::add_param -name "ASYNC_CLK" -component $cc -parent $features_group +set_property -dict [list \ + "display_name" "Enabled the asynchronous connection of the clocks in the FIFO" \ +] [ipgui::get_guiparamspec -name "ASYNC_CLK" -component $cc] + ## Create and save the XGUI file ipx::create_xgui_files $cc ipx::save_core [ipx::current_core] - diff --git a/projects/common/xilinx/data_offload_bd.tcl b/projects/common/xilinx/data_offload_bd.tcl index b70db0fbd71..bcf1c621d61 100644 --- a/projects/common/xilinx/data_offload_bd.tcl +++ b/projects/common/xilinx/data_offload_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -11,7 +11,8 @@ proc ad_data_offload_create {instance_name destination_dwidth {axi_data_width 256} {axi_addr_width 32} - {shared_devclk 0}} { + {shared_devclk 0} + {async_clk 1}} { global ad_hdl_dir global sys_cpu_resetn @@ -54,6 +55,7 @@ proc ad_data_offload_create {instance_name DST_DATA_WIDTH $destination_dwidth \ DST_CYCLIC_EN $datapath_type \ SYNC_EXT_ADD_INTERNAL_CDC [expr {!$shared_devclk}] \ + ASYNC_CLK $async_clk \ ] if {$mem_type == 0} { From a54fc0fa26a743db52d954a8d1931d1972a4132f Mon Sep 17 00:00:00 2001 From: PopPaul2021 Date: Thu, 3 Jul 2025 09:08:42 +0300 Subject: [PATCH 2/5] docs:data_offload: Add ASYNC_CLK parameter Signed-off-by: PopPaul2021 --- docs/library/data_offload/index.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/library/data_offload/index.rst b/docs/library/data_offload/index.rst index b73ad910cb7..974eb1795fa 100644 --- a/docs/library/data_offload/index.rst +++ b/docs/library/data_offload/index.rst @@ -90,6 +90,8 @@ Configuration Parameters - If enabled the CDC circuitry for the external sync signal is added. * - HAS_BYPASS - If enabled the bypass circuitry is added. + * - ASYNC_CLK + - If enabled the FIFO is connected to asynchronous clocks. Interface -------------------------------------------------------------------------------- From 9230cd0056aa2cedd2188d046d8ef5633838662a Mon Sep 17 00:00:00 2001 From: PopPaul2021 Date: Thu, 3 Jul 2025 09:15:18 +0300 Subject: [PATCH 3/5] projects:ad9081_fmca_ebz_x_band: Fix synchronization The CDC was moved from the DO to the DMA. The DMA clock was moved from the 250MHz PS clock to a 330MHz clock generated by the clock wizard. The cache coherency was disabled in order to have the HP ports working at maximum frequency. Signed-off-by: PopPaul2021 --- .../zcu102/system_bd.tcl | 100 +++++++++++++++++- 1 file changed, 98 insertions(+), 2 deletions(-) diff --git a/projects/ad9081_fmca_ebz_x_band/zcu102/system_bd.tcl b/projects/ad9081_fmca_ebz_x_band/zcu102/system_bd.tcl index e97e37d40d0..cb65994f168 100644 --- a/projects/ad9081_fmca_ebz_x_band/zcu102/system_bd.tcl +++ b/projects/ad9081_fmca_ebz_x_band/zcu102/system_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -12,8 +12,45 @@ source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl +set CACHE_COHERENCY false + ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0 +## Add the 330MHz clock generator for the DMAs + +ad_ip_instance clk_wiz dma_clk_wiz +ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM +ad_ip_parameter dma_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW +ad_ip_parameter dma_clk_wiz CONFIG.USE_LOCKED false +ad_ip_parameter dma_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 330 +ad_ip_parameter dma_clk_wiz CONFIG.PRIM_SOURCE No_buffer + +ad_connect $sys_cpu_clk dma_clk_wiz/clk_in1 +ad_connect $sys_cpu_resetn dma_clk_wiz/resetn + +## Disconnect the sys_dma_clk and connect it to the dma_clk_wiz/clk_out1 + +ad_connect sys_dma_clk_wiz dma_clk_wiz/clk_out1 + +unset sys_dma_clk +unset sys_dma_reset +unset sys_dma_resetn + +set sys_dma_clk [get_bd_nets sys_dma_clk_wiz] + +## Add the reset instance for the 330MHz clock and connect it to the sys_dma_reset/sys_dma_resetn + +ad_ip_instance proc_sys_reset sys_dma_wiz_rstgen + +ad_connect $sys_dma_clk sys_dma_wiz_rstgen/slowest_sync_clk +ad_connect $sys_cpu_resetn sys_dma_wiz_rstgen/ext_reset_in + +ad_connect sys_dma_wiz_reset sys_dma_wiz_rstgen/peripheral_reset +ad_connect sys_dma_wiz_resetn sys_dma_wiz_rstgen/peripheral_aresetn + +set sys_dma_reset [get_bd_nets sys_dma_wiz_reset] +set sys_dma_resetn [get_bd_nets sys_dma_wiz_resetn] + source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl @@ -157,6 +194,16 @@ ad_cpu_interrupt ps-9 mb-7 axi_spi_fmc/ip2intc_irpt ad_cpu_interconnect 0x45300000 axi_spi_fmc +# changes on the AD9081 block design + +ad_ip_parameter axi_mxfe_tx_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter axi_mxfe_tx_dma CONFIG.AXIS_TUSER_SYNC 0 +ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_LENGTH_WIDTH 30 +ad_ip_parameter axi_mxfe_tx_dma CONFIG.FIFO_SIZE 32 + +ad_ip_parameter $adc_data_offload_name/i_data_offload CONFIG.ASYNC_CLK false +ad_ip_parameter $dac_data_offload_name/i_data_offload CONFIG.ASYNC_CLK false + # Connect TDD create_bd_port -dir I tdd_sync create_bd_port -dir O tdd_enabled @@ -166,8 +213,57 @@ create_bd_port -dir O tdd_tx_stingray_en set tdd_sync_in_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_tdd_0/sync_in]]] set tdd_sync_in_pin [get_bd_pins axi_tdd_0/sync_in] -ad_disconnect $tdd_sync_in_net $tdd_sync_in_pin + +# The CDC from sys_dma_clk to tx/rx_clk will be performed in the DMA instead of DO + +set adc_do_m_axis_clk_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins $adc_data_offload_name/m_axis_aclk]]] +set adc_do_m_axis_clk_pin [get_bd_pins $adc_data_offload_name/m_axis_aclk] + +set adc_dma_s_axis_clk_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk]]] +set adc_dma_s_axis_clk_pin [get_bd_pins axi_mxfe_rx_dma/s_axis_aclk] + +set adc_do_m_axis_rst_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins $adc_data_offload_name/m_axis_aresetn]]] +set adc_do_m_axis_rst_pin [get_bd_pins $adc_data_offload_name/m_axis_aresetn] + + +set dac_do_s_axis_aclk_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins $dac_data_offload_name/s_axis_aclk]]] +set dac_do_s_axis_aclk_pin [get_bd_pins $dac_data_offload_name/s_axis_aclk] + +set dac_dma_m_axis_aclk_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk]]] +set dac_dma_m_axis_aclk_pin [get_bd_pins axi_mxfe_tx_dma/m_axis_aclk] + + +set dac_do_s_axis_aresetn_net [get_bd_nets -of_objects [find_bd_objs -relation connected_to [get_bd_pins $dac_data_offload_name/s_axis_aresetn]]] +set dac_do_s_axis_aresetn_pin [get_bd_pins $dac_data_offload_name/s_axis_aresetn] + +ad_disconnect $tdd_sync_in_net $tdd_sync_in_pin +ad_disconnect $adc_do_m_axis_clk_net $adc_do_m_axis_clk_pin +ad_disconnect $adc_dma_s_axis_clk_net $adc_dma_s_axis_clk_pin +ad_disconnect $adc_do_m_axis_rst_net $adc_do_m_axis_rst_pin + +ad_disconnect $dac_do_s_axis_aclk_net $dac_do_s_axis_aclk_pin +ad_disconnect $dac_dma_m_axis_aclk_net $dac_dma_m_axis_aclk_pin +ad_disconnect $dac_do_s_axis_aresetn_net $dac_do_s_axis_aresetn_pin + +ad_connect rx_device_clk $adc_data_offload_name/m_axis_aclk +ad_connect tx_device_clk $dac_data_offload_name/s_axis_aclk + +ad_connect tx_device_clk axi_mxfe_tx_dma/m_axis_aclk +ad_connect rx_device_clk axi_mxfe_rx_dma/s_axis_aclk + +ad_connect rx_device_clk_rstgen/peripheral_aresetn $adc_data_offload_name/m_axis_aresetn +ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/s_axis_aresetn + +# Update the axi_mxfe_rx_dma parameters + +ad_ip_parameter axi_mxfe_rx_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter axi_mxfe_rx_dma CONFIG.AXIS_TUSER_SYNC 0 +ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_LENGTH_WIDTH 30 +ad_ip_parameter axi_mxfe_tx_dma CONFIG.MAX_BYTES_PER_BURST 2048 + ad_connect axi_tdd_0/sync_in tdd_sync +ad_connect axi_tdd_0/tdd_channel_0 axi_mxfe_tx_dma/sync +ad_connect axi_tdd_0/tdd_channel_1 axi_mxfe_rx_dma/sync ad_connect axi_tdd_0/tdd_channel_2 tdd_enabled ad_connect axi_tdd_0/tdd_channel_3 tdd_rx_mxfe_en ad_connect axi_tdd_0/tdd_channel_4 tdd_tx_mxfe_en From e92f8ead1369b1e5028a93ed13169bf63698e2fe Mon Sep 17 00:00:00 2001 From: PopPaul2021 Date: Thu, 3 Jul 2025 09:16:04 +0300 Subject: [PATCH 4/5] docs:ad9081_fmca_ebz_x_band: Documentation updates The block diagram of the HDL design was updated. Notes regarding the system's use-case were added. Signed-off-by: PopPaul2021 --- .../ad9081_x_band_204b_M8L4.svg | 4295 ++++++++++++++++ .../ad9081_x_band_M8L4.svg | 4353 ----------------- .../projects/ad9081_fmca_ebz_x_band/index.rst | 16 +- 3 files changed, 4310 insertions(+), 4354 deletions(-) create mode 100644 docs/projects/ad9081_fmca_ebz_x_band/ad9081_x_band_204b_M8L4.svg delete mode 100644 docs/projects/ad9081_fmca_ebz_x_band/ad9081_x_band_M8L4.svg diff --git a/docs/projects/ad9081_fmca_ebz_x_band/ad9081_x_band_204b_M8L4.svg b/docs/projects/ad9081_fmca_ebz_x_band/ad9081_x_band_204b_M8L4.svg new file mode 100644 index 00000000000..949e32594a0 --- /dev/null +++ b/docs/projects/ad9081_fmca_ebz_x_band/ad9081_x_band_204b_M8L4.svg @@ -0,0 +1,4295 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + RX Global Clock = TX Global Clock = Lane Rate/40 = 250 MHz + + + + tx_data_3_p, n + RX Lane Rate10 Gbps  + + + tx_data_0_p, n + + + + + AXI_ADXCVR + + TX Lane Rate10 Gbps + + + +   + + + + + 128b + + + + JESD PHY + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + GPIO + DDRx + SPI + I2C + Interrupts + Timer + + + + Zynq UltraScale MP + + + + + Receive path + + + + Transmit path + + + Clock domain + + AXI_DMAC + + + + + + AXI_ADXCVR + + + + + + + + AXI_DMAC + + + + + + 128b + + rx_out_clk_0 + rx_sync + rx_0 + + RX JESD TPL + + 250 MHz + + + UTIL_ADXCVR + + 128b@250 MHz + + + + FMC CONNECTOR + + MEMORY INTERCONNECT + + + + rx_data_3_p, n + + + rx_data_0_p, n + + ref_clk_q0 + + + link_clk + VCU118/ZCU102 + + rx_3 + + AD9081-FMCA-EBZ-X-BAND + + + 128b + + + TX JESD LINK + + + 128b + + s_axi_aclk + JESD204B in subclass 1 + + + tx_0 + + tx_3 + + + + + + + + + + + + + tx_out_clk_0 + 250 MHz + + + + tx_sysref + 1 channel x8 samples + + + DATA_OFFLOAD + + + + + RX JESD LINK + + + TX: L=4, M=8, S=1, NP=16 RX: L=4, M=8, S=1, NP=16 + 128b@250 MHz + 4 x 32b@250 MHz + 4 x 32b@250 MHz + + + UTIL_CPACK + + + + 128b + + 128b@250 MHz + 128b@250 MHz + 8 channels x1 sample (16b) + clk + + + + + 16b + + + + 16b + + + rx_sysref + + + tx_sync + QPLL0CPLL_REF_CLK_0-3 + 8 channels x1 sample (16b) + + DATA_OFFLOAD + + UTIL_UPACK + clk + s_axi_aclk + + + + + 128b + + + + + + + 128b + + + + link_clk + TX JESD TPL + 128b@250 MHz + 1 channel x8 samples + + + + + + 16b + + + + + + 16b + + + 128b@250 MHz + 128b@250 MHz + 1 channel x8 samples + + + + + + 128b + + + + device_clk + + + 128b@250 MHz + + + device_clk + link_clk + link_clk + + DMA_CLK = 330MHz + 1 channel x8 samples + + + RxLaneRate = 10Gbps + + AXI_TDD + channel_0 + channel_1 + channel_3 + channel_4 + channel_5 + tdd_rx_mxfe_en + tdd_tx_stingray_en + tdd_tx_mxfe_en + tx_sync + rx_sync + + + + + + + + + HPC1 CONNECTOR + + PMOD0/PMOD1 + AXI_IIC_PMOD + + AXI_SPI_PMOD + + AXI_SPI_FMC + SystemClk=100MHz + + + + + + + + + + + diff --git a/docs/projects/ad9081_fmca_ebz_x_band/ad9081_x_band_M8L4.svg b/docs/projects/ad9081_fmca_ebz_x_band/ad9081_x_band_M8L4.svg deleted file mode 100644 index 4283550791a..00000000000 --- a/docs/projects/ad9081_fmca_ebz_x_band/ad9081_x_band_M8L4.svg +++ /dev/null @@ -1,4353 +0,0 @@ - - - - - Example block design for Single Link; M=4; L=8; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - Example block design for Single Link; M=4; L=8; - - - - - - - - - - - - - - DmaClk=250MHz - - - - - - - - - MEMORY INTERCONNECT - - ZCU102 - - - - HPC0 CONNECTOR - HPC1 CONNECTOR - AXI DMA - - - - UTIL_CPACK - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Receive data path - UTIL_ADC FIFO - - - - - - - - - - - - - Ethernet - UART - DDRx - SPI - GPIO - I2C - Interrupts - MicroBlaze/Zynq - Timer - - - - - - - RX JESD LINK - - RX JESD TPL - - 4x32bits@250MHz - - - 4x10 Gbps - - - - - - - - - - - - - - - 128bits@250MHz - - - - - - - - - - REFCLK0/1 - SYSREF - - - 8 channels x1 samples - 128bits@250MHz - 128bits@250MHz - 128bits@250MHz - 8 x1 samples - - Transmit data path - 128bits@250MHz - - - - - AXI DMA - - - - UTIL_UPACK - UTIL_DAC FIFO - - - - - - - - - - TX JESD LINK - - TX JESD TPL - - XCVR - 4x32bits@250MHz - - - 4x10 Gbps - - - - - - - - - - - - - - - 128bits@250MHz - - - - - - 8 channels x1 samples - 128bits@250MHz - 8 x1 samples - 128bits@250MHz - - L=4; M=8; F=4; S=1 - TxDeviceClock=RxDeviceClock=LaneRate/40=250MHz - TX_DEVICE_CLK - - RX_DEVICE_CLK - - TxLaneRate = 10Gbps - RxLaneRate = 10Gbps - - - AXI_TDD - s_axis_user - channel_0 - channel_1 - channel_3 - channel_4 - channel_5 - sync_ext - sync_ext - tdd_rx_mxfe_en - tdd_tx_stingray_en - tdd_tx_mxfe_en - PMOD0/PMOD1 - AXI_IIC_PMOD - - AXI_SPI_PMOD - - AXI_SPI_FMC - SystemClk=100MHz - - diff --git a/docs/projects/ad9081_fmca_ebz_x_band/index.rst b/docs/projects/ad9081_fmca_ebz_x_band/index.rst index bb70608ae8e..5a72a67b976 100644 --- a/docs/projects/ad9081_fmca_ebz_x_band/index.rst +++ b/docs/projects/ad9081_fmca_ebz_x_band/index.rst @@ -31,6 +31,20 @@ The system is designed to mate with a :xilinx:`ZCU102` Evaluation Board from Xilinx®, which features the Zynq® UltraScale+™ MPSoC FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing software. +.. important:: + + The current implementation is tailored for CW (Continuous Waveform) mode, + where the TDD frame rate matches the transmitted buffer length. + + For this to work,the following criteria must be met: + + - The RX/TX DMAs must handle the CDC (Clock Domain Crossing) between the + 330 MHz clock on the memory side and the 250MHz clock on the JESD side. + - The clock frequency on the memory interconnect side of the DMAs + must be configured to 330MHz. + - The DMAs' coherent mode must be disabled. + - The data offload IPs must be configured in bypass mode. + Supported boards ------------------------------------------------------------------------------- @@ -68,7 +82,7 @@ Block diagram Example block design for Single link; M=8; L=4 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -.. image:: ad9081_x_band_M8L4.svg +.. image:: ad9081_x_band_204b_M8L4.svg :width: 800 :align: center :alt: AD9081-FMCA-EBZ JESD204B M=8 L=4 block diagram From 235776f4258ab4a79ca468c24b4bc743a8886932 Mon Sep 17 00:00:00 2001 From: PopPaul2021 Date: Wed, 9 Jul 2025 09:22:57 +0300 Subject: [PATCH 5/5] library:data_offload: Fix Critical Warning The false path has to be set only when in async_clk mode. Signed-off-by: PopPaul2021 --- library/data_offload/data_offload_constr.ttcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/library/data_offload/data_offload_constr.ttcl b/library/data_offload/data_offload_constr.ttcl index 23790f23eb7..dd19ba58e5e 100644 --- a/library/data_offload/data_offload_constr.ttcl +++ b/library/data_offload/data_offload_constr.ttcl @@ -12,6 +12,7 @@ <: set tx_enable [getBooleanValue "TX_OR_RXN_PATH"] :> <: set internal_cdc [getBooleanValue "SYNC_EXT_ADD_INTERNAL_CDC"] :> <: set has_bypass [getBooleanValue "HAS_BYPASS"] :> +<: set async_clk [getBooleanValue "ASYNC_CLK"] :> ## for all synchronization registers from util_cdc modules set_property ASYNC_REG TRUE \ @@ -148,7 +149,7 @@ set_max_delay -quiet -datapath_only \ [get_property -min PERIOD $dest_clk] ## Constraints for the bypass module -<: if { $has_bypass } { :> +<: if { $has_bypass && $async_clk } { :> set_false_path \ -to [get_pins -hierarchical * -filter {NAME=~*i_waddr_sync_gray/cdc_sync_stage1_reg[*]/D}]