From b577677ec5b0f66e10308042349e98edc4a530ac Mon Sep 17 00:00:00 2001 From: sarpadi Date: Thu, 26 Jun 2025 15:40:26 +0300 Subject: [PATCH 1/3] ad9081_fmca_ebz: Remove vcu128 support Signed-off-by: sarpadi --- projects/ad9081_fmca_ebz/vcu128/Makefile | 42 -- projects/ad9081_fmca_ebz/vcu128/README.md | 79 ---- projects/ad9081_fmca_ebz/vcu128/system_bd.tcl | 158 -------- .../ad9081_fmca_ebz/vcu128/system_constr.xdc | 93 ----- .../ad9081_fmca_ebz/vcu128/system_project.tcl | 74 ---- projects/ad9081_fmca_ebz/vcu128/system_top.v | 372 ------------------ .../ad9081_fmca_ebz/vcu128/timing_constr.xdc | 67 ---- 7 files changed, 885 deletions(-) delete mode 100644 projects/ad9081_fmca_ebz/vcu128/Makefile delete mode 100644 projects/ad9081_fmca_ebz/vcu128/README.md delete mode 100644 projects/ad9081_fmca_ebz/vcu128/system_bd.tcl delete mode 100644 projects/ad9081_fmca_ebz/vcu128/system_constr.xdc delete mode 100644 projects/ad9081_fmca_ebz/vcu128/system_project.tcl delete mode 100644 projects/ad9081_fmca_ebz/vcu128/system_top.v delete mode 100644 projects/ad9081_fmca_ebz/vcu128/timing_constr.xdc diff --git a/projects/ad9081_fmca_ebz/vcu128/Makefile b/projects/ad9081_fmca_ebz/vcu128/Makefile deleted file mode 100644 index 48976cdf647..00000000000 --- a/projects/ad9081_fmca_ebz/vcu128/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := ad9081_fmca_ebz_vcu128 - -M_DEPS += timing_constr.xdc -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/xilinx/data_offload_bd.tcl -M_DEPS += ../../common/vcu128/vcu128_system_constr.xdc -M_DEPS += ../../common/vcu128/vcu128_system_bd.tcl -M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl -M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl -M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl -M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/common/ad_3w_spi.v -M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += axi_tdd -LIB_DEPS += data_offload -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac -LIB_DEPS += jesd204/axi_jesd204_rx -LIB_DEPS += jesd204/axi_jesd204_tx -LIB_DEPS += jesd204/jesd204_rx -LIB_DEPS += jesd204/jesd204_tx -LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx -LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx -LIB_DEPS += sysid_rom -LIB_DEPS += util_do_ram -LIB_DEPS += util_hbm -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += util_pack/util_upack2 -LIB_DEPS += xilinx/axi_adxcvr -LIB_DEPS += xilinx/util_adxcvr - -include ../../scripts/project-xilinx.mk diff --git a/projects/ad9081_fmca_ebz/vcu128/README.md b/projects/ad9081_fmca_ebz/vcu128/README.md deleted file mode 100644 index 55525b70d46..00000000000 --- a/projects/ad9081_fmca_ebz/vcu128/README.md +++ /dev/null @@ -1,79 +0,0 @@ -# AD9081-FMCA-EBZ/VCU128 HDL Project - -## Building the project - -The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration. - -:warning: **When changing the default configuration, the timing_constr.xdc constraints should be updated as well!** - -``` -cd projects/ad9081_fmca_ebz/vcu128 -make -``` - -All of the RX/TX link modes can be found in the [AD9081 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf). We offer support for only a few of them. - -The overwritable parameters from the environment are: - -- JESD_MODE: link layer encoder mode used; - - 8B10B - 8b10b link layer defined in JESD204B - - 64B66B - 64b66b link layer defined in JESD204C -- [RX/TX]_LANE_RATE: lane rate of the [RX/TX] link (RX: MxFE to FPGA/TX: FPGA to MxFE) -- [RX/TX]_JESD_M: [RX/TX] number of converters per link -- [RX/TX]_JESD_L: [RX/TX] number of lanes per link -- [RX/TX]_JESD_S: [RX/TX] number of samples per converter per frame -- [RX/TX]_JESD_NP: [RX/TX] number of bits per sample, only 16 is supported -- [RX/TX]_NUM_LINKS:- [RX/TX] number of links, which matches the number of MxFE devices -- [RX/TX]_KS_PER_CHANNEL: [RX/TX] number of samples stored in internal buffers in kilosamples per converter (M), for each channel in a block RAM, for a contiguous capture -- [ADC/DAC]_DO_MEM_TYPE: [ADC/DAC] Data Offload memory type; - - 0 - internal storage instance (BRAMs) - - 1 - bridge instance for the external **DDR** memory controller - - 2 - bridge instance for the external **HBM** memory controller - -### Example configurations - -#### JESD204B subclass 1, TX mode 9, RX mode 10 (default) - -This specific command is equivalent to running `make` only: - -``` -make JESD_MODE=8B10B \ -RX_LANE_RATE=10 \ -TX_LANE_RATE=10 \ -RX_JESD_M=8 \ -RX_JESD_L=4 \ -RX_JESD_S=1 \ -RX_JESD_NP=16 \ -RX_NUM_LINKS=1 \ -TX_JESD_M=8 \ -TX_JESD_L=4 \ -TX_JESD_S=1 \ -TX_JESD_NP=16 \ -TX_NUM_LINKS=1 \ -RX_KS_PER_CHANNEL=16384 \ -TX_KS_PER_CHANNEL=16384 \ -ADC_DO_MEM_TYPE=2 \ -DAC_DO_MEM_TYPE=2 -``` - -Corresponding device tree: [vcu128_ad9081_m8_l4.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vcu128_ad9081_m8_l4.dts) - -#### JESD204B subclass 1, TX mode 17, RX mode 18 - -``` -make JESD_MODE=8B10B \ -RX_LANE_RATE=15 \ -TX_LANE_RATE=15 \ -RX_JESD_M=4 \ -RX_JESD_L=8 \ -RX_JESD_S=1 \ -RX_JESD_NP=16 \ -RX_NUM_LINKS=1 \ -TX_JESD_M=4 \ -TX_JESD_L=8 \ -TX_JESD_S=1 \ -TX_JESD_NP=16 \ -TX_NUM_LINKS=1 -``` - -Corresponding device tree: [vcu128_ad9081.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vcu128_ad9081.dts) diff --git a/projects/ad9081_fmca_ebz/vcu128/system_bd.tcl b/projects/ad9081_fmca_ebz/vcu128/system_bd.tcl deleted file mode 100644 index 8c3e2db8a41..00000000000 --- a/projects/ad9081_fmca_ebz/vcu128/system_bd.tcl +++ /dev/null @@ -1,158 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -## ADC FIFO depth in samples per converter -set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] -## DAC FIFO depth in samples per converter -set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] - -source $ad_hdl_dir/library/util_hbm/scripts/adi_util_hbm.tcl -ad_create_hbm HBM - -source $ad_hdl_dir/projects/common/vcu128/vcu128_system_bd.tcl -source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -if {$INTF_CFG != "TX"} { - ad_connect_hbm HBM mxfe_rx_data_offload/storage_unit $sys_hbm_clk $sys_hbm_resetn 0 - ad_ip_parameter $adc_data_offload_name/i_data_offload CONFIG.HAS_BYPASS false - ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2 -} - -if {$INTF_CFG != "RX"} { - ad_connect_hbm HBM mxfe_tx_data_offload/storage_unit $sys_hbm_clk $sys_hbm_resetn 4 - ad_ip_parameter $dac_data_offload_name/i_data_offload CONFIG.HAS_BYPASS false - ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 -} - -ad_connect HBM/HBM_REF_CLK_0 $sys_cpu_clk -ad_connect HBM/APB_0_PCLK $sys_cpu_clk -ad_connect HBM/APB_0_PRESET_N $sys_cpu_resetn - -#system ID -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 10 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 10 - -set sys_cstring "$ad_project_params(JESD_MODE)\ -RX:RATE=$ad_project_params(RX_LANE_RATE)\ -M=$ad_project_params(RX_JESD_M)\ -L=$ad_project_params(RX_JESD_L)\ -S=$ad_project_params(RX_JESD_S)\ -NP=$ad_project_params(RX_JESD_NP)\ -LINKS=$ad_project_params(RX_NUM_LINKS)\ -KS/CH=$ad_project_params(RX_KS_PER_CHANNEL)\ -TX:RATE=$ad_project_params(TX_LANE_RATE)\ -M=$ad_project_params(TX_JESD_M)\ -L=$ad_project_params(TX_JESD_L)\ -S=$ad_project_params(TX_JESD_S)\ -NP=$ad_project_params(TX_JESD_NP)\ -LINKS=$ad_project_params(TX_NUM_LINKS)\ -KS/CH=$ad_project_params(TX_KS_PER_CHANNEL)\ -ADC_DO_MEM_TYPE:$ad_project_params(ADC_DO_MEM_TYPE)\ -DAC_DO_MEM_TYPE:$ad_project_params(DAC_DO_MEM_TYPE)" - -sysid_gen_sys_init_file $sys_cstring 10 - -# Parameters for 15.5Gpbs lane rate - -ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31 -ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31 -ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa -ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x2b -ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2 -ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2 -ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x4040 -ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1 -ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 -ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3002 -ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2 0x1E9 -ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x23 -ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x23 -ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x23 -ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x23 -ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x1 -ad_ip_parameter util_mxfe_xcvr CONFIG.RX_XMODE_SEL 0x0 -ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1 -ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00 -ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00 -ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00 -ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3100 -ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0 -ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 1 -ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x54 - -ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1 -ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c -ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x2 -ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20 -ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xB00 -ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2ff - -# 204C params 16.5Gbps..24.75Gpbs -if {$ad_project_params(JESD_MODE) == "64B66B"} { - - # Set higher swing for the diff driver, other case 16.5Gbps won't work - ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.TX_DIFFCTRL 0xC - - # Lane rate indepentent parameters - ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12 - ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12 - ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 - ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0 - ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x2 - ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6060 - ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 2 - ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 2 - ad_ip_parameter util_mxfe_xcvr CONFIG.RXDFE_KH_CFG2 0x281C - ad_ip_parameter util_mxfe_xcvr CONFIG.RXDFE_KH_CFG3 0x4120 - - # Lane rate indepentent QPLL parameters - ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0x600 - ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x331c - - # Lane rate dependent QPLL params (these match for 16.5 Gbps and 24.75 Gpbs) - ad_ip_parameter util_mxfe_xcvr CONFIG.PPF1_CFG 0x400 - ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x33f - ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG2 0x0FC1 - ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG2_G3 0x0FC1 - ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x03 - - # set dividers for 24.75Gbps, are overwritten by software - ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 10 - ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 10 - ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 66 - ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 2 - - if {$ad_project_params(RX_LANE_RATE) < 20} { - ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 - ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x0104 - } else { - ad_ip_parameter util_mxfe_xcvr CONFIG.RTX_BUF_CML_CTRL 0x6 - ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x3004 - } - - if {$ad_project_params(TX_LANE_RATE) < 20} { - ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 1 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG0 0x3C2 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xAA00 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xAA00 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xAA00 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x0100 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x1000 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXSWBST_EN 0 - } else { - ad_ip_parameter util_mxfe_xcvr CONFIG.TXDRV_FREQBAND 3 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG0 0x3C6 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG1 0xF800 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG2 0xF800 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXFE_CFG3 0xF800 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG0 0x3000 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG1 0x0 - ad_ip_parameter util_mxfe_xcvr CONFIG.TXSWBST_EN 1 - } - -} - diff --git a/projects/ad9081_fmca_ebz/vcu128/system_constr.xdc b/projects/ad9081_fmca_ebz/vcu128/system_constr.xdc deleted file mode 100644 index a35a90cf258..00000000000 --- a/projects/ad9081_fmca_ebz/vcu128/system_constr.xdc +++ /dev/null @@ -1,93 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# -## mxfe -# - -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## IO_L13P_T2L_N0_GC_QBC_71 -set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## IO_L13N_T2L_N1_GC_QBC_71 -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## IO_L14P_T2L_N2_GC_71 -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## IO_L14N_T2L_N3_GC_71 -set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## IO_L22P_T3U_N6_DBC_AD0P_71 -set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## IO_L22N_T3U_N7_DBC_AD0N_71 -set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## IO_L23P_T3U_N8_71 -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L23N_T3U_N9_71 -set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS } [get_ports clkin6_n ] ; ## IO_L11N_T1U_N9_GC_71 -set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVDS } [get_ports clkin6_p ] ; ## IO_L11P_T1U_N8_GC_71 -set_property -dict {PACKAGE_PIN AR41 } [get_ports clkin8_n ] ; ## MGTREFCLK0N_125 -set_property -dict {PACKAGE_PIN AR40 } [get_ports clkin8_p ] ; ## MGTREFCLK0P_125 -set_property -dict {PACKAGE_PIN AV43 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_124 -set_property -dict {PACKAGE_PIN AV42 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_124 -set_property -quiet -dict {PACKAGE_PIN BA54 } [get_ports rx_data_n[2] ] ; ## MGTYRXN2_124 FPGA_SERDIN_0_N -set_property -quiet -dict {PACKAGE_PIN BA53 } [get_ports rx_data_p[2] ] ; ## MGTYRXP2_124 FPGA_SERDIN_0_P -set_property -quiet -dict {PACKAGE_PIN BC54 } [get_ports rx_data_n[0] ] ; ## MGTYRXN0_124 FPGA_SERDIN_1_N -set_property -quiet -dict {PACKAGE_PIN BC53 } [get_ports rx_data_p[0] ] ; ## MGTYRXP0_124 FPGA_SERDIN_1_P -set_property -quiet -dict {PACKAGE_PIN AV52 } [get_ports rx_data_n[7] ] ; ## MGTYRXN3_125 FPGA_SERDIN_2_N -set_property -quiet -dict {PACKAGE_PIN AV51 } [get_ports rx_data_p[7] ] ; ## MGTYRXP3_125 FPGA_SERDIN_2_P -set_property -quiet -dict {PACKAGE_PIN AW50 } [get_ports rx_data_n[6] ] ; ## MGTYRXN2_125 FPGA_SERDIN_3_N -set_property -quiet -dict {PACKAGE_PIN AW49 } [get_ports rx_data_p[6] ] ; ## MGTYRXP2_125 FPGA_SERDIN_3_P -set_property -quiet -dict {PACKAGE_PIN AW54 } [get_ports rx_data_n[5] ] ; ## MGTYRXN1_125 FPGA_SERDIN_4_N -set_property -quiet -dict {PACKAGE_PIN AW53 } [get_ports rx_data_p[5] ] ; ## MGTYRXP1_125 FPGA_SERDIN_4_P -set_property -quiet -dict {PACKAGE_PIN AY52 } [get_ports rx_data_n[4] ] ; ## MGTYRXN0_125 FPGA_SERDIN_5_N -set_property -quiet -dict {PACKAGE_PIN AY51 } [get_ports rx_data_p[4] ] ; ## MGTYRXP0_125 FPGA_SERDIN_5_P -set_property -quiet -dict {PACKAGE_PIN BA50 } [get_ports rx_data_n[3] ] ; ## MGTYRXN3_124 FPGA_SERDIN_6_N -set_property -quiet -dict {PACKAGE_PIN BA49 } [get_ports rx_data_p[3] ] ; ## MGTYRXP3_124 FPGA_SERDIN_6_P -set_property -quiet -dict {PACKAGE_PIN BB52 } [get_ports rx_data_n[1] ] ; ## MGTYRXN1_124 FPGA_SERDIN_7_N -set_property -quiet -dict {PACKAGE_PIN BB51 } [get_ports rx_data_p[1] ] ; ## MGTYRXP1_124 FPGA_SERDIN_7_P -set_property -quiet -dict {PACKAGE_PIN BC49 } [get_ports tx_data_n[0] ] ; ## MGTYTXN0_124 FPGA_SERDOUT_0_N -set_property -quiet -dict {PACKAGE_PIN BC48 } [get_ports tx_data_p[0] ] ; ## MGTYTXP0_124 FPGA_SERDOUT_0_P -set_property -quiet -dict {PACKAGE_PIN BB47 } [get_ports tx_data_n[2] ] ; ## MGTYTXN2_124 FPGA_SERDOUT_1_N -set_property -quiet -dict {PACKAGE_PIN BB46 } [get_ports tx_data_p[2] ] ; ## MGTYTXP2_124 FPGA_SERDOUT_1_P -set_property -quiet -dict {PACKAGE_PIN AU45 } [get_ports tx_data_n[7] ] ; ## MGTYTXN3_125 FPGA_SERDOUT_2_N -set_property -quiet -dict {PACKAGE_PIN AU44 } [get_ports tx_data_p[7] ] ; ## MGTYTXP3_125 FPGA_SERDOUT_2_P -set_property -quiet -dict {PACKAGE_PIN AV47 } [get_ports tx_data_n[6] ] ; ## MGTYTXN2_125 FPGA_SERDOUT_3_N -set_property -quiet -dict {PACKAGE_PIN AV46 } [get_ports tx_data_p[6] ] ; ## MGTYTXP2_125 FPGA_SERDOUT_3_P -set_property -quiet -dict {PACKAGE_PIN BC45 } [get_ports tx_data_n[1] ] ; ## MGTYTXN1_124 FPGA_SERDOUT_4_N -set_property -quiet -dict {PACKAGE_PIN BC44 } [get_ports tx_data_p[1] ] ; ## MGTYTXP1_124 FPGA_SERDOUT_4_P -set_property -quiet -dict {PACKAGE_PIN AW45 } [get_ports tx_data_n[5] ] ; ## MGTYTXN1_125 FPGA_SERDOUT_5_N -set_property -quiet -dict {PACKAGE_PIN AW44 } [get_ports tx_data_p[5] ] ; ## MGTYTXP1_125 FPGA_SERDOUT_5_P -set_property -quiet -dict {PACKAGE_PIN AY47 } [get_ports tx_data_n[4] ] ; ## MGTYTXN0_125 FPGA_SERDOUT_6_N -set_property -quiet -dict {PACKAGE_PIN AY46 } [get_ports tx_data_p[4] ] ; ## MGTYTXP0_125 FPGA_SERDOUT_6_P -set_property -quiet -dict {PACKAGE_PIN BA45 } [get_ports tx_data_n[3] ] ; ## MGTYTXN3_124 FPGA_SERDOUT_7_N -set_property -quiet -dict {PACKAGE_PIN BA44 } [get_ports tx_data_p[3] ] ; ## MGTYTXP3_124 FPGA_SERDOUT_7_P -set_property -quiet -dict {PACKAGE_PIN K22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_0_n ] ; ## IO_L4N_T0U_N7_DBC_AD7N_72 -set_property -quiet -dict {PACKAGE_PIN L23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_0_p ] ; ## IO_L4P_T0U_N6_DBC_AD7P_72 -set_property -quiet -dict {PACKAGE_PIN A26 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_n ] ; ## IO_L23N_T3U_N9_72 -set_property -quiet -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18 } [get_ports fpga_syncin_1_p ] ; ## IO_L23P_T3U_N8_72 -set_property -quiet -dict {PACKAGE_PIN F25 IOSTANDARD LVDS } [get_ports fpga_syncout_0_n ] ; ## IO_L14N_T2L_N3_GC_72 -set_property -quiet -dict {PACKAGE_PIN F26 IOSTANDARD LVDS } [get_ports fpga_syncout_0_p ] ; ## IO_L14P_T2L_N2_GC_72 -set_property -quiet -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_n ] ; ## IO_L15N_T2L_N5_AD11N_72 -set_property -quiet -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS18 } [get_ports fpga_syncout_1_p ] ; ## IO_L15P_T2L_N4_AD11P_72 -set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## IO_L6P_T0U_N10_AD6P_72 -set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## IO_L6N_T0U_N11_AD6N_72 -set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## IO_L21P_T3L_N4_AD8P_71 -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## IO_L21N_T3L_N5_AD8N_71 -set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## IO_L24P_T3U_N10_72 -set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## IO_L24N_T3U_N11_72 -set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_72 -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_72 -set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## IO_L3P_T0L_N4_AD15P_72 -set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## IO_L3N_T0L_N5_AD15N_72 -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## IO_L24N_T3U_N11_71 -set_property -dict {PACKAGE_PIN B25 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## IO_L21N_T3L_N5_AD8N_72 -set_property -dict {PACKAGE_PIN J27 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## IO_L5N_T0U_N9_AD14N_72 -set_property -dict {PACKAGE_PIN E27 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## IO_L18P_T2U_N10_AD2P_72 -set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## IO_L18N_T2U_N11_AD2N_72 -set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## IO_L5P_T0U_N8_AD14P_72 -set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## IO_L22P_T3U_N6_DBC_AD0P_72 -set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## IO_L22N_T3U_N7_DBC_AD0N_72 -set_property -dict {PACKAGE_PIN H27 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## IO_L9P_T1L_N4_AD12P_72 -set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## IO_L9N_T1L_N5_AD12N_72 -set_property -dict {PACKAGE_PIN C25 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## IO_L20P_T3L_N2_AD1P_72 -set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## IO_L20N_T3L_N3_AD1N_72 -set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## IO_L8P_T1L_N2_AD5P_72 -set_property -dict {PACKAGE_PIN B26 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## IO_L21P_T3L_N4_AD8P_72 -set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## IO_L8N_T1L_N3_AD5N_72 -set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_n ] ; ## IO_L11N_T1U_N9_GC_72 -set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_p ] ; ## IO_L11P_T1U_N8_GC_72 -set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L17P_T2U_N8_AD10P_72 -set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L17N_T2U_N9_AD10N_72 - diff --git a/projects/ad9081_fmca_ebz/vcu128/system_project.tcl b/projects/ad9081_fmca_ebz/vcu128/system_project.tcl deleted file mode 100644 index aa5f1925990..00000000000 --- a/projects/ad9081_fmca_ebz/vcu128/system_project.tcl +++ /dev/null @@ -1,74 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -# get_env_param retrieves parameter value from the environment if exists, -# other case use the default value -# -# Use over-writable parameters from the environment. -# -# e.g. -# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_LANE_RATE=16.22016 TX_LANE_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4 -# make JESD_MODE=64B66B RX_LANE_RATE=16.50 TX_LANE_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16 -# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 -# make JESD_MODE=64B66B RX_LANE_RATE=16.50 TX_LANE_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 -# make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8 - -# -# Parameter description: -# JESD_MODE : Used link layer encoder mode -# 64B66B - 64b66b link layer defined in JESD 204C -# 8B10B - 8b10b link layer defined in JESD 204B -# -# RX_LANE_RATE : Lane rate of the Rx link ( MxFE to FPGA ) -# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to MxFE ) -# [RX/TX]_JESD_M : Number of converters per link -# [RX/TX]_JESD_L : Number of lanes per link -# [RX/TX]_JESD_S : Number of samples per frame -# [RX/TX]_JESD_NP : Number of bits per sample -# [RX/TX]_NUM_LINKS : Number of links -# [RX/TX]_KS_PER_CHANNEL : Number of samples stored in internal buffers in kilosamples per converter (M) -# - -adi_project ad9081_fmca_ebz_vcu128 0 [list \ - JESD_MODE [get_env_param JESD_MODE 8B10B ] \ - RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ - TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ - RX_JESD_M [get_env_param RX_JESD_M 8 ] \ - RX_JESD_L [get_env_param RX_JESD_L 4 ] \ - RX_JESD_S [get_env_param RX_JESD_S 1 ] \ - RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ - RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ - TX_JESD_M [get_env_param TX_JESD_M 8 ] \ - TX_JESD_L [get_env_param TX_JESD_L 4 ] \ - TX_JESD_S [get_env_param TX_JESD_S 1 ] \ - TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ - TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ - RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 16384 ] \ - TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 16384 ] \ - ADC_DO_MEM_TYPE [get_env_param ADC_DO_MEM_TYPE 2 ] \ - DAC_DO_MEM_TYPE [get_env_param DAC_DO_MEM_TYPE 2 ] \ -] - -adi_project_files ad9081_fmca_ebz_vcu128 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "timing_constr.xdc"\ - "../../../library/common/ad_3w_spi.v"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/vcu128/vcu128_system_constr.xdc" ] - -# Avoid critical warning in OOC mode from the clock definitions -# since at that stage the submodules are not stiched together yet -if {$ADI_USE_OOC_SYNTHESIS == 1} { - set_property used_in_synthesis false [get_files timing_constr.xdc] -} - -adi_project_run ad9081_fmca_ebz_vcu128 - diff --git a/projects/ad9081_fmca_ebz/vcu128/system_top.v b/projects/ad9081_fmca_ebz/vcu128/system_top.v deleted file mode 100644 index 75ad7b65a06..00000000000 --- a/projects/ad9081_fmca_ebz/vcu128/system_top.v +++ /dev/null @@ -1,372 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top #( - parameter TX_JESD_L = 8, - parameter TX_NUM_LINKS = 1, - parameter RX_JESD_L = 8, - parameter RX_NUM_LINKS = 1, - parameter JESD_MODE = "8B10B" -) ( - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - input uart_sin, - output uart_sout, - - output ddr4_act_n, - output [16:0] ddr4_addr, - output [ 1:0] ddr4_ba, - output [ 0:0] ddr4_bg, - output ddr4_ck_p, - output ddr4_ck_n, - output [ 0:0] ddr4_cke, - output [ 1:0] ddr4_cs_n, - inout [ 8:0] ddr4_dm_n, - inout [71:0] ddr4_dq, - inout [ 8:0] ddr4_dqs_p, - inout [ 8:0] ddr4_dqs_n, - output [ 0:0] ddr4_odt, - output ddr4_reset_n, - - output mdio_mdc, - inout mdio_mdio, - input phy_clk_p, - input phy_clk_n, - input phy_rx_p, - input phy_rx_n, - output phy_tx_p, - output phy_tx_n, - input phy_dummy_port_in, - - inout [7:0] gpio_bd, - - inout iic_scl, - inout iic_sda, - - input vadj_1v8_pgood, - - // FMC HPC IOs - input [1:0] agc0, - input [1:0] agc1, - input [1:0] agc2, - input [1:0] agc3, - input clkin8_n, - input clkin8_p, - input clkin6_n, - input clkin6_p, - input fpga_refclk_in_n, - input fpga_refclk_in_p, - input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, - input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, - output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, - output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, - input fpga_syncin_0_n, - input fpga_syncin_0_p, - inout fpga_syncin_1_n, - inout fpga_syncin_1_p, - output fpga_syncout_0_n, - output fpga_syncout_0_p, - inout fpga_syncout_1_n, - inout fpga_syncout_1_p, - inout [10:0] gpio, - inout hmc_gpio1, - output hmc_sync, - input [1:0] irqb, - output rstb, - output [1:0] rxen, - output spi0_csb, - input spi0_miso, - output spi0_mosi, - output spi0_sclk, - output spi1_csb, - output spi1_sclk, - inout spi1_sdio, - input sysref2_n, - input sysref2_p, - output [1:0] txen -); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 7:0] spi_csn; - wire spi_mosi; - wire spi_miso; - wire spi1_miso; - - wire ref_clk; - wire sysref; - wire [TX_NUM_LINKS-1:0] tx_syncin; - wire [RX_NUM_LINKS-1:0] rx_syncout; - - wire [7:0] tx_data_p_loc; - wire [7:0] tx_data_n_loc; - - wire clkin6; - wire clkin8; - wire tx_device_clk; - wire rx_device_clk; - - // instantiations - - IBUFDS_GTE4 i_ibufds_ref_clk ( - .CEB (1'd0), - .I (fpga_refclk_in_p), - .IB (fpga_refclk_in_n), - .O (ref_clk), - .ODIV2 ()); - - IBUFDS i_ibufds_sysref ( - .I (sysref2_p), - .IB (sysref2_n), - .O (sysref)); - - IBUFDS i_ibufds_device_clk ( - .I (clkin6_p), - .IB (clkin6_n), - .O (clkin6)); - - IBUFDS_GTE4 i_ibufds_rx_device_clk ( - .I (clkin8_p), - .IB (clkin8_n), - .CEB(1'b0), - .ODIV2 (clkin8)); - - IBUFDS i_ibufds_syncin_0 ( - .I (fpga_syncin_0_p), - .IB (fpga_syncin_0_n), - .O (tx_syncin[0])); - - OBUFDS i_obufds_syncout_0 ( - .I (rx_syncout[0]), - .O (fpga_syncout_0_p), - .OB (fpga_syncout_0_n)); - - BUFG i_tx_device_clk ( - .I (clkin6), - .O (tx_device_clk)); - - BUFG_GT i_rx_device_clk ( - .I (clkin8), - .O (rx_device_clk)); - - // spi - - assign spi0_csb = spi_csn[0]; - assign spi0_mosi = spi_mosi; - assign spi0_sclk = spi_clk; - - assign spi1_csb = spi_csn[1]; - assign spi1_sclk = spi_clk; - - assign spi_miso = ~spi_csn[0] ? spi0_miso : - ~spi_csn[1] ? spi1_miso : 1'b0; - - ad_3w_spi #( - .NUM_OF_SLAVES(1) - ) i_spi ( - .spi_csn (spi_csn[1]), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi), - .spi_miso (spi1_miso), - .spi_sdio (spi1_sdio), - .spi_dir ()); - - // gpios - - ad_iobuf #( - .DATA_WIDTH(12) - ) i_iobuf ( - .dio_t (gpio_t[43:32]), - .dio_i (gpio_o[43:32]), - .dio_o (gpio_i[43:32]), - .dio_p ({hmc_gpio1, // 43 - gpio[10:0]})); // 42-32 - - assign gpio_i[44] = agc0[0]; - assign gpio_i[45] = agc0[1]; - assign gpio_i[46] = agc1[0]; - assign gpio_i[47] = agc1[1]; - assign gpio_i[48] = agc2[0]; - assign gpio_i[49] = agc2[1]; - assign gpio_i[50] = agc3[0]; - assign gpio_i[51] = agc3[1]; - assign gpio_i[52] = irqb[0]; - assign gpio_i[53] = irqb[1]; - - assign hmc_sync = gpio_o[54]; - assign rstb = gpio_o[55]; - assign rxen[0] = gpio_o[56]; - assign rxen[1] = gpio_o[57]; - assign txen[0] = gpio_o[58]; - assign txen[1] = gpio_o[59]; - - generate - if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin - assign tx_syncin[1] = fpga_syncin_1_p; - end else begin - ad_iobuf #( - .DATA_WIDTH(2) - ) i_syncin_iobuf ( - .dio_t (gpio_t[61:60]), - .dio_i (gpio_o[61:60]), - .dio_o (gpio_i[61:60]), - .dio_p ({fpga_syncin_1_n, // 61 - fpga_syncin_1_p})); // 60 - end - - if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin - assign fpga_syncout_1_p = rx_syncout[1]; - assign fpga_syncout_1_n = 0; - end else begin - ad_iobuf #( - .DATA_WIDTH(2) - ) i_syncout_iobuf ( - .dio_t (gpio_t[63:62]), - .dio_i (gpio_o[63:62]), - .dio_o (gpio_i[63:62]), - .dio_p ({fpga_syncout_1_n, // 63 - fpga_syncout_1_p})); // 62 - end - endgenerate - - ad_iobuf #( - .DATA_WIDTH(8) - ) i_iobuf_bd ( - .dio_t (gpio_t[7:0]), - .dio_i (gpio_o[7:0]), - .dio_o (gpio_i[7:0]), - .dio_p (gpio_bd)); - - assign gpio_i[59:54] = gpio_o[59:54]; - assign gpio_i[31:8] = gpio_o[31:8]; - - system_wrapper i_system_wrapper ( - .sys_rst (sys_rst), - .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p), - .ddr4_act_n (ddr4_act_n), - .ddr4_adr (ddr4_addr), - .ddr4_ba (ddr4_ba), - .ddr4_bg (ddr4_bg), - .ddr4_ck_c (ddr4_ck_n), - .ddr4_ck_t (ddr4_ck_p), - .ddr4_cke (ddr4_cke), - .ddr4_cs_n (ddr4_cs_n), - .ddr4_dm_n (ddr4_dm_n), - .ddr4_dq (ddr4_dq), - .ddr4_dqs_c (ddr4_dqs_n), - .ddr4_dqs_t (ddr4_dqs_p), - .ddr4_odt (ddr4_odt), - .ddr4_reset_n (ddr4_reset_n), - .phy_sd (1'b1), - .phy_dummy_port_in (phy_dummy_port_in), - .sgmii_rxn (phy_rx_n), - .sgmii_rxp (phy_rx_p), - .sgmii_txn (phy_tx_n), - .sgmii_txp (phy_tx_p), - .mdio_mdc (mdio_mdc), - .mdio_mdio_io (mdio_mdio), - .sgmii_phyclk_clk_n (phy_clk_n), - .sgmii_phyclk_clk_p (phy_clk_p), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .uart_sin (uart_sin), - .uart_sout (uart_sout), - .spi_clk_i (spi_clk), - .spi_clk_o (spi_clk), - .spi_csn_i (spi_csn), - .spi_csn_o (spi_csn), - .spi_sdi_i (spi_miso), - .spi_sdo_i (spi_mosi), - .spi_sdo_o (spi_mosi), - .gpio0_i (gpio_i[31:0]), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio1_i (gpio_i[63:32]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - // FMC HPC - .rx_data_0_n (rx_data_n[0]), - .rx_data_0_p (rx_data_p[0]), - .rx_data_1_n (rx_data_n[1]), - .rx_data_1_p (rx_data_p[1]), - .rx_data_2_n (rx_data_n[2]), - .rx_data_2_p (rx_data_p[2]), - .rx_data_3_n (rx_data_n[3]), - .rx_data_3_p (rx_data_p[3]), - .rx_data_4_n (rx_data_n[4]), - .rx_data_4_p (rx_data_p[4]), - .rx_data_5_n (rx_data_n[5]), - .rx_data_5_p (rx_data_p[5]), - .rx_data_6_n (rx_data_n[6]), - .rx_data_6_p (rx_data_p[6]), - .rx_data_7_n (rx_data_n[7]), - .rx_data_7_p (rx_data_p[7]), - .tx_data_0_n (tx_data_n_loc[0]), - .tx_data_0_p (tx_data_p_loc[0]), - .tx_data_1_n (tx_data_n_loc[1]), - .tx_data_1_p (tx_data_p_loc[1]), - .tx_data_2_n (tx_data_n_loc[2]), - .tx_data_2_p (tx_data_p_loc[2]), - .tx_data_3_n (tx_data_n_loc[3]), - .tx_data_3_p (tx_data_p_loc[3]), - .tx_data_4_n (tx_data_n_loc[4]), - .tx_data_4_p (tx_data_p_loc[4]), - .tx_data_5_n (tx_data_n_loc[5]), - .tx_data_5_p (tx_data_p_loc[5]), - .tx_data_6_n (tx_data_n_loc[6]), - .tx_data_6_p (tx_data_p_loc[6]), - .tx_data_7_n (tx_data_n_loc[7]), - .tx_data_7_p (tx_data_p_loc[7]), - .ref_clk_q0 (ref_clk), - .ref_clk_q1 (ref_clk), - .rx_device_clk (rx_device_clk), - .tx_device_clk (tx_device_clk), - .rx_sync_0 (rx_syncout), - .tx_sync_0 (tx_syncin), - .rx_sysref_0 (sysref), - .tx_sysref_0 (sysref)); - - assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; - assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; - -endmodule diff --git a/projects/ad9081_fmca_ebz/vcu128/timing_constr.xdc b/projects/ad9081_fmca_ebz/vcu128/timing_constr.xdc deleted file mode 100644 index 7554f73752d..00000000000 --- a/projects/ad9081_fmca_ebz/vcu128/timing_constr.xdc +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# Primary clock definitions - -# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block -# Maximum values for Link clock: -# 204B - 15.5 Gbps /40 = 387.5MHz -# 204C - 24.75 Gbps /66 = 375MHz - -set link_mode [get_property LINK_MODE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]] - -set rx_lane_rate [get_property RX_LANE_RATE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]] -set tx_lane_rate [get_property TX_LANE_RATE [get_cells i_system_wrapper/system_i/util_mxfe_xcvr/inst]] - -set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] -set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] - -set rx_link_clk_period [expr 1000/$rx_link_clk] -set tx_link_clk_period [expr 1000/$tx_link_clk] - -set rx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_rx_jesd/rx/inst]] -set tx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_tx_jesd/tx/inst]] -set rx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_rx_jesd/rx/inst]] -set tx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_mxfe_tx_jesd/tx/inst]] - -set rx_device_clk [expr $rx_link_clk*$rx_ll_width/$rx_tpl_width] -set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width] -set rx_device_clk_period [expr 1000/$rx_device_clk] -set tx_device_clk_period [expr 1000/$tx_device_clk] - -# Set reference clock to same frequency as the link clock, -# this will ease the XCVR out clocks propagation calculation. -# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE -create_clock -name refclk -period $rx_link_clk_period [get_ports fpga_refclk_in_p] - -# device clock -create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clkin8_p] -create_clock -name tx_device_clk -period $tx_device_clk_period [get_ports clkin6_p] - -# Constraint SYSREFs -# Assumption is that REFCLK and SYSREF have similar propagation delay, -# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK -set_input_delay -clock [get_clocks rx_device_clk] \ - [get_property PERIOD [get_clocks rx_device_clk]] \ - [get_ports {sysref2_*}] -set_input_delay -clock [get_clocks tx_device_clk] -add_delay\ - [get_property PERIOD [get_clocks tx_device_clk]] \ - [get_ports {sysref2_*}] -set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous - -# For transceiver output clocks use reference clock divided by one -# This will help autoderive the clocks correcly -set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]] -set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]] -set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]] -set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]] -set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]] - -set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]] -set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]] -set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]] -set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]] -set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]] - From 8b63314f89c479601fe54cd6cd3c3e5c82befea6 Mon Sep 17 00:00:00 2001 From: sarpadi Date: Thu, 26 Jun 2025 15:48:14 +0300 Subject: [PATCH 2/3] ad9081_fmca_ebz: Update project doc Signed-off-by: sarpadi --- docs/projects/ad9081_fmca_ebz/index.rst | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index e08f85f73eb..d381b87e553 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -93,7 +93,7 @@ Supported carriers - :xilinx:`VCU118` - FMC+ * - - - :xilinx:`VCU128` + - :xilinx:`VCU128` * - FMC+ * - - :xilinx:`ZCU102` @@ -102,6 +102,12 @@ Supported carriers - :xilinx:`ZC706` - FMC HPC +.. admonition:: Legend + :class: note + + - ``*`` removed; last release that supports this project on this carrier is + :git-hdl:`hdl_2023_r2 ` + .. list-table:: :widths: 35 35 30 :header-rows: 1 From 1761e325933abc81f6b68b34eb899b9be9699b60 Mon Sep 17 00:00:00 2001 From: sarpadi Date: Tue, 15 Jul 2025 15:23:07 +0300 Subject: [PATCH 3/3] projects/common: Remove vcu128 support Signed-off-by: sarpadi --- docs/library/jesd204/index.rst | 2 +- docs/projects/template/index.rst | 3 - projects/common/vcu128/Makefile | 17 - projects/common/vcu128/system_bd.tcl | 14 - projects/common/vcu128/system_project.tcl | 16 - projects/common/vcu128/system_top.v | 147 -------- projects/common/vcu128/vcu128_fmcp.txt | 191 ---------- projects/common/vcu128/vcu128_system_bd.tcl | 350 ------------------ .../common/vcu128/vcu128_system_constr.xdc | 63 ---- projects/scripts/adi_project_xilinx.tcl | 6 +- 10 files changed, 2 insertions(+), 807 deletions(-) delete mode 100755 projects/common/vcu128/Makefile delete mode 100755 projects/common/vcu128/system_bd.tcl delete mode 100755 projects/common/vcu128/system_project.tcl delete mode 100755 projects/common/vcu128/system_top.v delete mode 100755 projects/common/vcu128/vcu128_fmcp.txt delete mode 100644 projects/common/vcu128/vcu128_system_bd.tcl delete mode 100644 projects/common/vcu128/vcu128_system_constr.xdc diff --git a/docs/library/jesd204/index.rst b/docs/library/jesd204/index.rst index 5b918249b18..fc771ba8ab7 100644 --- a/docs/library/jesd204/index.rst +++ b/docs/library/jesd204/index.rst @@ -474,7 +474,7 @@ HDL Example Projects - (AD9081) :git-hdl:`AMD Xilinx ZC706 ` - (AD9081) :git-hdl:`AMD Xilinx ZCU102 ` - (AD9081) :git-hdl:`AMD Xilinx VCU118 ` - - (AD9081) :git-hdl:`AMD Xilinx VCU128 ` + - (AD9081) :git-hdl:`AMD Xilinx VCU128 (RETIRED) ` - (AD9081) :git-hdl:`AMD Xilinx VCK190 ` - (AD9082) :git-hdl:`AMD Xilinx VCK190 ` - (AD9082) :git-hdl:`AMD Xilinx VCU118 ` diff --git a/docs/projects/template/index.rst b/docs/projects/template/index.rst index ee937a0af14..b31a894149d 100644 --- a/docs/projects/template/index.rst +++ b/docs/projects/template/index.rst @@ -54,9 +54,6 @@ Supported carriers * - - :xilinx:`VCU118` - FMC+ - * - - - :xilinx:`VCU128` - - FMC+ * - - :xilinx:`ZCU102` - FMC HPC0 diff --git a/projects/common/vcu128/Makefile b/projects/common/vcu128/Makefile deleted file mode 100755 index 8c075815a5a..00000000000 --- a/projects/common/vcu128/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := template_vcu128 - -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/vcu128/vcu128_system_constr.xdc -M_DEPS += ../../common/vcu128/vcu128_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v - -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom - -include ../../scripts/project-xilinx.mk diff --git a/projects/common/vcu128/system_bd.tcl b/projects/common/vcu128/system_bd.tcl deleted file mode 100755 index 5279c9d95c6..00000000000 --- a/projects/common/vcu128/system_bd.tcl +++ /dev/null @@ -1,14 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source $ad_hdl_dir/projects/scripts/adi_pd.tcl -source $ad_hdl_dir/projects/common/vcu128/vcu128_system_bd.tcl - -#system ID -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 - -sysid_gen_sys_init_file diff --git a/projects/common/vcu128/system_project.tcl b/projects/common/vcu128/system_project.tcl deleted file mode 100755 index afefc06e413..00000000000 --- a/projects/common/vcu128/system_project.tcl +++ /dev/null @@ -1,16 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project template_vcu128 -adi_project_files template_vcu118 [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/vcu128/vcu128_system_constr.xdc" \ - "system_top.v" ] - -adi_project_run template_vcu118 diff --git a/projects/common/vcu128/system_top.v b/projects/common/vcu128/system_top.v deleted file mode 100755 index bb9bb9a5a6f..00000000000 --- a/projects/common/vcu128/system_top.v +++ /dev/null @@ -1,147 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - input uart_sin, - output uart_sout, - - output ddr4_act_n, - output [16:0] ddr4_addr, - output [ 1:0] ddr4_ba, - output ddr4_bg, - output ddr4_ck_p, - output ddr4_ck_n, - output ddr4_cke, - output [ 1:0] ddr4_cs_n, - inout [ 8:0] ddr4_dm_n, - inout [71:0] ddr4_dq, - inout [ 8:0] ddr4_dqs_p, - inout [ 8:0] ddr4_dqs_n, - output ddr4_odt, - output ddr4_reset_n, - - output mdio_mdc, - inout mdio_mdio, - input phy_clk_p, - input phy_clk_n, - input phy_rx_p, - input phy_rx_n, - output phy_tx_p, - output phy_tx_n, - input phy_dummy_port_in, - - inout [ 7:0] gpio_bd, - - inout iic_scl, - inout iic_sda -); - - // internal signals - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - assign gpio_i[63:32] = gpio_o[63:32]; - assign gpio_i[31: 9] = gpio_o[31: 9]; - - // instantiations - ad_iobuf #( - .DATA_WIDTH (8) - ) i_iobuf_bd ( - .dio_t (gpio_t[ 7:0]), - .dio_i (gpio_o[ 7:0]), - .dio_o (gpio_i[ 7:0]), - .dio_p (gpio_bd )); - - system_wrapper i_system_wrapper ( - .sys_rst (sys_rst), - .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p), - - .ddr4_act_n (ddr4_act_n), - .ddr4_adr (ddr4_addr), - .ddr4_ba (ddr4_ba), - .ddr4_bg (ddr4_bg), - .ddr4_ck_c (ddr4_ck_n), - .ddr4_ck_t (ddr4_ck_p), - .ddr4_cke (ddr4_cke), - .ddr4_cs_n (ddr4_cs_n), - .ddr4_dm_n (ddr4_dm_n), - .ddr4_dq (ddr4_dq), - .ddr4_dqs_c (ddr4_dqs_n), - .ddr4_dqs_t (ddr4_dqs_p), - .ddr4_odt (ddr4_odt), - .ddr4_reset_n (ddr4_reset_n), - - .phy_sd (1'b1), - .phy_dummy_port_in (phy_dummy_port_in), - .sgmii_rxn (phy_rx_n), - .sgmii_rxp (phy_rx_p), - .sgmii_txn (phy_tx_n), - .sgmii_txp (phy_tx_p), - .mdio_mdc (mdio_mdc), - .mdio_mdio_io (mdio_mdio), - .sgmii_phyclk_clk_n (phy_clk_n), - .sgmii_phyclk_clk_p (phy_clk_p), - - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - - .uart_sin (uart_sin), - .uart_sout (uart_sout), - - .spi_clk_i (), - .spi_clk_o (), - .spi_csn_i (1'b1), - .spi_csn_o (1'b1), - .spi_sdi_i (1'b0), - .spi_sdo_i (), - .spi_sdo_o (), - - .gpio0_i (gpio_i[31:0]), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio1_i (gpio_i[63:32]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32])); - -endmodule diff --git a/projects/common/vcu128/vcu128_fmcp.txt b/projects/common/vcu128/vcu128_fmcp.txt deleted file mode 100755 index a8e4362b4af..00000000000 --- a/projects/common/vcu128/vcu128_fmcp.txt +++ /dev/null @@ -1,191 +0,0 @@ -FMC_pin FMC_port_name FPGA_pin FPGA_port_name Comments - -H5 FMC_CLK0_M2C_N F23 IO_L11N_T1U_N9_GC_72 - -H4 FMC_CLK0_M2C_P F24 IO_L11P_T1U_N8_GC_72 - -G3 FMC_CLK1_M2C_N G17 IO_L11N_T1U_N9_GC_71 - -G2 FMC_CLK1_M2C_P G18 IO_L11P_T1U_N8_GC_71 - -G7 FMC_LA00_CC_N E23 IO_L13N_T2L_N1_GC_QBC_72 - -G6 FMC_LA00_CC_P E24 IO_L13P_T2L_N0_GC_QBC_72 - -D9 FMC_LA01_CC_N F25 IO_L14N_T2L_N3_GC_72 - -D8 FMC_LA01_CC_P F26 IO_L14P_T2L_N2_GC_72 - -H8 FMC_LA02_N K22 IO_L4N_T0U_N7_DBC_AD7N_72 - -H7 FMC_LA02_P L23 IO_L4P_T0U_N6_DBC_AD7P_72 - -G10 FMC_LA03_N A26 IO_L23N_T3U_N9_72 - -G9 FMC_LA03_P B27 IO_L23P_T3U_N8_72 - -H11 FMC_LA04_N C24 IO_L20N_T3L_N3_AD1N_72 - -H10 FMC_LA04_P C25 IO_L20P_T3L_N2_AD1P_72 - -D12 FMC_LA05_N G27 IO_L9N_T1L_N5_AD12N_72 - -D11 FMC_LA05_P H27 IO_L9P_T1L_N4_AD12P_72 - -C11 FMC_LA06_N D22 IO_L15N_T2L_N5_AD11N_72 - -C10 FMC_LA06_P E22 IO_L15P_T2L_N4_AD11P_72 - -H14 FMC_LA07_N J27 IO_L5N_T0U_N9_AD14N_72 - -H13 FMC_LA07_P K27 IO_L5P_T0U_N8_AD14P_72 - -G13 FMC_LA08_N D27 IO_L18N_T2U_N11_AD2N_72 - -G12 FMC_LA08_P E27 IO_L18P_T2U_N10_AD2P_72 - -D15 FMC_LA09_N D26 IO_L17N_T2U_N9_AD10N_72 - -D14 FMC_LA09_P E26 IO_L17P_T2U_N8_AD10P_72 - -C15 FMC_LA10_N A23 IO_L22N_T3U_N7_DBC_AD0N_72 - -C14 FMC_LA10_P B23 IO_L22P_T3U_N6_DBC_AD0P_72 - -H17 FMC_LA11_N B25 IO_L21N_T3L_N5_AD8N_72 - -H16 FMC_LA11_P B26 IO_L21P_T3L_N4_AD8P_72 - -G16 FMC_LA12_N H22 IO_L8N_T1L_N3_AD5N_72 - -G15 FMC_LA12_P J22 IO_L8P_T1L_N2_AD5P_72 - -D18 FMC_LA13_N A24 IO_L24N_T3U_N11_72 - -D17 FMC_LA13_P A25 IO_L24P_T3U_N10_72 - -C19 FMC_LA14_N B22 IO_L19N_T3L_N1_DBC_AD9N_72 - -C18 FMC_LA14_P C23 IO_L19P_T3L_N0_DBC_AD9P_72 - -H20 FMC_LA15_N J25 IO_L6N_T0U_N11_AD6N_72 - -H19 FMC_LA15_P J26 IO_L6P_T0U_N10_AD6P_72 - -G19 FMC_LA16_N K23 IO_L3N_T0L_N5_AD15N_72 - -G18 FMC_LA16_P K24 IO_L3P_T0L_N4_AD15P_72 - -D21 FMC_LA17_CC_N E17 IO_L13N_T2L_N1_GC_QBC_71 - -D20 FMC_LA17_CC_P F18 IO_L13P_T2L_N0_GC_QBC_71 - -C23 FMC_LA18_CC_N E18 IO_L14N_T2L_N3_GC_71 - -C22 FMC_LA18_CC_P E19 IO_L14P_T2L_N2_GC_71 - -H23 FMC_LA19_N B17 IO_L21N_T3L_N5_AD8N_71 - -H22 FMC_LA19_P B18 IO_L21P_T3L_N4_AD8P_71 - -G22 FMC_LA20_N A20 IO_L22N_T3U_N7_DBC_AD0N_71 - -G21 FMC_LA20_P A21 IO_L22P_T3U_N6_DBC_AD0P_71 - -H26 FMC_LA21_N A18 IO_L23N_T3U_N9_71 - -H25 FMC_LA21_P A19 IO_L23P_T3U_N8_71 - -G25 FMC_LA22_N A16 IO_L24N_T3U_N11_71 - -G24 FMC_LA22_P B16 IO_L24P_T3U_N10_71 - -D24 FMC_LA23_N B20 IO_L20N_T3L_N3_AD1N_71 - -D23 FMC_LA23_P B21 IO_L20P_T3L_N2_AD1P_71 - -H29 FMC_LA24_N C17 IO_L19N_T3L_N1_DBC_AD9N_71 - -H28 FMC_LA24_P C18 IO_L19P_T3L_N0_DBC_AD9P_71 - -G28 FMC_LA25_N D19 IO_L18N_T2U_N11_AD2N_71 - -G27 FMC_LA25_P D20 IO_L18P_T2U_N10_AD2P_71 - -D27 FMC_LA26_N D16 IO_L17N_T2U_N9_AD10N_71 - -D26 FMC_LA26_P D17 IO_L17P_T2U_N8_AD10P_71 - -C27 FMC_LA27_N D21 IO_L16N_T2U_N7_QBC_AD3N_71 - -C26 FMC_LA27_P E21 IO_L16P_T2U_N6_QBC_AD3P_71 - -H32 FMC_LA28_N F21 IO_L10N_T1U_N7_QBC_AD4N_71 - -H31 FMC_LA28_P G21 IO_L10P_T1U_N6_QBC_AD4P_71 - -G31 FMC_LA29_N H18 IO_L9N_T1L_N5_AD12N_71 - -G30 FMC_LA29_P H19 IO_L9P_T1L_N4_AD12P_71 - -H35 FMC_LA30_N J19 IO_L6N_T0U_N11_AD6N_71 - -H34 FMC_LA30_P J20 IO_L6P_T0U_N10_AD6P_71 - -G34 FMC_LA31_N G16 IO_L7N_T1L_N1_QBC_AD13N_71 - -G33 FMC_LA31_P H17 IO_L7P_T1L_N0_QBC_AD13P_71 - -H38 FMC_LA32_N G20 IO_L8N_T1L_N3_AD5N_71 - -H37 FMC_LA32_P H20 IO_L8P_T1L_N2_AD5P_71 - -G37 FMC_LA33_N J21 IO_L5N_T0U_N9_AD14N_71 - -G36 FMC_LA33_P K21 IO_L5P_T0U_N8_AD14P_71 - -D5 FMC_GBTCLK0_M2C_N AV43 MGTREFCLK0N_124 - -D4 FMC_GBTCLK0_M2C_P AV42 MGTREFCLK0P_124 - -B21 FMC_GBTCLK1_M2C_N AR41 MGTREFCLK0N_125 - -B20 FMC_GBTCLK1_M2C_P AR40 MGTREFCLK0P_125 - -L13 FMC_GBTCLK2_M2C_N AN41 MGTREFCLK0N_126 - -L12 FMC_GBTCLK2_M2C_P AN40 MGTREFCLK0P_126 - -L9 FMC_GBTCLK3_M2C_N AL41 MGTREFCLK0N_127 - -L8 FMC_GBTCLK3_M2C_P AL40 MGTREFCLK0P_127 - -L5 FMC_GBTCLK4_M2C_N AJ41 MGTREFCLK0N_128 - -L4 FMC_GBTCLK4_M2C_P AJ40 MGTREFCLK0P_128 - -Z21 FMC_GBTCLK5_M2C_N AG41 MGTREFCLK0N_129 - -Z20 FMC_GBTCLK5_M2C_P AG40 MGTREFCLK0P_129 - -L17 FMC_SYNC_C2M_N D24 IO_L16N_T2U_N7_QBC_AD3N_72 - -L16 FMC_SYNC_C2M_P D25 IO_L16P_T2U_N6_QBC_AD3P_72 - -L29 FMC_SYNC_M2C_N G22 IO_L10N_T1U_N7_QBC_AD4N_72 - -L28 FMC_SYNC_M2C_P G23 IO_L10P_T1U_N6_QBC_AD4P_72 - -L21 FMC_REFCLK_C2M_N H23 IO_L7N_T1L_N1_QBC_AD13N_72 - -L20 FMC_REFCLK_C2M_P H24 IO_L7P_T1L_N0_QBC_AD13P_72 - -L25 FMC_REFCLK_M2C_N G25 IO_L12N_T1U_N11_GC_72 - -L24 FMC_REFCLK_M2C_P G26 IO_L12P_T1U_N10_GC_72 - -C3 FMC_DP0_C2M_N BC49 MGTYTXN0_124 - -C2 FMC_DP0_C2M_P BC48 MGTYTXP0_124 - -C7 FMC_DP0_M2C_N BC54 MGTYRXN0_124 - -C6 FMC_DP0_M2C_P BC53 MGTYRXP0_124 - -A23 FMC_DP1_C2M_N BC45 MGTYTXN1_124 - -A22 FMC_DP1_C2M_P BC44 MGTYTXP1_124 - -A3 FMC_DP1_M2C_N BB52 MGTYRXN1_124 - -A2 FMC_DP1_M2C_P BB51 MGTYRXP1_124 - -A27 FMC_DP2_C2M_N BB47 MGTYTXN2_124 - -A26 FMC_DP2_C2M_P BB46 MGTYTXP2_124 - -A7 FMC_DP2_M2C_N BA54 MGTYRXN2_124 - -A6 FMC_DP2_M2C_P BA53 MGTYRXP2_124 - -A31 FMC_DP3_C2M_N BA45 MGTYTXN3_124 - -A30 FMC_DP3_C2M_P BA44 MGTYTXP3_124 - -A11 FMC_DP3_M2C_N BA50 MGTYRXN3_124 - -A10 FMC_DP3_M2C_P BA49 MGTYRXP3_124 - -A35 FMC_DP4_C2M_N AY47 MGTYTXN0_125 - -A34 FMC_DP4_C2M_P AY46 MGTYTXP0_125 - -A15 FMC_DP4_M2C_N AY52 MGTYRXN0_125 - -A14 FMC_DP4_M2C_P AY51 MGTYRXP0_125 - -A39 FMC_DP5_C2M_N AW45 MGTYTXN1_125 - -A38 FMC_DP5_C2M_P AW44 MGTYTXP1_125 - -A19 FMC_DP5_M2C_N AW54 MGTYRXN1_125 - -A18 FMC_DP5_M2C_P AW53 MGTYRXP1_125 - -B37 FMC_DP6_C2M_N AV47 MGTYTXN2_125 - -B36 FMC_DP6_C2M_P AV46 MGTYTXP2_125 - -B17 FMC_DP6_M2C_N AW50 MGTYRXN2_125 - -B16 FMC_DP6_M2C_P AW49 MGTYRXP2_125 - -B33 FMC_DP7_C2M_N AU45 MGTYTXN3_125 - -B32 FMC_DP7_C2M_P AU44 MGTYTXP3_125 - -B13 FMC_DP7_M2C_N AV52 MGTYRXN3_125 - -B12 FMC_DP7_M2C_P AV51 MGTYRXP3_125 - -B29 FMC_DP8_C2M_N AU49 MGTYTXN0_126 - -B28 FMC_DP8_C2M_P AU48 MGTYTXP0_126 - -B9 FMC_DP8_M2C_N AU54 MGTYRXN0_126 - -B8 FMC_DP8_M2C_P AU53 MGTYRXP0_126 - -B25 FMC_DP9_C2M_N AT47 MGTYTXN1_126 - -B24 FMC_DP9_C2M_P AT46 MGTYTXP1_126 - -B5 FMC_DP9_M2C_N AT52 MGTYRXN1_126 - -B4 FMC_DP9_M2C_P AT51 MGTYRXP1_126 - -Z25 FMC_DP10_C2M_N AR49 MGTYTXN2_126 - -Z24 FMC_DP10_C2M_P AR48 MGTYTXP2_126 - -Y11 FMC_DP10_M2C_N AR54 MGTYRXN2_126 - -Y10 FMC_DP10_M2C_P AR53 MGTYRXP2_126 - -Y27 FMC_DP11_C2M_N AR45 MGTYTXN3_126 - -Y26 FMC_DP11_C2M_P AR44 MGTYTXP3_126 - -Z13 FMC_DP11_M2C_N AP52 MGTYRXN3_126 - -Z12 FMC_DP11_M2C_P AP51 MGTYRXP3_126 - -Z29 FMC_DP12_C2M_N AP47 MGTYTXN0_127 - -Z28 FMC_DP12_C2M_P AP46 MGTYTXP0_127 - -Y15 FMC_DP12_M2C_N AN54 MGTYRXN0_127 - -Y14 FMC_DP12_M2C_P AN53 MGTYRXP0_127 - -Y31 FMC_DP13_C2M_N AN45 MGTYTXN1_127 - -Y30 FMC_DP13_C2M_P AN44 MGTYTXP1_127 - -Z17 FMC_DP13_M2C_N AN50 MGTYRXN1_127 - -Z16 FMC_DP13_M2C_P AN49 MGTYRXP1_127 - -M19 FMC_DP14_C2M_N AM47 MGTYTXN2_127 - -M19 FMC_DP14_C2M_N AM47 MGTYTXN2_127 - -M18 FMC_DP14_C2M_P AM46 MGTYTXP2_127 - -Y19 FMC_DP14_M2C_N AM52 MGTYRXN2_127 - -Y18 FMC_DP14_M2C_P AM51 MGTYRXP2_127 - -M23 FMC_DP15_C2M_N AL45 MGTYTXN3_127 - -M22 FMC_DP15_C2M_P AL44 MGTYTXP3_127 - -Y23 FMC_DP15_M2C_N AL54 MGTYRXN3_127 - -Y22 FMC_DP15_M2C_P AL53 MGTYRXP3_127 - -M27 FMC_DP16_C2M_N AK47 MGTYTXN0_128 - -M26 FMC_DP16_C2M_P AK46 MGTYTXP0_128 - -Z33 FMC_DP16_M2C_N AL50 MGTYRXN0_128 - -Z32 FMC_DP16_M2C_P AL49 MGTYRXP0_128 - -M31 FMC_DP17_C2M_N AJ49 MGTYTXN1_128 - -M30 FMC_DP17_C2M_P AJ48 MGTYTXP1_128 - -Y35 FMC_DP17_M2C_N AK52 MGTYRXN1_128 - -Y34 FMC_DP17_M2C_P AK51 MGTYRXP1_128 - -M35 FMC_DP18_C2M_N AJ45 MGTYTXN2_128 - -M34 FMC_DP18_C2M_P AJ44 MGTYTXP2_128 - -Z37 FMC_DP18_M2C_N AJ54 MGTYRXN2_128 - -Z36 FMC_DP18_M2C_P AJ53 MGTYRXP2_128 - -M39 FMC_DP19_C2M_N AH47 MGTYTXN3_128 - -M38 FMC_DP19_C2M_P AH46 MGTYTXP3_128 - -Y39 FMC_DP19_M2C_N AH52 MGTYRXN3_128 - -Y38 FMC_DP19_M2C_P AH51 MGTYRXP3_128 - -Z9 FMC_DP20_C2M_N AG49 MGTYTXN0_129 - -Z8 FMC_DP20_C2M_P AG48 MGTYTXP0_129 - -M15 FMC_DP20_M2C_N AG54 MGTYRXN0_129 - -M14 FMC_DP20_M2C_P AG53 MGTYRXP0_129 - -Y7 FMC_DP21_C2M_N AG45 MGTYTXN1_129 - -Y6 FMC_DP21_C2M_P AG44 MGTYTXP1_129 - -M11 FMC_DP21_M2C_N AF52 MGTYRXN1_129 - -M10 FMC_DP21_M2C_P AF51 MGTYRXP1_129 - -Z5 FMC_DP22_C2M_N AF47 MGTYTXN2_129 - -Z4 FMC_DP22_C2M_P AF46 MGTYTXP2_129 - -M7 FMC_DP22_M2C_N AE54 MGTYRXN2_129 - -M6 FMC_DP22_M2C_P AE53 MGTYRXP2_129 - -Y3 FMC_DP23_C2M_N AE45 MGTYTXN3_129 - -Y2 FMC_DP23_C2M_P AE44 MGTYTXP3_129 - -M3 FMC_DP23_M2C_N AE50 MGTYRXN3_129 - -M2 FMC_DP23_M2C_P AE49 MGTYRXP3_129 - \ No newline at end of file diff --git a/projects/common/vcu128/vcu128_system_bd.tcl b/projects/common/vcu128/vcu128_system_bd.tcl deleted file mode 100644 index f3d6acacdbf..00000000000 --- a/projects/common/vcu128/vcu128_system_bd.tcl +++ /dev/null @@ -1,350 +0,0 @@ -############################################################################### -## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -set CACHE_COHERENCY false - -# create board design -# interface ports - -create_bd_port -dir I -type rst sys_rst - -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4 - -create_bd_port -dir I phy_sd -create_bd_port -dir O -type rst phy_rst_n -create_bd_port -dir I phy_dummy_port_in - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sgmii_phyclk -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main - -create_bd_port -dir I uart_sin -create_bd_port -dir O uart_sout - -create_bd_port -dir O -from 7 -to 0 spi_csn_o -create_bd_port -dir I -from 7 -to 0 spi_csn_i -create_bd_port -dir I spi_clk_i -create_bd_port -dir O spi_clk_o -create_bd_port -dir I spi_sdo_i -create_bd_port -dir O spi_sdo_o -create_bd_port -dir I spi_sdi_i - -create_bd_port -dir I -from 31 -to 0 gpio0_i -create_bd_port -dir O -from 31 -to 0 gpio0_o -create_bd_port -dir O -from 31 -to 0 gpio0_t -create_bd_port -dir I -from 31 -to 0 gpio1_i -create_bd_port -dir O -from 31 -to 0 gpio1_o -create_bd_port -dir O -from 31 -to 0 gpio1_t - -# io settings - -set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] -set_property -dict [list CONFIG.FREQ_HZ {100000000}] [get_bd_intf_ports sys_clk] -set_property -dict [list CONFIG.FREQ_HZ {625000000}] [get_bd_intf_ports sgmii_phyclk] - -# instance: microblaze - processor - -ad_ip_instance microblaze sys_mb -ad_ip_parameter sys_mb CONFIG.G_TEMPLATE_LIST 4 -ad_ip_parameter sys_mb CONFIG.C_DCACHE_FORCE_TAG_LUTRAM 1 -ad_ip_parameter sys_mb CONFIG.C_ADDR_TAG_BITS 15 -ad_ip_parameter sys_mb CONFIG.C_CACHE_BYTE_SIZE 65536 -ad_ip_parameter sys_mb CONFIG.C_DCACHE_ADDR_TAG 15 -ad_ip_parameter sys_mb CONFIG.C_DCACHE_BYTE_SIZE 65536 -ad_ip_parameter sys_mb CONFIG.C_USE_BRANCH_TARGET_CACHE 1 - -# instance: microblaze - local memory & bus - -ad_ip_instance lmb_v10 sys_dlmb -ad_ip_instance lmb_v10 sys_ilmb - -ad_ip_instance lmb_bram_if_cntlr sys_dlmb_cntlr -ad_ip_parameter sys_dlmb_cntlr CONFIG.C_ECC {0} - -ad_ip_instance lmb_bram_if_cntlr sys_ilmb_cntlr -ad_ip_parameter sys_ilmb_cntlr CONFIG.C_ECC {0} - -ad_ip_instance blk_mem_gen sys_lmb_bram -ad_ip_parameter sys_lmb_bram CONFIG.Memory_Type True_Dual_Port_RAM -ad_ip_parameter sys_lmb_bram CONFIG.use_bram_block BRAM_Controller - -# instance: microblaze- mdm - -ad_ip_instance mdm sys_mb_debug -ad_ip_parameter sys_mb_debug CONFIG.C_USE_UART 1 - -# instance: system reset/clocks -ad_ip_instance proc_sys_reset sys_rstgen -ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 -ad_ip_instance proc_sys_reset sys_mb_rstgen -ad_ip_parameter sys_mb_rstgen CONFIG.C_EXT_RST_WIDTH 1 -ad_ip_instance proc_sys_reset sys_250m_rstgen -ad_ip_parameter sys_250m_rstgen CONFIG.C_EXT_RST_WIDTH 1 -ad_ip_instance proc_sys_reset sys_500m_rstgen -ad_ip_parameter sys_500m_rstgen CONFIG.C_EXT_RST_WIDTH 1 -ad_ip_instance proc_sys_reset sys_hbm_rstgen -ad_ip_parameter sys_hbm_rstgen CONFIG.C_EXT_RST_WIDTH 1 - -# Clock for HBM -ad_ip_instance clk_wiz hbm_clk_wiz [ list \ - PRIMITIVE {Auto} \ - PRIM_IN_FREQ {100} \ - CLKOUT1_REQUESTED_OUT_FREQ {450} \ -] - -# instance: ddr4 -# -ad_ip_instance ip:ddr4 axi_ddr_cntrl -ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE {default_100mhz_clk} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} -ad_ip_parameter axi_ddr_cntrl ONFIG.RESET_BOARD_INTERFACE {reset} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_Clamshell {true} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_InputClockPeriod {10000} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_DataWidth {72} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_Ecc {true} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_AxiDataWidth {512} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_AxiAddressWidth {32} -ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ 200 -ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ 250 -ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 500 -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.BANK_GROUP_WIDTH {1} -ad_ip_parameter axi_ddr_cntrl CONFIG.C0.CS_WIDTH {2} - -ad_ip_instance proc_sys_reset axi_ddr_cntrl_rstgen - -# instance: default peripherals - -ad_ip_instance axi_ethernet axi_ethernet_0 -ad_ip_parameter axi_ethernet_0 CONFIG.DIFFCLK_BOARD_INTERFACE sgmii_phyclk -ad_ip_parameter axi_ethernet_0 CONFIG.ETHERNET_BOARD_INTERFACE sgmii_lvds -ad_ip_parameter axi_ethernet_0 CONFIG.MDIO_BOARD_INTERFACE mdio_mdc -ad_ip_parameter axi_ethernet_0 CONFIG.PHYRST_BOARD_INTERFACE_DUMMY_PORT dummy_port_in -ad_ip_parameter axi_ethernet_0 CONFIG.TXCSUM Full -ad_ip_parameter axi_ethernet_0 CONFIG.RXCSUM Full -ad_ip_parameter axi_ethernet_0 CONFIG.TXMEM 8k -ad_ip_parameter axi_ethernet_0 CONFIG.RXMEM 8k - -ad_ip_instance axi_dma axi_ethernet_dma -ad_ip_parameter axi_ethernet_dma CONFIG.c_include_mm2s_dre 1 -ad_ip_parameter axi_ethernet_dma CONFIG.c_sg_use_stsapp_length 1 -ad_ip_parameter axi_ethernet_dma CONFIG.c_include_s2mm_dre 1 - -ad_ip_instance axi_iic axi_iic_main - -ad_ip_instance axi_uartlite axi_uart -ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200 - -ad_ip_instance axi_timer axi_timer - -ad_ip_instance axi_quad_spi axi_spi -ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0 -ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 8 -ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8 - -ad_ip_instance axi_gpio axi_gpio -ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1 -ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32 -ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32 -ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1 - -ad_ip_instance util_ds_buf sys_cpu_clk_BUFGCE -ad_ip_parameter sys_cpu_clk_BUFGCE CONFIG.C_BUF_TYPE {BUFGCE_DIV} -ad_ip_parameter sys_cpu_clk_BUFGCE CONFIG.C_BUFGCE_DIV 2 -ad_connect sys_cpu_clk_BUFGCE/BUFGCE_CE VCC -ad_connect sys_cpu_clk_BUFGCE/BUFGCE_CLR GND -ad_connect sys_cpu_clk_BUFGCE/BUFGCE_I sys_mb_clk -ad_connect sys_cpu_clk sys_cpu_clk_BUFGCE/BUFGCE_O - -# instance: interrupt - -ad_ip_instance axi_intc axi_intc -ad_ip_parameter axi_intc CONFIG.C_HAS_FAST 0 - -ad_ip_instance xlconcat sys_concat_intc -ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 17 - -# ddr4 - -ad_connect sys_rst axi_ddr_cntrl/sys_rst -ad_connect sys_clk axi_ddr_cntrl/C0_SYS_CLK -ad_connect ddr4 axi_ddr_cntrl/C0_DDR4 -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst axi_ddr_cntrl_rstgen/ext_reset_in -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_rstgen/ext_reset_in -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_mb_rstgen/ext_reset_in -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_250m_rstgen/ext_reset_in -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_500m_rstgen/ext_reset_in -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst sys_hbm_rstgen/ext_reset_in -ad_connect sys_mem_clk axi_ddr_cntrl/c0_ddr4_ui_clk -ad_connect sys_mem_clk axi_ddr_cntrl_rstgen/slowest_sync_clk -ad_connect sys_mb_clk axi_ddr_cntrl/addn_ui_clkout1 -ad_connect sys_mb_clk sys_mb_rstgen/slowest_sync_clk -ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk -ad_connect sys_mem_resetn axi_ddr_cntrl_rstgen/peripheral_aresetn -ad_connect sys_mem_resetn axi_ddr_cntrl/c0_ddr4_aresetn -ad_connect sys_250m_clk axi_ddr_cntrl/addn_ui_clkout2 -ad_connect sys_250m_clk sys_250m_rstgen/slowest_sync_clk -ad_connect sys_500m_clk axi_ddr_cntrl/addn_ui_clkout3 -ad_connect sys_500m_clk sys_500m_rstgen/slowest_sync_clk -ad_connect sys_hbm_clk hbm_clk_wiz/clk_out1 -ad_connect sys_hbm_clk sys_hbm_rstgen/slowest_sync_clk -ad_connect sys_cpu_reset sys_rstgen/peripheral_reset -ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn -ad_connect sys_250m_reset sys_250m_rstgen/peripheral_reset -ad_connect sys_250m_resetn sys_250m_rstgen/peripheral_aresetn -ad_connect sys_500m_reset sys_500m_rstgen/peripheral_reset -ad_connect sys_500m_resetn sys_500m_rstgen/peripheral_aresetn - -# generic system clocks pointers - -set sys_cpu_clk [get_bd_pins sys_cpu_clk_BUFGCE/BUFGCE_O] -set sys_mb_clk [get_bd_nets axi_ddr_cntrl/addn_ui_clkout1] -set sys_dma_clk [get_bd_nets sys_250m_clk] -set sys_iodelay_clk [get_bd_nets sys_500m_clk] -set sys_hbm_clk [get_bd_pins hbm_clk_wiz/clk_out1] - -set sys_cpu_reset [get_bd_nets sys_cpu_reset] -set sys_cpu_resetn [get_bd_pins sys_rstgen/peripheral_aresetn] -set sys_dma_reset [get_bd_nets sys_250m_reset] -set sys_dma_resetn [get_bd_nets sys_250m_resetn] -set sys_iodelay_reset [get_bd_nets sys_500m_reset] -set sys_iodelay_resetn [get_bd_nets sys_500m_resetn] -set sys_hbm_reset [get_bd_pins sys_hbm_rstgen/peripheral_reset] -set sys_hbm_resetn [get_bd_pins sys_hbm_rstgen/peripheral_aresetn] - -# clock gen connections - -ad_connect $sys_cpu_clk hbm_clk_wiz/clk_in1 - -# microblaze debug & interrupt - -ad_connect sys_mb_clk sys_mb/Clk -ad_connect sys_mb_clk sys_dlmb/LMB_Clk -ad_connect sys_mb_clk sys_ilmb/LMB_Clk -ad_connect sys_mb_clk sys_dlmb_cntlr/LMB_Clk -ad_connect sys_mb_clk sys_ilmb_cntlr/LMB_Clk -ad_connect sys_mb_rstgen/mb_reset sys_mb/Reset -ad_connect sys_mb_rstgen/bus_struct_reset sys_dlmb/SYS_Rst -ad_connect sys_mb_rstgen/bus_struct_reset sys_ilmb/SYS_Rst -ad_connect sys_mb_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst -ad_connect sys_mb_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst -ad_connect sys_mb/DLMB sys_dlmb/LMB_M -ad_connect sys_mb/ILMB sys_ilmb/LMB_M -ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB -ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB -ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA -ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB -ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst -ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG -ad_connect axi_intc/interrupt sys_mb/INTERRUPT -ad_connect axi_intc/intr sys_concat_intc/dout - -# ethernet - -ad_connect sgmii axi_ethernet_0/sgmii -ad_connect sgmii_phyclk axi_ethernet_0/lvds_clk -ad_connect mdio axi_ethernet_0/mdio -ad_connect phy_sd axi_ethernet_0/signal_detect -ad_connect phy_dummy_port_in axi_ethernet_0/dummy_port_in -ad_connect sys_cpu_clk axi_ethernet_0/axis_clk -ad_connect axi_ethernet_0/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S -ad_connect axi_ethernet_0/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL -ad_connect axi_ethernet_0/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM -ad_connect axi_ethernet_0/m_axis_rxs axi_ethernet_dma/S_AXIS_STS -ad_connect axi_ethernet_0/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n -ad_connect axi_ethernet_0/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n -ad_connect axi_ethernet_0/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n -ad_connect axi_ethernet_0/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n - -# system id - -ad_ip_instance axi_sysid axi_sysid_0 -ad_ip_instance sysid_rom rom_sys_0 - -ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr -ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data -ad_connect sys_cpu_clk rom_sys_0/clk - -# iic, spi and gpio - -ad_connect iic_main axi_iic_main/iic -ad_connect uart_sin axi_uart/rx -ad_connect uart_sout axi_uart/tx -ad_connect spi_csn_i axi_spi/ss_i -ad_connect spi_csn_o axi_spi/ss_o -ad_connect spi_clk_i axi_spi/sck_i -ad_connect spi_clk_o axi_spi/sck_o -ad_connect spi_sdo_i axi_spi/io0_i -ad_connect spi_sdo_o axi_spi/io0_o -ad_connect spi_sdi_i axi_spi/io1_i -ad_connect gpio0_i axi_gpio/gpio_io_i -ad_connect gpio0_o axi_gpio/gpio_io_o -ad_connect gpio0_t axi_gpio/gpio_io_t -ad_connect gpio1_i axi_gpio/gpio2_io_i -ad_connect gpio1_o axi_gpio/gpio2_io_o -ad_connect gpio1_t axi_gpio/gpio2_io_t -ad_connect sys_cpu_clk axi_spi/ext_spi_clk - -# defaults (interrupts) - -ad_connect sys_concat_intc/In0 axi_timer/interrupt -ad_connect sys_concat_intc/In1 axi_ethernet_0/interrupt -ad_connect sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut -ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut -ad_connect sys_concat_intc/In4 axi_uart/interrupt -ad_connect sys_concat_intc/In5 GND -ad_connect sys_concat_intc/In6 GND -ad_connect sys_concat_intc/In7 GND -ad_connect sys_concat_intc/In8 GND -ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt -ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt -ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt -ad_connect sys_concat_intc/In12 GND -ad_connect sys_concat_intc/In13 GND -ad_connect sys_concat_intc/In14 GND -ad_connect sys_concat_intc/In15 GND -ad_connect sys_concat_intc/In16 GND - -# interconnect - processor - -ad_cpu_interconnect 0x40C00000 axi_ethernet_0 -ad_cpu_interconnect 0x41E10000 axi_ethernet_dma -ad_cpu_interconnect 0x40000000 axi_gpio -ad_cpu_interconnect 0x40600000 axi_uart -ad_cpu_interconnect 0x41200000 axi_intc -ad_cpu_interconnect 0x41C00000 axi_timer -ad_cpu_interconnect 0x41600000 axi_iic_main -ad_cpu_interconnect 0x45000000 axi_sysid_0 -ad_cpu_interconnect 0x44A70000 axi_spi -ad_cpu_interconnect 0x41400000 sys_mb_debug -ad_cpu_interconnect 0x45100000 axi_ddr_cntrl C0_DDR4_S_AXI_CTRL - -### Workaround for DDR controller with control interface -### DDR contoller control interface runs at UI clock not CPU clock -set_property -dict [list CONFIG.NUM_CLKS {3}] [get_bd_cells axi_dp_interconnect] -ad_connect axi_ddr_cntrl/c0_ddr4_ui_clk axi_dp_interconnect/aclk1 - -### Peripheral Data Interface runs at the sys_mb_clk frequency -ad_connect sys_mb_clk axi_dp_interconnect/aclk2 - -# interconnect - memory - -ad_mem_hp0_interconnect sys_mem_clk axi_ddr_cntrl/C0_DDR4_S_AXI -ad_mem_hp0_interconnect sys_mb_clk sys_mb/M_AXI_DC -ad_mem_hp0_interconnect sys_mb_clk sys_mb/M_AXI_IC -ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG -ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S -ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM - -create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \ - [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr -create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \ - [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr - diff --git a/projects/common/vcu128/vcu128_system_constr.xdc b/projects/common/vcu128/vcu128_system_constr.xdc deleted file mode 100644 index 4dc2fec9b28..00000000000 --- a/projects/common/vcu128/vcu128_system_constr.xdc +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################### -## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# constraints - -set_property -dict {PACKAGE_PIN BM29 IOSTANDARD LVCMOS12} [get_ports sys_rst] - -# clocks -# DDR4 Component Memory I/F clock, fixed 100 MHz LVDS [U76] - -set_property -dict {PACKAGE_PIN BH51 IOSTANDARD LVDS} [get_ports sys_clk_p] -set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD LVDS} [get_ports sys_clk_n] - -# ethernet - -set_property PACKAGE_PIN BG22 [get_ports phy_tx_p] -set_property PACKAGE_PIN BH22 [get_ports phy_tx_n] -set_property PACKAGE_PIN BJ22 [get_ports phy_rx_p] -set_property PACKAGE_PIN BK21 [get_ports phy_rx_n] - -set_property -dict {PACKAGE_PIN BH27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports phy_clk_p] -set_property -dict {PACKAGE_PIN BJ27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports phy_clk_n] - -set_property -dict {PACKAGE_PIN BN27 IOSTANDARD LVCMOS18} [get_ports mdio_mdc] -set_property -dict {PACKAGE_PIN BG23 IOSTANDARD LVCMOS18} [get_ports mdio_mdio] - -# uart - -set_property -dict {PACKAGE_PIN BP26 IOSTANDARD LVCMOS18} [get_ports uart_sin] -set_property -dict {PACKAGE_PIN BN26 IOSTANDARD LVCMOS18} [get_ports uart_sout] - -set_property -dict {PACKAGE_PIN BH24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## GPIO_LED_0_LS -set_property -dict {PACKAGE_PIN BG24 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## GPIO_LED_1_LS -set_property -dict {PACKAGE_PIN BG25 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## GPIO_LED_2_LS -set_property -dict {PACKAGE_PIN BF25 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## GPIO_LED_3_LS -set_property -dict {PACKAGE_PIN BF26 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## GPIO_LED_4_LS -set_property -dict {PACKAGE_PIN BF27 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## GPIO_LED_5_LS -set_property -dict {PACKAGE_PIN BG27 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## GPIO_LED_6_LS -set_property -dict {PACKAGE_PIN BG28 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## GPIO_LED_7_LS - -# iic - -set_property -dict {PACKAGE_PIN BM27 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl] -set_property -dict {PACKAGE_PIN BL28 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda] - -# Create SPI clock -create_generated_clock -name spi_clk \ - -source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \ - -divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o] - -# Balance clocks -# -# Minimize skew on synchronous CDC timing paths between clocks originating -# from the same MMCM source. (sys_mem_clk and sys_cpu_clk) -# This is required mostly by the smart interconnect. -# Property must be applied directly to the output net of BUFGs. -set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS \ - [list [get_nets [get_property PARENT [get_nets {i_system_wrapper/system_i/sys_cpu_clk}]]] \ - [get_nets [get_property PARENT [get_nets {i_system_wrapper/system_i/sys_mem_clk}]]] \ - ] - diff --git a/projects/scripts/adi_project_xilinx.tcl b/projects/scripts/adi_project_xilinx.tcl index d29c2eaf752..3a0c44fd518 100644 --- a/projects/scripts/adi_project_xilinx.tcl +++ b/projects/scripts/adi_project_xilinx.tcl @@ -45,7 +45,7 @@ set p_prcfg_status "" # \param[parameter_list] - a list of global parameters (parameters of the # system_top module) # -# Supported carrier names are: ac701, kc705, vc707, vcu118, vcu128, kcu105, zed, +# Supported carrier names are: ac701, kc705, vc707, vcu118, kcu105, zed, # microzed, zc702, zc706, mitx405, zcu102. # proc adi_project {project_name {mode 0} {parameter_list {}} } { @@ -70,10 +70,6 @@ proc adi_project {project_name {mode 0} {parameter_list {}} } { set device "xcvu9p-flga2104-2L-e" set board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end] } - if [regexp "_vcu128" $project_name] { - set device "xcvu37p-fsvh2892-2L-e" - set board [lindex [lsearch -all -inline [get_board_parts] *vcu128:part0*] end] - } if [regexp "_kcu105" $project_name] { set device "xcku040-ffva1156-2-e" set board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end]