diff --git a/docs/library/jesd204/index.rst b/docs/library/jesd204/index.rst index 5b918249b18..4125f9f7e10 100644 --- a/docs/library/jesd204/index.rst +++ b/docs/library/jesd204/index.rst @@ -495,7 +495,7 @@ HDL Example Projects - :ref:`AD6676EVB Reference Design ` on: - - :git-hdl:`AMD Xilinx VC707 ` + - :git-hdl:`AMD Xilinx VC707 (RETIRED) ` - :git-hdl:`AMD Xilinx ZC706 ` - :ref:`AD9083-EVB Reference Design ` on: diff --git a/docs/projects/ad6676evb/index.rst b/docs/projects/ad6676evb/index.rst index 8d6a6d96755..0b13c54fab7 100644 --- a/docs/projects/ad6676evb/index.rst +++ b/docs/projects/ad6676evb/index.rst @@ -41,12 +41,18 @@ Supported carriers - Carrier - FMC slot * - :adi:`EVAL-AD6676` - - :xilinx:`VC707` + - :xilinx:`VC707` * - FMC1 HPC * - - :xilinx:`ZC706` - FMC HPC +.. admonition:: Legend + :class: note + + - ``*`` removed; last release that supports this project on this carrier is + :git-hdl:`hdl_2023_r2 ` + Block design ------------------------------------------------------------------------------- @@ -247,27 +253,17 @@ the HDL repository. **Linux/Cygwin/WSL** -Building the VC707/ZC706 project with the default configuration, +Building the ZC706 project with the default configuration, RX_JESD_L=2 lanes. -.. shell:: bash - - $cd hdl/projects/ad6676evb/vc707 - $make - .. shell:: bash $cd hdl/projects/ad6676evb/zc706 $make -Building the VC707/ZC706 project with the other available configuration, +Building the ZC706 project with the other available configuration, with just **one lane**: -.. shell:: bash - - $cd hdl/projects/ad6676evb/vc707 - $make RX_JESD_L=1 - .. shell:: bash $cd hdl/projects/ad6676evb/zc706 diff --git a/docs/projects/fmcomms2/index.rst b/docs/projects/fmcomms2/index.rst index 4099b715987..caa4b133cf6 100644 --- a/docs/projects/fmcomms2/index.rst +++ b/docs/projects/fmcomms2/index.rst @@ -62,7 +62,7 @@ Supported carriers - :xilinx:`KCU105` - FMC LPC * - - - :xilinx:`VC707` + - :xilinx:`VC707` * - FMC HPC1 * - - :xilinx:`ZC702` @@ -77,6 +77,12 @@ Supported carriers - `ZedBoard `__ - FMC LPC +.. admonition:: Legend + :class: note + + - ``*`` removed; last release that supports this project on this carrier is + :git-hdl:`hdl_2023_r2 ` + Block design ------------------------------------------------------------------------------- diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile deleted file mode 100644 index 45d4dc8558d..00000000000 --- a/projects/ad6676evb/vc707/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := ad6676evb_vc707 - -M_DEPS += ../common/ad6676evb_bd.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/vc707/vc707_system_mig.prj -M_DEPS += ../../common/vc707/vc707_system_constr.xdc -M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl -M_DEPS += ../../../library/common/ad_sysref_gen.v -M_DEPS += ../../../library/common/ad_iobuf.v - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc -LIB_DEPS += jesd204/axi_jesd204_rx -LIB_DEPS += jesd204/jesd204_rx -LIB_DEPS += sysid_rom -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += xilinx/axi_adxcvr -LIB_DEPS += xilinx/util_adxcvr - -include ../../scripts/project-xilinx.mk diff --git a/projects/ad6676evb/vc707/README.md b/projects/ad6676evb/vc707/README.md deleted file mode 100644 index b3199bc016f..00000000000 --- a/projects/ad6676evb/vc707/README.md +++ /dev/null @@ -1,30 +0,0 @@ -# AD6676-EVB/VC707 HDL Project - -## Building the project - -The parameter configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration. - -``` -cd projects/ad6676evb/vc707 -make -``` - -All of the RX link modes can be found in the [AD6676 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD6676.pdf). We offer support for only one of them. - -If other configurations are desired, then the parameter from the HDL project (see below) needs to be changed, as well as the Linux/no-OS project configurations. - -The overwritable parameter from the environment: - -- [RX/TX]_JESD_L: [RX/TX] number of lanes per link - -### Example configurations - -#### Default configuration - -This specific command is equivalent to running `make` only: - -``` -make RX_JESD_L=2 -``` - -Corresponding device tree: [vc707_ad6676evb.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vc707_ad6676evb.dts) diff --git a/projects/ad6676evb/vc707/system_bd.tcl b/projects/ad6676evb/vc707/system_bd.tcl deleted file mode 100644 index 8c2ff1d293c..00000000000 --- a/projects/ad6676evb/vc707/system_bd.tcl +++ /dev/null @@ -1,17 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl -source ../common/ad6676evb_bd.tcl -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -#system ID -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 - -set sys_cstring "RX:L=$ad_project_params(RX_JESD_L)" - -sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc deleted file mode 100644 index b50d17e352a..00000000000 --- a/projects/ad6676evb/vc707/system_constr.xdc +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# ad6676 - -set_property -dict {PACKAGE_PIN A10} [get_ports rx_ref_clk_p] ; ## D04 FMC1_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN A9 } [get_ports rx_ref_clk_n] ; ## D05 FMC1_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN D8 } [get_ports rx_data_p[0]] ; ## C06 FMC1_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN D7 } [get_ports rx_data_n[0]] ; ## C07 FMC1_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN C6 } [get_ports rx_data_p[1]] ; ## A02 FMC1_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_n[1]] ; ## A03 FMC1_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC1_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC1_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G06 FMC1_HPC_LA00_CC_P -set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G07 FMC1_HPC_LA00_CC_N - -set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports spi_csn] ; ## D12 FMC1_HPC_LA05_N -set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H11 FMC1_HPC_LA04_N -set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H10 FMC1_HPC_LA04_P -set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## D11 FMC1_HPC_LA05_P - -set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports adc_oen] ; ## C11 FMC1_HPC_LA06_N -set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports adc_sela] ; ## G12 FMC1_HPC_LA08_P -set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports adc_selb] ; ## G13 FMC1_HPC_LA08_N -set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports adc_s0] ; ## H13 FMC1_HPC_LA07_P -set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports adc_s1] ; ## H14 FMC1_HPC_LA07_N -set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports adc_resetb] ; ## C10 FMC1_HPC_LA06_P -set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports adc_agc1] ; ## H07 FMC1_HPC_LA02_P -set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports adc_agc2] ; ## H08 FMC1_HPC_LA02_N -set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports adc_agc3] ; ## G09 FMC1_HPC_LA03_P -set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4] ; ## G10 FMC1_HPC_LA03_N - -# clocks - -create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl deleted file mode 100644 index 595fcf4aa5f..00000000000 --- a/projects/ad6676evb/vc707/system_project.tcl +++ /dev/null @@ -1,35 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -# get_env_param retrieves parameter value from the environment if exists, -# other case use the default value -# -# Use over-writable parameters from the environment. -# -# e.g. -# make RX_JESD_L=1 -# make RX_JESD_L=2 - -# Parameter description: -# RX_JESD_L : Number of lanes per link - -adi_project ad6676evb_vc707 0 [list \ - RX_JESD_L [get_env_param RX_JESD_L 2 ] \ -] - -adi_project_files ad6676evb_vc707 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/library/common/ad_sysref_gen.v" \ - "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] - -adi_project_run ad6676evb_vc707 - - diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v deleted file mode 100644 index ea739f4b42d..00000000000 --- a/projects/ad6676evb/vc707/system_top.v +++ /dev/null @@ -1,246 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - input uart_sin, - output uart_sout, - - output ddr3_reset_n, - output [13:0] ddr3_addr, - output [ 2:0] ddr3_ba, - output ddr3_cas_n, - output ddr3_ras_n, - output ddr3_we_n, - output [ 0:0] ddr3_ck_n, - output [ 0:0] ddr3_ck_p, - output [ 0:0] ddr3_cke, - output [ 0:0] ddr3_cs_n, - output [ 7:0] ddr3_dm, - inout [63:0] ddr3_dq, - inout [ 7:0] ddr3_dqs_n, - inout [ 7:0] ddr3_dqs_p, - output [ 0:0] ddr3_odt, - - input sgmii_rxp, - input sgmii_rxn, - output sgmii_txp, - output sgmii_txn, - - output phy_rstn, - input mgt_clk_p, - input mgt_clk_n, - output mdio_mdc, - inout mdio_mdio, - - output [26:1] linear_flash_addr, - output linear_flash_adv_ldn, - output linear_flash_ce_n, - inout [15:0] linear_flash_dq_io, - output linear_flash_oen, - output linear_flash_wen, - - output fan_pwm, - - inout [ 6:0] gpio_lcd, - inout [20:0] gpio_bd, - - output iic_rstn, - inout iic_scl, - inout iic_sda, - - input rx_ref_clk_p, - input rx_ref_clk_n, - output rx_sysref_p, - output rx_sysref_n, - output rx_sync_p, - output rx_sync_n, - input [ 1:0] rx_data_p, - input [ 1:0] rx_data_n, - - inout adc_oen, - inout adc_sela, - inout adc_selb, - inout adc_s0, - inout adc_s1, - inout adc_resetb, - inout adc_agc1, - inout adc_agc2, - inout adc_agc3, - inout adc_agc4, - - output spi_csn, - output spi_clk, - output spi_mosi, - input spi_miso -); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 6:0] spi_csn_open; - wire rx_ref_clk; - wire rx_sysref; - wire rx_sync; - wire rx_clk; - - // default logic - - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - - assign gpio_i[63:42]= gpio_o[63:42]; - assign gpio_i[31:21]= gpio_o[31:21]; - - // instantiations - - IBUFDS_GTE2 i_ibufds_rx_ref_clk ( - .CEB (1'd0), - .I (rx_ref_clk_p), - .IB (rx_ref_clk_n), - .O (rx_ref_clk), - .ODIV2 ()); - - OBUFDS i_obufds_rx_sysref ( - .I (rx_sysref), - .O (rx_sysref_p), - .OB (rx_sysref_n)); - - OBUFDS i_obufds_rx_sync ( - .I (rx_sync), - .O (rx_sync_p), - .OB (rx_sync_n)); - - ad_iobuf #( - .DATA_WIDTH(10) - ) i_iobuf ( - .dio_t (gpio_t[41:32]), - .dio_i (gpio_o[41:32]), - .dio_o (gpio_i[41:32]), - .dio_p ({ adc_oen, - adc_sela, - adc_selb, - adc_s0, - adc_s1, - adc_resetb, - adc_agc1, - adc_agc2, - adc_agc3, - adc_agc4})); - - ad_iobuf #( - .DATA_WIDTH(21) - ) i_iobuf_bd ( - .dio_t (gpio_t[20:0]), - .dio_i (gpio_o[20:0]), - .dio_o (gpio_i[20:0]), - .dio_p (gpio_bd)); - - ad_sysref_gen i_sysref ( - .core_clk (rx_clk), - .sysref_en (gpio_o[48]), - .sysref_out (rx_sysref)); - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .gpio0_i (gpio_i[31:0]), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio1_i (gpio_i[63:32]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio_lcd_tri_io (gpio_lcd), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .linear_flash_addr (linear_flash_addr), - .linear_flash_adv_ldn (linear_flash_adv_ldn), - .linear_flash_ce_n (linear_flash_ce_n), - .linear_flash_dq_io (linear_flash_dq_io), - .linear_flash_oen (linear_flash_oen), - .linear_flash_wen (linear_flash_wen), - .mdio_mdc (mdio_mdc), - .mdio_mdio_io (mdio_mdio), - .mgt_clk_clk_n (mgt_clk_n), - .mgt_clk_clk_p (mgt_clk_p), - .phy_rstn (phy_rstn), - .phy_sd (1'b1), - .rx_data_0_n (rx_data_n[0]), - .rx_data_0_p (rx_data_p[0]), - .rx_data_1_n (rx_data_n[1]), - .rx_data_1_p (rx_data_p[1]), - .rx_ref_clk_0 (rx_ref_clk), - .rx_sync_0 (rx_sync), - .rx_sysref_0 (rx_sysref), - .rx_core_clk (rx_clk), - .sgmii_rxn (sgmii_rxn), - .sgmii_rxp (sgmii_rxp), - .sgmii_txn (sgmii_txn), - .sgmii_txp (sgmii_txp), - .spi_clk_i (spi_clk), - .spi_clk_o (spi_clk), - .spi_csn_i ({spi_csn_open, spi_csn}), - .spi_csn_o ({spi_csn_open, spi_csn}), - .spi_sdi_i (spi_miso), - .spi_sdo_i (spi_mosi), - .spi_sdo_o (spi_mosi), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .uart_sin (uart_sin), - .uart_sout (uart_sout)); - -endmodule diff --git a/projects/common/vc707/Makefile b/projects/common/vc707/Makefile deleted file mode 100755 index e3dee714596..00000000000 --- a/projects/common/vc707/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := template_vc707 - -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/vc707/vc707_system_mig.prj -M_DEPS += ../../common/vc707/vc707_system_constr.xdc -M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v - -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom - -include ../../scripts/project-xilinx.mk diff --git a/projects/common/vc707/system_bd.tcl b/projects/common/vc707/system_bd.tcl deleted file mode 100755 index dd43df543a2..00000000000 --- a/projects/common/vc707/system_bd.tcl +++ /dev/null @@ -1,14 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source $ad_hdl_dir/projects/scripts/adi_pd.tcl -source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl - -#system ID -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 - -sysid_gen_sys_init_file diff --git a/projects/common/vc707/system_project.tcl b/projects/common/vc707/system_project.tcl deleted file mode 100755 index 0c3999452c4..00000000000 --- a/projects/common/vc707/system_project.tcl +++ /dev/null @@ -1,16 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project template_vc707 -adi_project_files template_vc707 [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" \ - "system_top.v" ] - -adi_project_run template_vc707 diff --git a/projects/common/vc707/system_top.v b/projects/common/vc707/system_top.v deleted file mode 100755 index cd4e48374e1..00000000000 --- a/projects/common/vc707/system_top.v +++ /dev/null @@ -1,173 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - input uart_sin, - output uart_sout, - - output [13:0] ddr3_addr, - output [ 2:0] ddr3_ba, - output ddr3_cas_n, - output ddr3_ck_n, - output ddr3_ck_p, - output ddr3_cke, - output ddr3_cs_n, - output [ 7:0] ddr3_dm, - inout [63:0] ddr3_dq, - inout [ 7:0] ddr3_dqs_n, - inout [ 7:0] ddr3_dqs_p, - output ddr3_odt, - output ddr3_ras_n, - output ddr3_reset_n, - output ddr3_we_n, - - output [26:1] linear_flash_addr, - output linear_flash_adv_ldn, - output linear_flash_ce_n, - output linear_flash_oen, - output linear_flash_wen, - inout [15:0] linear_flash_dq_io, - - input sgmii_rxp, - input sgmii_rxn, - output sgmii_txp, - output sgmii_txn, - - output phy_rstn, - input mgt_clk_p, - input mgt_clk_n, - output mdio_mdc, - inout mdio_mdio, - - output fan_pwm, - - inout [ 6:0] gpio_lcd, - inout [20:0] gpio_bd, - - output iic_rstn, - inout iic_scl, - inout iic_sda -); - - // internal signals - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - assign gpio_i[63:32] = gpio_o[63:32]; - assign gpio_i[31:21] = gpio_o[31:21]; - - // default logic - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - - // instantiations - ad_iobuf #( - .DATA_WIDTH (21) - ) i_iobuf_bd ( - .dio_t (gpio_t[20:0]), - .dio_i (gpio_o[20:0]), - .dio_o (gpio_i[20:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - - .linear_flash_addr (linear_flash_addr), - .linear_flash_adv_ldn (linear_flash_adv_ldn), - .linear_flash_ce_n (linear_flash_ce_n), - .linear_flash_oen (linear_flash_oen), - .linear_flash_wen (linear_flash_wen), - .linear_flash_dq_io (linear_flash_dq_io), - - .gpio_lcd_tri_io (gpio_lcd), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio0_i (gpio_i[31:0]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio1_i (gpio_i[63:32]), - - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - - .mdio_mdc (mdio_mdc), - .mdio_mdio_io (mdio_mdio), - .mgt_clk_clk_n (mgt_clk_n), - .mgt_clk_clk_p (mgt_clk_p), - .phy_rstn (phy_rstn), - .phy_sd (1'b1), - .sgmii_rxn (sgmii_rxn), - .sgmii_rxp (sgmii_rxp), - .sgmii_txn (sgmii_txn), - .sgmii_txp (sgmii_txp), - - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - - .spi_clk_i (), - .spi_clk_o (), - .spi_csn_i (1'b1), - .spi_csn_o (), - .spi_sdi_i (1'b0), - .spi_sdo_i (1'b0), - .spi_sdo_o (), - - .uart_sin (uart_sin), - .uart_sout (uart_sout)); - -endmodule diff --git a/projects/common/vc707/vc707_fmc1_hpc.txt b/projects/common/vc707/vc707_fmc1_hpc.txt deleted file mode 100755 index 32981fa26b8..00000000000 --- a/projects/common/vc707/vc707_fmc1_hpc.txt +++ /dev/null @@ -1,220 +0,0 @@ -FMC_pin FMC_port_name FPGA_pin FPGA_port_name Comments - -H4 FMC1_CLK0_M2C_P L39 IO_L13P_T2_MRCC_19 - -H5 FMC1_CLK0_M2C_N L40 IO_L13N_T2_MRCC_19 - -G2 FMC1_CLK1_M2C_P N30 IO_L13P_T2_MRCC_34 - -G3 FMC1_CLK1_M2C_N M31 IO_L13N_T2_MRCC_34 - -B1 CLK_DIR #N/A #N/A - -K4 CLK2_IO_P #N/A #N/A - -K5 CLK2_IO_N #N/A #N/A - -J2 CLK3_IO_P #N/A #N/A - -J3 CLK3_IO_N #N/A #N/A - -G6 FMC1_LA00_CC_P K39 IO_L12P_T1_MRCC_19 - -G7 FMC1_LA00_CC_N K40 IO_L12N_T1_MRCC_19 - -D8 FMC1_LA01_CC_P J40 IO_L11P_T1_SRCC_19 - -D9 FMC1_LA01_CC_N J41 IO_L11N_T1_SRCC_19 - -H7 FMC1_LA02_P P41 IO_L19P_T3_19 - -H8 FMC1_LA02_N N41 IO_L19N_T3_VREF_19 - -G9 FMC1_LA03_P M42 IO_L16P_T2_19 - -G10 FMC1_LA03_N L42 IO_L16N_T2_19 - -H10 FMC1_LA04_P H40 IO_L7P_T1_19 - -H11 FMC1_LA04_N H41 IO_L7N_T1_19 - -D11 FMC1_LA05_P M41 IO_L14P_T2_SRCC_19 - -D12 FMC1_LA05_N L41 IO_L14N_T2_SRCC_19 - -C10 FMC1_LA06_P K42 IO_L15P_T2_DQS_19 - -C11 FMC1_LA06_N J42 IO_L15N_T2_DQS_19 - -H13 FMC1_LA07_P G41 IO_L9P_T1_DQS_19 - -H14 FMC1_LA07_N G42 IO_L9N_T1_DQS_19 - -G12 FMC1_LA08_P M37 IO_L20P_T3_19 - -G13 FMC1_LA08_N M38 IO_L20N_T3_19 - -D14 FMC1_LA09_P R42 IO_L21P_T3_DQS_19 - -D15 FMC1_LA09_N P42 IO_L21N_T3_DQS_19 - -C14 FMC1_LA10_P N38 IO_L22P_T3_19 - -C15 FMC1_LA10_N M39 IO_L22N_T3_19 - -H16 FMC1_LA11_P F40 IO_L10P_T1_19 - -H17 FMC1_LA11_N F41 IO_L10N_T1_19 - -G15 FMC1_LA12_P R40 IO_L23P_T3_19 - -G16 FMC1_LA12_N P40 IO_L23N_T3_19 - -D17 FMC1_LA13_P H39 IO_L8P_T1_19 - -D18 FMC1_LA13_N G39 IO_L8N_T1_19 - -C18 FMC1_LA14_P N39 IO_L24P_T3_19 - -C19 FMC1_LA14_N N40 IO_L24N_T3_19 - -H19 FMC1_LA15_P M36 IO_L18P_T2_19 - -H20 FMC1_LA15_N L37 IO_L18N_T2_19 - -G18 FMC1_LA16_P K37 IO_L17P_T2_19 - -G19 FMC1_LA16_N K38 IO_L17N_T2_19 - -D20 FMC1_LA17_CC_P L31 IO_L12P_T1_MRCC_34 - -D21 FMC1_LA17_CC_N K32 IO_L12N_T1_MRCC_34 - -C22 FMC1_LA18_CC_P M32 IO_L11P_T1_SRCC_34 - -C23 FMC1_LA18_CC_N L32 IO_L11N_T1_SRCC_34 - -H22 FMC1_LA19_P W30 IO_L22P_T3_34 - -H23 FMC1_LA19_N W31 IO_L22N_T3_34 - -G21 FMC1_LA20_P Y29 IO_L24P_T3_34 - -G22 FMC1_LA20_N Y30 IO_L24N_T3_34 - -H25 FMC1_LA21_P N28 IO_L17P_T2_34 - -H26 FMC1_LA21_N N29 IO_L17N_T2_34 - -G24 FMC1_LA22_P R28 IO_L16P_T2_34 - -G25 FMC1_LA22_N P28 IO_L16N_T2_34 - -D23 FMC1_LA23_P P30 IO_L14P_T2_SRCC_34 - -D24 FMC1_LA23_N N31 IO_L14N_T2_SRCC_34 - -H28 FMC1_LA24_P R30 IO_L18P_T2_34 - -H29 FMC1_LA24_N P31 IO_L18N_T2_34 - -G27 FMC1_LA25_P K29 IO_L7P_T1_34 - -G28 FMC1_LA25_N K30 IO_L7N_T1_34 - -D26 FMC1_LA26_P J30 IO_L8P_T1_34 - -D27 FMC1_LA26_N H30 IO_L8N_T1_34 - -C26 FMC1_LA27_P J31 IO_L10P_T1_34 - -C27 FMC1_LA27_N H31 IO_L10N_T1_34 - -H31 FMC1_LA28_P L29 IO_L9P_T1_DQS_34 - -H32 FMC1_LA28_N L30 IO_L9N_T1_DQS_34 - -G30 FMC1_LA29_P T29 IO_L21P_T3_DQS_34 - -G31 FMC1_LA29_N T30 IO_L21N_T3_DQS_34 - -H34 FMC1_LA30_P V30 IO_L20P_T3_34 - -H35 FMC1_LA30_N V31 IO_L20N_T3_34 - -G33 FMC1_LA31_P M28 IO_L15P_T2_DQS_34 - -G34 FMC1_LA31_N M29 IO_L15N_T2_DQS_34 - -H37 FMC1_LA32_P V29 IO_L23P_T3_34 - -H38 FMC1_LA32_N U29 IO_L23N_T3_34 - -G36 FMC1_LA33_P U31 IO_L19P_T3_34 - -G37 FMC1_LA33_N T31 IO_L19N_T3_VREF_34 - -F4 FMC1_HA00_CC_P E34 IO_L13P_T2_MRCC_35 - -F5 FMC1_HA00_CC_N E35 IO_L13N_T2_MRCC_35 - -E2 FMC1_HA01_CC_P D35 IO_L11P_T1_SRCC_35 - -E3 FMC1_HA01_CC_N D36 IO_L11N_T1_SRCC_35 - -K7 FMC1_HA02_P E33 IO_L9P_T1_DQS_AD7P_35 - -K8 FMC1_HA02_N D33 IO_L9N_T1_DQS_AD7N_35 - -J6 FMC1_HA03_P H33 IO_L18P_T2_35 - -J7 FMC1_HA03_N G33 IO_L18N_T2_35 - -F7 FMC1_HA04_P F34 IO_L17P_T2_35 - -F8 FMC1_HA04_N F35 IO_L17N_T2_35 - -E6 FMC1_HA05_P G32 IO_L15P_T2_DQS_35 - -E7 FMC1_HA05_N F32 IO_L15N_T2_DQS_35 - -K10 FMC1_HA06_P G36 IO_L20P_T3_35 - -K11 FMC1_HA06_N G37 IO_L20N_T3_35 - -J9 FMC1_HA07_P C38 IO_L5P_T0_AD13P_35 - -J10 FMC1_HA07_N C39 IO_L5N_T0_AD13N_35 - -F10 FMC1_HA08_P J36 IO_L24P_T3_35 - -F11 FMC1_HA08_N H36 IO_L24N_T3_35 - -E9 FMC1_HA09_P E32 IO_L7P_T1_AD6P_35 - -E10 FMC1_HA09_N D32 IO_L7N_T1_AD6N_35 - -K13 FMC1_HA10_P H38 IO_L23P_T3_35 - -K14 FMC1_HA10_N G38 IO_L23N_T3_35 - -J12 FMC1_HA11_P J37 IO_L22P_T3_35 - -J13 FMC1_HA11_N J38 IO_L22N_T3_35 - -F13 FMC1_HA12_P B37 IO_L6P_T0_35 - -F14 FMC1_HA12_N B38 IO_L6N_T0_VREF_35 - -E12 FMC1_HA13_P B36 IO_L1P_T0_AD4P_35 - -E13 FMC1_HA13_N A37 IO_L1N_T0_AD4N_35 - -J15 FMC1_HA14_P E37 IO_L19P_T3_35 - -J16 FMC1_HA14_N E38 IO_L19N_T3_VREF_35 - -F16 FMC1_HA15_P C33 IO_L10P_T1_AD15P_35 - -F17 FMC1_HA15_N C34 IO_L10N_T1_AD15N_35 - -E15 FMC1_HA16_P B39 IO_L3P_T0_DQS_AD5P_35 - -E16 FMC1_HA16_N A39 IO_L3N_T0_DQS_AD5N_35 - -K16 FMC1_HA17_CC_P C35 IO_L12P_T1_MRCC_35 - -K17 FMC1_HA17_CC_N C36 IO_L12N_T1_MRCC_35 - -J18 FMC1_HA18_P F39 IO_L21P_T3_DQS_35 - -J19 FMC1_HA18_N E39 IO_L21N_T3_DQS_35 - -F19 FMC1_HA19_P B32 IO_L8P_T1_AD14P_35 - -F20 FMC1_HA19_N B33 IO_L8N_T1_AD14N_35 - -E18 FMC1_HA20_P B34 IO_L2P_T0_AD12P_35 - -E19 FMC1_HA20_N A34 IO_L2N_T0_AD12N_35 - -K19 FMC1_HA21_P D37 IO_L14P_T2_SRCC_35 - -K20 FMC1_HA21_N D38 IO_L14N_T2_SRCC_35 - -J21 FMC1_HA22_P F36 IO_L16P_T2_35 - -J22 FMC1_HA22_N F37 IO_L16N_T2_35 - -K22 FMC1_HA23_P A35 IO_L4P_T0_35 - -K23 FMC1_HA23_N A36 IO_L4N_T0_35 - -K25 FMC1_HB00_CC_P J25 IO_L12P_T1_MRCC_36 - -K26 FMC1_HB00_CC_N J26 IO_L12N_T1_MRCC_36 - -J24 FMC1_HB01_P H28 IO_L9P_T1_DQS_36 - -J25 FMC1_HB01_N H29 IO_L9N_T1_DQS_36 - -F22 FMC1_HB02_P K28 IO_L8P_T1_36 - -F23 FMC1_HB02_N J28 IO_L8N_T1_36 - -E21 FMC1_HB03_P G28 IO_L7P_T1_36 - -E22 FMC1_HB03_N G29 IO_L7N_T1_36 - -F25 FMC1_HB04_P H24 IO_L1P_T0_36 - -F26 FMC1_HB04_N G24 IO_L1N_T0_36 - -E24 FMC1_HB05_P K27 IO_L10P_T1_36 - -E25 FMC1_HB05_N J27 IO_L10N_T1_36 - -K28 FMC1_HB06_CC_P K23 IO_L14P_T2_SRCC_36 - -K29 FMC1_HB06_CC_N J23 IO_L14N_T2_SRCC_36 - -J27 FMC1_HB07_P G26 IO_L5P_T0_36 - -J28 FMC1_HB07_N G27 IO_L5N_T0_36 - -F28 FMC1_HB08_P H25 IO_L3P_T0_DQS_36 - -F29 FMC1_HB08_N H26 IO_L3N_T0_DQS_36 - -E27 FMC1_HB09_P H23 IO_L6P_T0_36 - -E28 FMC1_HB09_N G23 IO_L6N_T0_VREF_36 - -K31 FMC1_HB10_P M22 IO_L15P_T2_DQS_36 - -K32 FMC1_HB10_N L22 IO_L15N_T2_DQS_36 - -J30 FMC1_HB11_P K22 IO_L17P_T2_36 - -J31 FMC1_HB11_N J22 IO_L17N_T2_36 - -F31 FMC1_HB12_P K24 IO_L11P_T1_SRCC_36 - -F32 FMC1_HB12_N K25 IO_L11N_T1_SRCC_36 - -E30 FMC1_HB13_P P25 IO_L20P_T3_36 - -E31 FMC1_HB13_N P26 IO_L20N_T3_36 - -K34 FMC1_HB14_P J21 IO_L2P_T0_36 - -K35 FMC1_HB14_N H21 IO_L2N_T0_36 - -J33 FMC1_HB15_P M21 IO_L18P_T2_36 - -J34 FMC1_HB15_N L21 IO_L18N_T2_36 - -F34 FMC1_HB16_P N25 IO_L22P_T3_36 - -F35 FMC1_HB16_N N26 IO_L22N_T3_36 - -K37 FMC1_HB17_CC_P M24 IO_L13P_T2_MRCC_36 - -K38 FMC1_HB17_CC_N L24 IO_L13N_T2_MRCC_36 - -J36 FMC1_HB18_P G21 IO_L4P_T0_36 - -J37 FMC1_HB18_N G22 IO_L4N_T0_36 - -E33 FMC1_HB19_P L25 IO_L16P_T2_36 - -E34 FMC1_HB19_N L26 IO_L16N_T2_36 - -F37 FMC1_HB20_P P21 IO_L19P_T3_36 - -F38 FMC1_HB20_N N21 IO_L19N_T3_VREF_36 - -E36 FMC1_HB21_P P22 IO_L21P_T3_DQS_36 - -E37 FMC1_HB21_N P23 IO_L21N_T3_DQS_36 - -D4 FMC1_GBTCLK0_M2C_P A10 MGTREFCLK0P_119 - -D5 FMC1_GBTCLK0_M2C_N A9 MGTREFCLK0N_119 - -B20 FMC1_GBTCLK1_M2C_P E10 MGTREFCLK0P_118 - -B21 FMC1_GBTCLK1_M2C_N E9 MGTREFCLK0N_118 - -C2 FMC1_DP0_C2M_P E2 MGTXTXP0_119 - -C3 FMC1_DP0_C2M_N E1 MGTXTXN0_119 - -C6 FMC1_DP0_M2C_P D8 MGTXRXP0_119 - -C7 FMC1_DP0_M2C_N D7 MGTXRXN0_119 - -A22 FMC1_DP1_C2M_P D4 MGTXTXP1_119 - -A23 FMC1_DP1_C2M_N D3 MGTXTXN1_119 - -A2 FMC1_DP1_M2C_P C6 MGTXRXP1_119 - -A3 FMC1_DP1_M2C_N C5 MGTXRXN1_119 - -A26 FMC1_DP2_C2M_P C2 MGTXTXP2_119 - -A27 FMC1_DP2_C2M_N C1 MGTXTXN2_119 - -A6 FMC1_DP2_M2C_P B8 MGTXRXP2_119 - -A7 FMC1_DP2_M2C_N B7 MGTXRXN2_119 - -A30 FMC1_DP3_C2M_P B4 MGTXTXP3_119 - -A31 FMC1_DP3_C2M_N B3 MGTXTXN3_119 - -A10 FMC1_DP3_M2C_P A6 MGTXRXP3_119 - -A11 FMC1_DP3_M2C_N A5 MGTXRXN3_119 - -A34 FMC1_DP4_C2M_P J2 MGTXTXP0_118 - -A35 FMC1_DP4_C2M_N J1 MGTXTXN0_118 - -A14 FMC1_DP4_M2C_P H8 MGTXRXP0_118 - -A15 FMC1_DP4_M2C_N H7 MGTXRXN0_118 - -A38 FMC1_DP5_C2M_P H4 MGTXTXP1_118 - -A39 FMC1_DP5_C2M_N H3 MGTXTXN1_118 - -A18 FMC1_DP5_M2C_P G6 MGTXRXP1_118 - -A19 FMC1_DP5_M2C_N G5 MGTXRXN1_118 - -B36 FMC1_DP6_C2M_P G2 MGTXTXP2_118 - -B37 FMC1_DP6_C2M_N G1 MGTXTXN2_118 - -B16 FMC1_DP6_M2C_P F8 MGTXRXP2_118 - -B17 FMC1_DP6_M2C_N F7 MGTXRXN2_118 - -B32 FMC1_DP7_C2M_P F4 MGTXTXP3_118 - -B33 FMC1_DP7_C2M_N F3 MGTXTXN3_118 - -B12 FMC1_DP7_M2C_P E6 MGTXRXP3_118 - -B13 FMC1_DP7_M2C_N E5 MGTXRXN3_118 - -B28 FMC1_DP8_C2M_P #N/A #N/A - -B29 FMC1_DP8_C2M_N #N/A #N/A - -B8 FMC1_DP8_M2C_P #N/A #N/A - -B9 FMC1_DP8_M2C_N #N/A #N/A - -B24 FMC1_DP9_C2M_P #N/A #N/A - -B25 FMC1_DP9_C2M_N #N/A #N/A - -B4 FMC1_DP9_M2C_P #N/A #N/A - -B5 FMC1_DP9_M2C_N #N/A #N/A - -C30 FMC1_SCL #N/A #N/A - -C31 FMC1_SDA #N/A #N/A - -D1 PG_C2M #N/A #N/A - -F1 FMC1_PG_M2C AN34 IO_L15N_T2_DQS_DOUT_CSO_B_14 - -H2 FMC1_PRSNT_M2C_L AM31 IO_L16P_T2_CSI_B_14 - \ No newline at end of file diff --git a/projects/common/vc707/vc707_fmc2_hpc.txt b/projects/common/vc707/vc707_fmc2_hpc.txt deleted file mode 100755 index 4390919bcfd..00000000000 --- a/projects/common/vc707/vc707_fmc2_hpc.txt +++ /dev/null @@ -1,220 +0,0 @@ -FMC_pin FMC_port_name FPGA_pin FPGA_port_name Comments - -H4 FMC2_CLK0_M2C_P AF39 IO_L13P_T2_MRCC_17 - -H5 FMC2_CLK0_M2C_N AF40 IO_L13N_T2_MRCC_17 - -G2 FMC2_CLK1_M2C_P U39 IO_L12P_T1_MRCC_18 - -G3 FMC2_CLK1_M2C_N T39 IO_L12N_T1_MRCC_18 - -B1 CLK_DIR #N/A #N/A - -K4 CLK2_IO_P #N/A #N/A - -K5 CLK2_IO_N #N/A #N/A - -J2 CLK3_IO_P #N/A #N/A - -J3 CLK3_IO_N #N/A #N/A - -G6 FMC2_LA00_CC_P AD40 IO_L12P_T1_MRCC_17 - -G7 FMC2_LA00_CC_N AD41 IO_L12N_T1_MRCC_17 - -D8 FMC2_LA01_CC_P AF41 IO_L14P_T2_SRCC_17 - -D9 FMC2_LA01_CC_N AG41 IO_L14N_T2_SRCC_17 - -H7 FMC2_LA02_P AK39 IO_L23P_T3_17 - -H8 FMC2_LA02_N AL39 IO_L23N_T3_17 - -G9 FMC2_LA03_P AJ42 IO_L24P_T3_17 - -G10 FMC2_LA03_N AK42 IO_L24N_T3_17 - -H10 FMC2_LA04_P AL41 IO_L21P_T3_DQS_17 - -H11 FMC2_LA04_N AL42 IO_L21N_T3_DQS_17 - -D11 FMC2_LA05_P AF42 IO_L16P_T2_17 - -D12 FMC2_LA05_N AG42 IO_L16N_T2_17 - -C10 FMC2_LA06_P AD38 IO_L9P_T1_DQS_17 - -C11 FMC2_LA06_N AE38 IO_L9N_T1_DQS_17 - -H13 FMC2_LA07_P AC40 IO_L10P_T1_17 - -H14 FMC2_LA07_N AC41 IO_L10N_T1_17 - -G12 FMC2_LA08_P AD42 IO_L8P_T1_17 - -G13 FMC2_LA08_N AE42 IO_L8N_T1_17 - -D14 FMC2_LA09_P AJ38 IO_L18P_T2_17 - -D15 FMC2_LA09_N AK38 IO_L18N_T2_17 - -C14 FMC2_LA10_P AB41 IO_L1P_T0_17 - -C15 FMC2_LA10_N AB42 IO_L1N_T0_17 - -H16 FMC2_LA11_P Y42 IO_L4P_T0_17 - -H17 FMC2_LA11_N AA42 IO_L4N_T0_17 - -G15 FMC2_LA12_P Y39 IO_L3P_T0_DQS_17 - -G16 FMC2_LA12_N AA39 IO_L3N_T0_DQS_17 - -D17 FMC2_LA13_P W40 IO_L2P_T0_17 - -D18 FMC2_LA13_N Y40 IO_L2N_T0_17 - -C18 FMC2_LA14_P AB38 IO_L5P_T0_17 - -C19 FMC2_LA14_N AB39 IO_L5N_T0_17 - -H19 FMC2_LA15_P AC38 IO_L7P_T1_17 - -H20 FMC2_LA15_N AC39 IO_L7N_T1_17 - -G18 FMC2_LA16_P AJ40 IO_L22P_T3_17 - -G19 FMC2_LA16_N AJ41 IO_L22N_T3_17 - -D20 FMC2_LA17_CC_P U37 IO_L11P_T1_SRCC_18 - -D21 FMC2_LA17_CC_N U38 IO_L11N_T1_SRCC_18 - -C22 FMC2_LA18_CC_P U36 IO_L13P_T2_MRCC_18 - -C23 FMC2_LA18_CC_N T37 IO_L13N_T2_MRCC_18 - -H22 FMC2_LA19_P U32 IO_L17P_T2_18 - -H23 FMC2_LA19_N U33 IO_L17N_T2_18 - -G21 FMC2_LA20_P V33 IO_L15P_T2_DQS_18 - -G22 FMC2_LA20_N V34 IO_L15N_T2_DQS_18 - -H25 FMC2_LA21_P P35 IO_L4P_T0_18 - -H26 FMC2_LA21_N P36 IO_L4N_T0_18 - -G24 FMC2_LA22_P W32 IO_L18P_T2_18 - -G25 FMC2_LA22_N W33 IO_L18N_T2_18 - -D23 FMC2_LA23_P R38 IO_L10P_T1_18 - -D24 FMC2_LA23_N R39 IO_L10N_T1_18 - -H28 FMC2_LA24_P U34 IO_L9P_T1_DQS_18 - -H29 FMC2_LA24_N T35 IO_L9N_T1_DQS_18 - -G27 FMC2_LA25_P R33 IO_L3P_T0_DQS_18 - -G28 FMC2_LA25_N R34 IO_L3N_T0_DQS_18 - -D26 FMC2_LA26_P N33 IO_L2P_T0_18 - -D27 FMC2_LA26_N N34 IO_L2N_T0_18 - -C26 FMC2_LA27_P P32 IO_L6P_T0_18 - -C27 FMC2_LA27_N P33 IO_L6N_T0_VREF_18 - -H31 FMC2_LA28_P V35 IO_L14P_T2_SRCC_18 - -H32 FMC2_LA28_N V36 IO_L14N_T2_SRCC_18 - -G30 FMC2_LA29_P W36 IO_L16P_T2_18 - -G31 FMC2_LA29_N W37 IO_L16N_T2_18 - -H34 FMC2_LA30_P T32 IO_L5P_T0_18 - -H35 FMC2_LA30_N R32 IO_L5N_T0_18 - -G33 FMC2_LA31_P V39 IO_L19P_T3_18 - -G34 FMC2_LA31_N V40 IO_L19N_T3_VREF_18 - -H37 FMC2_LA32_P P37 IO_L8P_T1_18 - -H38 FMC2_LA32_N P38 IO_L8N_T1_18 - -G36 FMC2_LA33_P T36 IO_L7P_T1_18 - -G37 FMC2_LA33_N R37 IO_L7N_T1_18 - -F4 FMC2_HA00_CC_P AB33 IO_L12P_T1_MRCC_16 - -F5 FMC2_HA00_CC_N AC33 IO_L12N_T1_MRCC_16 - -E2 FMC2_HA01_CC_P AD32 IO_L13P_T2_MRCC_16 - -E3 FMC2_HA01_CC_N AD33 IO_L13N_T2_MRCC_16 - -K7 FMC2_HA02_P AC30 IO_L22P_T3_16 - -K8 FMC2_HA02_N AD30 IO_L22N_T3_16 - -J6 FMC2_HA03_P AA29 IO_L23P_T3_16 - -J7 FMC2_HA03_N AA30 IO_L23N_T3_16 - -F7 FMC2_HA04_P AB29 IO_L24P_T3_16 - -F8 FMC2_HA04_N AC29 IO_L24N_T3_16 - -E6 FMC2_HA05_P Y32 IO_L19P_T3_16 - -E7 FMC2_HA05_N Y33 IO_L19N_T3_VREF_16 - -K10 FMC2_HA06_P AB31 IO_L11P_T1_SRCC_16 - -K11 FMC2_HA06_N AB32 IO_L11N_T1_SRCC_16 - -J9 FMC2_HA07_P AC31 IO_L20P_T3_16 - -J10 FMC2_HA07_N AD31 IO_L20N_T3_16 - -F10 FMC2_HA08_P AA31 IO_L21P_T3_DQS_16 - -F11 FMC2_HA08_N AA32 IO_L21N_T3_DQS_16 - -E9 FMC2_HA09_P AE29 IO_L18P_T2_16 - -E10 FMC2_HA09_N AE30 IO_L18N_T2_16 - -K13 FMC2_HA10_P AF31 IO_L16P_T2_16 - -K14 FMC2_HA10_N AF32 IO_L16N_T2_16 - -J12 FMC2_HA11_P AE34 IO_L17P_T2_16 - -J13 FMC2_HA11_N AE35 IO_L17N_T2_16 - -F13 FMC2_HA12_P AF34 IO_L3P_T0_DQS_16 - -F14 FMC2_HA12_N AG34 IO_L3N_T0_DQS_16 - -E12 FMC2_HA13_P AE32 IO_L15P_T2_DQS_16 - -E13 FMC2_HA13_N AE33 IO_L15N_T2_DQS_16 - -J15 FMC2_HA14_P AF35 IO_L1P_T0_16 - -J16 FMC2_HA14_N AF36 IO_L1N_T0_16 - -F16 FMC2_HA15_P AE37 IO_L2P_T0_16 - -F17 FMC2_HA15_N AF37 IO_L2N_T0_16 - -E15 FMC2_HA16_P AG36 IO_L6P_T0_16 - -E16 FMC2_HA16_N AH36 IO_L6N_T0_VREF_16 - -K16 FMC2_HA17_CC_P AC34 IO_L14P_T2_SRCC_16 - -K17 FMC2_HA17_CC_N AD35 IO_L14N_T2_SRCC_16 - -J18 FMC2_HA18_P AB36 IO_L9P_T1_DQS_16 - -J19 FMC2_HA18_N AB37 IO_L9N_T1_DQS_16 - -F19 FMC2_HA19_P AC35 IO_L5P_T0_16 - -F20 FMC2_HA19_N AC36 IO_L5N_T0_16 - -E18 FMC2_HA20_P AD36 IO_L4P_T0_16 - -E19 FMC2_HA20_N AD37 IO_L4N_T0_16 - -K19 FMC2_HA21_P AA34 IO_L10P_T1_16 - -K20 FMC2_HA21_N AA35 IO_L10N_T1_16 - -J21 FMC2_HA22_P Y35 IO_L8P_T1_16 - -J22 FMC2_HA22_N AA36 IO_L8N_T1_16 - -K22 FMC2_HA23_P Y37 IO_L7P_T1_16 - -K23 FMC2_HA23_N AA37 IO_L7N_T1_16 - -K25 FMC2_HB00_CC_P AT17 #N/A - -K26 FMC2_HB00_CC_N AU17 #N/A - -J24 FMC2_HB01_P AM16 #N/A - -J25 FMC2_HB01_N AN16 #N/A - -F22 FMC2_HB02_P AV16 #N/A - -F23 FMC2_HB02_N AW16 #N/A - -E21 FMC2_HB03_P AT16 #N/A - -E22 FMC2_HB03_N AU16 #N/A - -F25 FMC2_HB04_P AU18 #N/A - -F26 FMC2_HB04_N AV18 #N/A - -E24 FMC2_HB05_P BA17 #N/A - -E25 FMC2_HB05_N BB17 #N/A - -K28 FMC2_HB06_CC_P AY18 #N/A - -K29 FMC2_HB06_CC_N AY17 #N/A - -J27 FMC2_HB07_P BB19 #N/A - -J28 FMC2_HB07_N BB18 #N/A - -F28 FMC2_HB08_P AY20 #N/A - -F29 FMC2_HB08_N BA20 #N/A - -E27 FMC2_HB09_P AV20 #N/A - -E28 FMC2_HB09_N AW20 #N/A - -K31 FMC2_HB10_P AP20 #N/A - -K32 FMC2_HB10_N AR19 #N/A - -J30 FMC2_HB11_P AM18 #N/A - -J31 FMC2_HB11_N AM17 #N/A - -F31 FMC2_HB12_P AU19 #N/A - -F32 FMC2_HB12_N AV19 #N/A - -E30 FMC2_HB13_P AT20 #N/A - -E31 FMC2_HB13_N AT19 #N/A - -K34 FMC2_HB14_P AK19 #N/A - -K35 FMC2_HB14_N AK18 #N/A - -J33 FMC2_HB15_P AL19 #N/A - -J34 FMC2_HB15_N AM19 #N/A - -F34 FMC2_HB16_P AR18 #N/A - -F35 FMC2_HB16_N AR17 #N/A - -K37 FMC2_HB17_CC_P AW18 #N/A - -K38 FMC2_HB17_CC_N AW17 #N/A - -J36 FMC2_HB18_P AJ18 #N/A - -J37 FMC2_HB18_N AJ17 #N/A - -E33 FMC2_HB19_P AP18 #N/A - -E34 FMC2_HB19_N AP17 #N/A - -F37 FMC2_HB20_P AK17 #N/A - -F38 FMC2_HB20_N AL17 #N/A - -E36 FMC2_HB21_P AN19 #N/A - -E37 FMC2_HB21_N AN18 #N/A - -D4 FMC2_GBTCLK0_M2C_P K8 MGTREFCLK0P_117 - -D5 FMC2_GBTCLK0_M2C_N K7 MGTREFCLK0N_117 - -B20 FMC2_GBTCLK1_M2C_P T8 MGTREFCLK0P_116 - -B21 FMC2_GBTCLK1_M2C_N T7 MGTREFCLK0N_116 - -C2 FMC2_DP0_C2M_P N2 MGTXTXP0_117 - -C3 FMC2_DP0_C2M_N N1 MGTXTXN0_117 - -C6 FMC2_DP0_M2C_P P8 MGTXRXP0_117 - -C7 FMC2_DP0_M2C_N P7 MGTXRXN0_117 - -A22 FMC2_DP1_C2M_P M4 MGTXTXP1_117 - -A23 FMC2_DP1_C2M_N M3 MGTXTXN1_117 - -A2 FMC2_DP1_M2C_P N6 MGTXRXP1_117 - -A3 FMC2_DP1_M2C_N N5 MGTXRXN1_117 - -A26 FMC2_DP2_C2M_P L2 MGTXTXP2_117 - -A27 FMC2_DP2_C2M_N L1 MGTXTXN2_117 - -A6 FMC2_DP2_M2C_P L6 MGTXRXP2_117 - -A7 FMC2_DP2_M2C_N L5 MGTXRXN2_117 - -A30 FMC2_DP3_C2M_P K4 MGTXTXP3_117 - -A31 FMC2_DP3_C2M_N K3 MGTXTXN3_117 - -A10 FMC2_DP3_M2C_P J6 MGTXRXP3_117 - -A11 FMC2_DP3_M2C_N J5 MGTXRXN3_117 - -A34 FMC2_DP4_C2M_P U2 MGTXTXP0_116 - -A35 FMC2_DP4_C2M_N U1 MGTXTXN0_116 - -A14 FMC2_DP4_M2C_P W6 MGTXRXP0_116 - -A15 FMC2_DP4_M2C_N W5 MGTXRXN0_116 - -A38 FMC2_DP5_C2M_P T4 MGTXTXP1_116 - -A39 FMC2_DP5_C2M_N T3 MGTXTXN1_116 - -A18 FMC2_DP5_M2C_P V4 MGTXRXP1_116 - -A19 FMC2_DP5_M2C_N V3 MGTXRXN1_116 - -B36 FMC2_DP6_C2M_P R2 MGTXTXP2_116 - -B37 FMC2_DP6_C2M_N R1 MGTXTXN2_116 - -B16 FMC2_DP6_M2C_P U6 MGTXRXP2_116 - -B17 FMC2_DP6_M2C_N U5 MGTXRXN2_116 - -B32 FMC2_DP7_C2M_P P4 MGTXTXP3_116 - -B33 FMC2_DP7_C2M_N P3 MGTXTXN3_116 - -B12 FMC2_DP7_M2C_P R6 MGTXRXP3_116 - -B13 FMC2_DP7_M2C_N R5 MGTXRXN3_116 - -B28 FMC2_DP8_C2M_P #N/A #N/A - -B29 FMC2_DP8_C2M_N #N/A #N/A - -B8 FMC2_DP8_M2C_P #N/A #N/A - -B9 FMC2_DP8_M2C_N #N/A #N/A - -B24 FMC2_DP9_C2M_P #N/A #N/A - -B25 FMC2_DP9_C2M_N #N/A #N/A - -B4 FMC2_DP9_M2C_P #N/A #N/A - -B5 FMC2_DP9_M2C_N #N/A #N/A - -C30 FMC2_SCL #N/A #N/A - -C31 FMC2_SDA #N/A #N/A - -D1 PG_C2M #N/A #N/A - -F1 FMC2_PG_M2C AF29 IO_L21P_T3_DQS_14 - -H2 FMC2_PRSNT_M2C_L AG32 IO_25_VRP_14 - \ No newline at end of file diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl deleted file mode 100644 index 6bf5f68df28..00000000000 --- a/projects/common/vc707/vc707_system_bd.tcl +++ /dev/null @@ -1,320 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -set CACHE_COHERENCY false - -# create board design -# default ports - -create_bd_port -dir I -type rst sys_rst -create_bd_port -dir I sys_clk_p -create_bd_port -dir I sys_clk_n - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 - -create_bd_port -dir O -type rst phy_rstn -create_bd_port -dir I phy_sd -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:emc_rtl:1.0 linear_flash - -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main - -create_bd_port -dir I uart_sin -create_bd_port -dir O uart_sout - -create_bd_port -dir O -from 7 -to 0 spi_csn_o -create_bd_port -dir I -from 7 -to 0 spi_csn_i -create_bd_port -dir I spi_clk_i -create_bd_port -dir O spi_clk_o -create_bd_port -dir I spi_sdo_i -create_bd_port -dir O spi_sdo_o -create_bd_port -dir I spi_sdi_i - -create_bd_port -dir I -from 31 -to 0 gpio0_i -create_bd_port -dir O -from 31 -to 0 gpio0_o -create_bd_port -dir O -from 31 -to 0 gpio0_t -create_bd_port -dir I -from 31 -to 0 gpio1_i -create_bd_port -dir O -from 31 -to 0 gpio1_o -create_bd_port -dir O -from 31 -to 0 gpio1_t - -set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] - -# instance: microblaze - processor - -ad_ip_instance microblaze sys_mb -ad_ip_parameter sys_mb CONFIG.G_TEMPLATE_LIST 4 -ad_ip_parameter sys_mb CONFIG.C_DCACHE_FORCE_TAG_LUTRAM 1 - -# instance: microblaze - local memory & bus - -ad_ip_instance lmb_v10 sys_dlmb -ad_ip_instance lmb_v10 sys_ilmb - -ad_ip_instance lmb_bram_if_cntlr sys_dlmb_cntlr -ad_ip_parameter sys_dlmb_cntlr CONFIG.C_ECC 0 - -ad_ip_instance lmb_bram_if_cntlr sys_ilmb_cntlr -ad_ip_parameter sys_ilmb_cntlr CONFIG.C_ECC 0 - -ad_ip_instance blk_mem_gen sys_lmb_bram -ad_ip_parameter sys_lmb_bram CONFIG.Memory_Type True_Dual_Port_RAM -ad_ip_parameter sys_lmb_bram CONFIG.use_bram_block BRAM_Controller - -# instance: microblaze- mdm - -ad_ip_instance mdm sys_mb_debug -ad_ip_parameter sys_mb_debug CONFIG.C_USE_UART 1 - -# instance: system reset/clocks - -ad_ip_instance proc_sys_reset sys_rstgen -ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 -ad_ip_instance proc_sys_reset sys_200m_rstgen -ad_ip_parameter sys_200m_rstgen CONFIG.C_EXT_RST_WIDTH 1 - -# instance: ddr (mig) - -ad_ip_instance mig_7series axi_ddr_cntrl -set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]] -file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/" -ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE vc707_system_mig.prj -ad_ip_parameter axi_ddr_cntrl CONFIG.RESET_BOARD_INTERFACE Custom - -# instance: default peripherals - -ad_ip_instance axi_ethernet axi_ethernet -ad_ip_parameter axi_ethernet CONFIG.PHY_TYPE SGMII -ad_ip_parameter axi_ethernet CONFIG.TXCSUM Full -ad_ip_parameter axi_ethernet CONFIG.RXCSUM Full -ad_ip_parameter axi_ethernet CONFIG.TXMEM 8k -ad_ip_parameter axi_ethernet CONFIG.RXMEM 8k - -ad_ip_instance axi_dma axi_ethernet_dma -ad_ip_parameter axi_ethernet_dma CONFIG.c_include_mm2s_dre 1 -ad_ip_parameter axi_ethernet_dma CONFIG.c_sg_use_stsapp_length 1 -ad_ip_parameter axi_ethernet_dma CONFIG.c_include_s2mm_dre 1 - -ad_ip_instance axi_iic axi_iic_main - -ad_ip_instance axi_uartlite axi_uart -ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200 - -ad_ip_instance axi_timer axi_timer - -ad_ip_instance axi_gpio axi_gpio_lcd -ad_ip_parameter axi_gpio_lcd CONFIG.C_GPIO_WIDTH 7 -ad_ip_parameter axi_gpio_lcd CONFIG.C_INTERRUPT_PRESENT 1 - -ad_ip_instance axi_quad_spi axi_spi -ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0 -ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 8 -ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8 - -ad_ip_instance axi_gpio axi_gpio -ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1 -ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32 -ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32 -ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1 - -# instance: interrupt - -ad_ip_instance axi_intc axi_intc -ad_ip_parameter axi_intc CONFIG.C_HAS_FAST 0 - -ad_ip_instance xlconcat sys_concat_intc -ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 - -# linear flash - -ad_ip_instance axi_emc axi_linear_flash -ad_ip_parameter axi_linear_flash CONFIG.USE_BOARD_FLOW true -ad_ip_parameter axi_linear_flash CONFIG.EMC_BOARD_INTERFACE linear_flash -ad_ip_parameter axi_linear_flash CONFIG.C_MEM0_TYPE 2 -ad_ip_parameter axi_linear_flash CONFIG.C_S_AXI_MEM_ID_WIDTH 0 -ad_ip_parameter axi_linear_flash CONFIG.C_THZCE_PS_MEM_0 7000 -ad_ip_parameter axi_linear_flash CONFIG.C_TLZWE_PS_MEM_0 0 -ad_ip_parameter axi_linear_flash CONFIG.C_TWC_PS_MEM_0 15000 -ad_ip_parameter axi_linear_flash CONFIG.C_WR_REC_TIME_MEM_0 0 -ad_ip_parameter axi_linear_flash CONFIG.C_TWP_PS_MEM_0 40000 -ad_ip_parameter axi_linear_flash CONFIG.C_TWPH_PS_MEM_0 20000 -ad_ip_parameter axi_linear_flash CONFIG.C_TPACC_PS_FLASH_0 15000 -ad_ip_parameter axi_linear_flash CONFIG.C_TCEDV_PS_MEM_0 96000 -ad_ip_parameter axi_linear_flash CONFIG.C_TAVDV_PS_MEM_0 96000 - -# connections - -ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst -ad_connect sys_rstgen/mb_reset sys_mb/Reset -ad_connect sys_rstgen/bus_struct_reset sys_dlmb/SYS_Rst -ad_connect sys_rstgen/bus_struct_reset sys_ilmb/SYS_Rst -ad_connect sys_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst -ad_connect sys_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst - -# microblaze local memory - -ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB -ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB -ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA -ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB -ad_connect sys_mb/DLMB sys_dlmb/LMB_M -ad_connect sys_mb/ILMB sys_ilmb/LMB_M - -# system id - -ad_ip_instance axi_sysid axi_sysid_0 -ad_ip_instance sysid_rom rom_sys_0 - -ad_connect axi_sysid_0/rom_addr rom_sys_0/rom_addr -ad_connect axi_sysid_0/sys_rom_data rom_sys_0/rom_data -ad_connect sys_cpu_clk rom_sys_0/clk - -# microblaze debug & interrupt - -ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG -ad_connect axi_intc/interrupt sys_mb/INTERRUPT -ad_connect sys_concat_intc/dout axi_intc/intr - -# defaults (peripherals) - -ad_connect axi_ddr_cntrl/device_temp_i GND -ad_connect axi_ddr_cntrl/mmcm_locked sys_rstgen/dcm_locked -ad_connect axi_ddr_cntrl/mmcm_locked sys_200m_rstgen/dcm_locked - -ad_connect sys_cpu_clk axi_ddr_cntrl/ui_addn_clk_0 -ad_connect sys_200m_clk axi_ddr_cntrl/ui_clk -ad_connect sys_cpu_resetn axi_ddr_cntrl/aresetn -ad_connect sys_cpu_reset sys_rstgen/peripheral_reset -ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn -ad_connect sys_200m_reset sys_200m_rstgen/peripheral_reset -ad_connect sys_200m_resetn sys_200m_rstgen/peripheral_aresetn - -# generic system clocks pointers - -set sys_cpu_clk [get_bd_nets sys_cpu_clk] -set sys_dma_clk [get_bd_nets sys_200m_clk] -set sys_iodelay_clk [get_bd_nets sys_200m_clk] - -set sys_cpu_reset [get_bd_nets sys_cpu_reset] -set sys_cpu_resetn [get_bd_nets sys_cpu_resetn] -set sys_dma_reset [get_bd_nets sys_200m_reset] -set sys_dma_resetn [get_bd_nets sys_200m_resetn] -set sys_iodelay_reset [get_bd_nets sys_200m_reset] -set sys_iodelay_resetn [get_bd_nets sys_200m_resetn] - -ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk -ad_connect sys_200m_clk sys_200m_rstgen/slowest_sync_clk -ad_connect sys_cpu_clk sys_mb/Clk -ad_connect sys_cpu_clk sys_dlmb/LMB_Clk -ad_connect sys_cpu_clk sys_ilmb/LMB_Clk -ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk -ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk -ad_connect sys_cpu_clk axi_spi/ext_spi_clk - -# defaults (interrupts) - -ad_connect sys_concat_intc/In0 axi_timer/interrupt -ad_connect sys_concat_intc/In1 axi_ethernet/interrupt -ad_connect sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut -ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut -ad_connect sys_concat_intc/In4 axi_uart/interrupt -ad_connect sys_concat_intc/In5 axi_gpio_lcd/ip2intc_irpt -ad_connect sys_concat_intc/In6 GND -ad_connect sys_concat_intc/In7 GND -ad_connect sys_concat_intc/In8 GND -ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt -ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt -ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt -ad_connect sys_concat_intc/In12 GND -ad_connect sys_concat_intc/In13 GND -ad_connect sys_concat_intc/In14 GND -ad_connect sys_concat_intc/In15 GND - -# defaults (external interface) - -ad_connect sys_rst sys_rstgen/ext_reset_in -ad_connect sys_rst axi_ddr_cntrl/sys_rst -ad_connect sys_200m_rst sys_200m_rstgen/ext_reset_in -ad_connect sys_200m_rst axi_ddr_cntrl/ui_clk_sync_rst -ad_connect sys_clk_p axi_ddr_cntrl/sys_clk_p -ad_connect sys_clk_n axi_ddr_cntrl/sys_clk_n -ad_connect ddr3 axi_ddr_cntrl/DDR3 -ad_connect sys_200m_clk axi_ethernet/ref_clk -ad_connect sys_cpu_clk axi_ethernet/axis_clk -ad_connect phy_sd axi_ethernet/signal_detect -ad_connect phy_rstn axi_ethernet/phy_rst_n -ad_connect mgt_clk axi_ethernet/mgt_clk -ad_connect mdio axi_ethernet/mdio -ad_connect sgmii axi_ethernet/sgmii -ad_connect sys_cpu_clk axi_ethernet_dma/m_axi_sg_aclk -ad_connect sys_cpu_clk axi_ethernet_dma/m_axi_mm2s_aclk -ad_connect sys_cpu_clk axi_ethernet_dma/m_axi_s2mm_aclk -ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n -ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n -ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n -ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n -ad_connect axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S -ad_connect axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL -ad_connect axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM -ad_connect axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS -ad_connect uart_sin axi_uart/rx -ad_connect uart_sout axi_uart/tx -ad_connect gpio_lcd axi_gpio_lcd/gpio -ad_connect iic_main axi_iic_main/iic - -ad_connect spi_csn_i axi_spi/ss_i -ad_connect spi_csn_o axi_spi/ss_o -ad_connect spi_clk_i axi_spi/sck_i -ad_connect spi_clk_o axi_spi/sck_o -ad_connect spi_sdo_i axi_spi/io0_i -ad_connect spi_sdo_o axi_spi/io0_o -ad_connect spi_sdi_i axi_spi/io1_i -ad_connect gpio0_i axi_gpio/gpio_io_i -ad_connect gpio0_o axi_gpio/gpio_io_o -ad_connect gpio0_t axi_gpio/gpio_io_t -ad_connect gpio1_i axi_gpio/gpio2_io_i -ad_connect gpio1_o axi_gpio/gpio2_io_o -ad_connect gpio1_t axi_gpio/gpio2_io_t - -# linear_flash - -ad_connect axi_linear_flash/EMC_INTF linear_flash - -ad_connect sys_cpu_resetn axi_linear_flash/s_axi_aresetn -ad_connect sys_cpu_clk axi_linear_flash/s_axi_aclk -ad_connect sys_cpu_clk axi_linear_flash/rdclk - -# address mapping - -ad_cpu_interconnect 0x41400000 sys_mb_debug -ad_cpu_interconnect 0x40E00000 axi_ethernet -ad_cpu_interconnect 0x40010000 axi_gpio_lcd -ad_cpu_interconnect 0x41E10000 axi_ethernet_dma -ad_cpu_interconnect 0x41200000 axi_intc -ad_cpu_interconnect 0x41C00000 axi_timer -ad_cpu_interconnect 0x40600000 axi_uart -ad_cpu_interconnect 0x41600000 axi_iic_main -ad_cpu_interconnect 0x45000000 axi_sysid_0 -ad_cpu_interconnect 0x40000000 axi_gpio -ad_cpu_interconnect 0x44A70000 axi_spi -ad_cpu_interconnect 0x60000000 axi_linear_flash - -ad_mem_hp0_interconnect sys_200m_clk axi_ddr_cntrl/S_AXI -ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_DC -ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC -ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG -ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S -ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM - -create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \ - [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr -create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \ - [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr - -set_property range 0x8000000 [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_linear_flash}] diff --git a/projects/common/vc707/vc707_system_constr.xdc b/projects/common/vc707/vc707_system_constr.xdc deleted file mode 100644 index 6dec2947f3a..00000000000 --- a/projects/common/vc707/vc707_system_constr.xdc +++ /dev/null @@ -1,87 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# constraints - -set_property -dict {PACKAGE_PIN AV40 IOSTANDARD LVCMOS18} [get_ports sys_rst] - -# clocks - -set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS} [get_ports sys_clk_p] -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS} [get_ports sys_clk_n] - -# ethernet - -set_property PACKAGE_PIN AN2 [get_ports sgmii_txp] -set_property PACKAGE_PIN AN1 [get_ports sgmii_txn] -set_property PACKAGE_PIN AM8 [get_ports sgmii_rxp] -set_property PACKAGE_PIN AM7 [get_ports sgmii_rxn] - -set_property PACKAGE_PIN AH8 [get_ports mgt_clk_p] -set_property PACKAGE_PIN AH7 [get_ports mgt_clk_n] - -# Define the 125 MHz SGMII clock -create_clock -name mgt_clk -period 8.00 [get_ports mgt_clk_p] - -set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18} [get_ports phy_rstn] -set_property -dict {PACKAGE_PIN AH31 IOSTANDARD LVCMOS18} [get_ports mdio_mdc] -set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18} [get_ports mdio_mdio] - -set_false_path -through [get_nets phy_rstn] - -# uart - -set_property -dict {PACKAGE_PIN AU33 IOSTANDARD LVCMOS18} [get_ports uart_sin] -set_property -dict {PACKAGE_PIN AU36 IOSTANDARD LVCMOS18} [get_ports uart_sout] - -# fan - -set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm] - -# lcd - -set_property -dict {PACKAGE_PIN AT40 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[6]] ; ## lcd_e -set_property -dict {PACKAGE_PIN AN41 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[5]] ; ## lcd_rs -set_property -dict {PACKAGE_PIN AR42 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[4]] ; ## lcd_rw -set_property -dict {PACKAGE_PIN AN40 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[3]] ; ## lcd_db[7] -set_property -dict {PACKAGE_PIN AR39 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[2]] ; ## lcd_db[6] -set_property -dict {PACKAGE_PIN AR38 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[1]] ; ## lcd_db[5] -set_property -dict {PACKAGE_PIN AT42 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[0]] ; ## lcd_db[4] -set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0 -set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1 -set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2 -set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3 -set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## GPIO_DIP_SW4 -set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## GPIO_DIP_SW5 -set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## GPIO_DIP_SW6 -set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## GPIO_DIP_SW7 -set_property -dict {PACKAGE_PIN AR40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[8]] ; ## GPIO_SW_N -set_property -dict {PACKAGE_PIN AU38 IOSTANDARD LVCMOS18} [get_ports gpio_bd[9]] ; ## GPIO_SW_E -set_property -dict {PACKAGE_PIN AP40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[10]] ; ## GPIO_SW_S -set_property -dict {PACKAGE_PIN AW40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[11]] ; ## GPIO_SW_W -set_property -dict {PACKAGE_PIN AV39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[12]] ; ## GPIO_SW_C -set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[13]] ; ## GPIO_LED_0_LS -set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[14]] ; ## GPIO_LED_1_LS -set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## GPIO_LED_2_LS -set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18} [get_ports gpio_bd[16]] ; ## GPIO_LED_3_LS -set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18} [get_ports gpio_bd[17]] ; ## GPIO_LED_4_LS -set_property -dict {PACKAGE_PIN AP41 IOSTANDARD LVCMOS18} [get_ports gpio_bd[18]] ; ## GPIO_LED_5_LS -set_property -dict {PACKAGE_PIN AP42 IOSTANDARD LVCMOS18} [get_ports gpio_bd[19]] ; ## GPIO_LED_6_LS -set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[20]] ; ## GPIO_LED_7_LS - -# iic - -set_property -dict {PACKAGE_PIN AY42 IOSTANDARD LVCMOS18} [get_ports iic_rstn] -set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl] -set_property -dict {PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda] - -#Setting the Configuration Bank Voltage Select -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] - -# Create SPI clock -create_generated_clock -name spi_clk \ - -source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \ - -divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o] diff --git a/projects/common/vc707/vc707_system_mig.prj b/projects/common/vc707/vc707_system_mig.prj deleted file mode 100644 index 6fec8b1b2a7..00000000000 --- a/projects/common/vc707/vc707_system_mig.prj +++ /dev/null @@ -1,203 +0,0 @@ - - - - system_axi_ddr_cntrl_0 - 1 - 1 - OFF - 1024 - ON - Disabled - xc7vx485t-ffg1761/-2 - 2.3 - Differential - Use System Clock - ACTIVE HIGH - FALSE - 0 - 50 Ohms - 0 - - DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6 - 1250 - 2.0V - 4:1 - 200 - 1 - 800 - 8.000 - 1 - 1 - 1 - 1 - 64 - 1 - 1 - Disabled - Normal - FALSE - - 14 - 10 - 3 - 1.5V - 1073741824 - BANK_ROW_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 - Fixed - Sequential - 11 - Normal - No - Slow Exit - Enable - RZQ/6 - Disable - Enable - RZQ/6 - 0 - Disabled - Enabled - Output Buffer Enabled - Full Array - 8 - Enabled - Normal - Dynamic ODT off - AXI - - RD_PRI_REG - 30 - 256 - 3 - 0 - - - - diff --git a/projects/fmcomms2/vc707/Makefile b/projects/fmcomms2/vc707/Makefile deleted file mode 100644 index a9f45ab15e3..00000000000 --- a/projects/fmcomms2/vc707/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. -### SPDX short identifier: BSD-1-Clause -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := fmcomms2_vc707 - -M_DEPS += ../common/fmcomms2_bd.tcl -M_DEPS += ../../scripts/adi_pd.tcl -M_DEPS += ../../common/vc707/vc707_system_mig.prj -M_DEPS += ../../common/vc707/vc707_system_constr.xdc -M_DEPS += ../../common/vc707/vc707_system_bd.tcl -M_DEPS += ../../../library/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl - -LIB_DEPS += axi_ad9361 -LIB_DEPS += axi_dmac -LIB_DEPS += axi_sysid -LIB_DEPS += sysid_rom -LIB_DEPS += util_pack/util_cpack2 -LIB_DEPS += util_pack/util_upack2 -LIB_DEPS += util_rfifo -LIB_DEPS += util_tdd_sync -LIB_DEPS += util_wfifo -LIB_DEPS += xilinx/util_clkdiv - -include ../../scripts/project-xilinx.mk diff --git a/projects/fmcomms2/vc707/README.md b/projects/fmcomms2/vc707/README.md deleted file mode 100644 index 2a7f10945c5..00000000000 --- a/projects/fmcomms2/vc707/README.md +++ /dev/null @@ -1,13 +0,0 @@ -# FMCOMMS2/VC707 HDL Project - -## Building the project - -``` -cd projects/fmcomms2/vc707 -make -``` - -Corresponding device trees: - -- for FMCOMMS2/3: [vc707_fmcomms2-3.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vc707_fmcomms2-3.dts) -- for FMCOMMS4: [vc707_fmcomms4.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vc707_fmcomms4.dts) \ No newline at end of file diff --git a/projects/fmcomms2/vc707/system_bd.tcl b/projects/fmcomms2/vc707/system_bd.tcl deleted file mode 100644 index 1bd16552e49..00000000000 --- a/projects/fmcomms2/vc707/system_bd.tcl +++ /dev/null @@ -1,17 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl -source ../common/fmcomms2_bd.tcl -source $ad_hdl_dir/projects/scripts/adi_pd.tcl - -#system ID -ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 -ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" -ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 - -sysid_gen_sys_init_file - -ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 22 diff --git a/projects/fmcomms2/vc707/system_constr.xdc b/projects/fmcomms2/vc707/system_constr.xdc deleted file mode 100644 index 6def4acbfc4..00000000000 --- a/projects/fmcomms2/vc707/system_constr.xdc +++ /dev/null @@ -1,69 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -# constraints -# ad9361 - -set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC1_HPC_LA00_CC_P -set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC1_HPC_LA00_CC_N -set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC1_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC1_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC1_HPC_LA02_P -set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC1_HPC_LA02_N -set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC1_HPC_LA03_P -set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC1_HPC_LA03_N -set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC1_HPC_LA04_P -set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC1_HPC_LA04_N -set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC1_HPC_LA05_P -set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC1_HPC_LA05_N -set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC1_HPC_LA06_P -set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC1_HPC_LA06_N -set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC1_HPC_LA07_P -set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC1_HPC_LA07_N -set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## G12 FMC1_HPC_LA08_P -set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## G13 FMC1_HPC_LA08_N -set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## D14 FMC1_HPC_LA09_P -set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## D15 FMC1_HPC_LA09_N -set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## H16 FMC1_HPC_LA11_P -set_property -dict {PACKAGE_PIN F41 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## H17 FMC1_HPC_LA11_N -set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## G15 FMC1_HPC_LA12_P -set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## G16 FMC1_HPC_LA12_N -set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## D17 FMC1_HPC_LA13_P -set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## D18 FMC1_HPC_LA13_N -set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## C14 FMC1_HPC_LA10_P -set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## C15 FMC1_HPC_LA10_N -set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## C18 FMC1_HPC_LA14_P -set_property -dict {PACKAGE_PIN N40 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## C19 FMC1_HPC_LA14_N -set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## H19 FMC1_HPC_LA15_P -set_property -dict {PACKAGE_PIN L37 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## H20 FMC1_HPC_LA15_N - -set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## G21 FMC1_HPC_LA20_P -set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## G22 FMC1_HPC_LA20_N -set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] ; ## H25 FMC1_HPC_LA21_P -set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] ; ## H26 FMC1_HPC_LA21_N -set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] ; ## G24 FMC1_HPC_LA22_P -set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] ; ## G25 FMC1_HPC_LA22_N -set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] ; ## D23 FMC1_HPC_LA23_P -set_property -dict {PACKAGE_PIN N31 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] ; ## D24 FMC1_HPC_LA23_N -set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] ; ## H28 FMC1_HPC_LA24_P -set_property -dict {PACKAGE_PIN P31 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] ; ## H29 FMC1_HPC_LA24_N -set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] ; ## G27 FMC1_HPC_LA25_P -set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## G28 FMC1_HPC_LA25_N -set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC1_HPC_LA19_P -set_property -dict {PACKAGE_PIN W31 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC1_HPC_LA19_N -set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC1_HPC_LA28_P - -set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports enable] ; ## G18 FMC1_HPC_LA16_P -set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## G19 FMC1_HPC_LA16_N - -set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC1_HPC_LA26_P -set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC1_HPC_LA26_N -set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## C26 FMC1_HPC_LA27_P -set_property -dict {PACKAGE_PIN H31 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## C27 FMC1_HPC_LA27_N - -# clocks - -create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] - diff --git a/projects/fmcomms2/vc707/system_project.tcl b/projects/fmcomms2/vc707/system_project.tcl deleted file mode 100644 index 2c713f424c6..00000000000 --- a/projects/fmcomms2/vc707/system_project.tcl +++ /dev/null @@ -1,19 +0,0 @@ -############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -### SPDX short identifier: ADIBSD -############################################################################### - -source ../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project fmcomms2_vc707 -adi_project_files fmcomms2_vc707 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] - -adi_project_run fmcomms2_vc707 -source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl - diff --git a/projects/fmcomms2/vc707/system_top.v b/projects/fmcomms2/vc707/system_top.v deleted file mode 100644 index 5288a0a7108..00000000000 --- a/projects/fmcomms2/vc707/system_top.v +++ /dev/null @@ -1,229 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - input uart_sin, - output uart_sout, - - output [13:0] ddr3_addr, - output [ 2:0] ddr3_ba, - output ddr3_cas_n, - output [ 0:0] ddr3_ck_n, - output [ 0:0] ddr3_ck_p, - output [ 0:0] ddr3_cke, - output [ 0:0] ddr3_cs_n, - output [ 7:0] ddr3_dm, - inout [63:0] ddr3_dq, - inout [ 7:0] ddr3_dqs_n, - inout [ 7:0] ddr3_dqs_p, - output [ 0:0] ddr3_odt, - output ddr3_ras_n, - output ddr3_reset_n, - output ddr3_we_n, - - output [26:1] linear_flash_addr, - output linear_flash_adv_ldn, - output linear_flash_ce_n, - output linear_flash_oen, - output linear_flash_wen, - inout [15:0] linear_flash_dq_io, - - input sgmii_rxp, - input sgmii_rxn, - output sgmii_txp, - output sgmii_txn, - - output phy_rstn, - input mgt_clk_p, - input mgt_clk_n, - output mdio_mdc, - inout mdio_mdio, - - output fan_pwm, - - inout [ 6:0] gpio_lcd, - inout [20:0] gpio_bd, - - output iic_rstn, - inout iic_scl, - inout iic_sda, - - input rx_clk_in_p, - input rx_clk_in_n, - input rx_frame_in_p, - input rx_frame_in_n, - input [ 5:0] rx_data_in_p, - input [ 5:0] rx_data_in_n, - - output tx_clk_out_p, - output tx_clk_out_n, - output tx_frame_out_p, - output tx_frame_out_n, - output [ 5:0] tx_data_out_p, - output [ 5:0] tx_data_out_n, - - output txnrx, - output enable, - - inout gpio_resetb, - inout gpio_sync, - inout gpio_en_agc, - inout [ 3:0] gpio_ctl, - inout [ 7:0] gpio_status, - - output spi_csn_0, - output spi_clk, - output spi_mosi, - input spi_miso -); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 7:0] spi_csn; - - // default logic - - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - assign spi_csn_0 = spi_csn[0]; - - // instantiations - - ad_iobuf #( - .DATA_WIDTH(15) - ) i_iobuf ( - .dio_t (gpio_t[46:32]), - .dio_i (gpio_o[46:32]), - .dio_o (gpio_i[46:32]), - .dio_p ({ gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status})); - - ad_iobuf #( - .DATA_WIDTH(21) - ) i_iobuf_sw_led ( - .dio_t (gpio_t[20:0]), - .dio_i (gpio_o[20:0]), - .dio_o (gpio_i[20:0]), - .dio_p (gpio_bd)); - - assign gpio_i[63:47] = gpio_o[63:47]; - assign gpio_i[31:21] = gpio_o[31:21]; - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .linear_flash_addr (linear_flash_addr), - .linear_flash_adv_ldn (linear_flash_adv_ldn), - .linear_flash_ce_n (linear_flash_ce_n), - .linear_flash_oen (linear_flash_oen), - .linear_flash_wen (linear_flash_wen), - .linear_flash_dq_io(linear_flash_dq_io), - .gpio_lcd_tri_io (gpio_lcd), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio0_i (gpio_i[31:0]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio1_i (gpio_i[63:32]), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .mdio_mdc (mdio_mdc), - .mdio_mdio_io (mdio_mdio), - .mgt_clk_clk_n (mgt_clk_n), - .mgt_clk_clk_p (mgt_clk_p), - .phy_rstn (phy_rstn), - .phy_sd (1'b1), - .sgmii_rxn (sgmii_rxn), - .sgmii_rxp (sgmii_rxp), - .sgmii_txn (sgmii_txn), - .sgmii_txp (sgmii_txp), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .spi_clk_i (), - .spi_clk_o (spi_clk), - .spi_csn_i (spi_csn), - .spi_csn_o (spi_csn), - .spi_sdi_i (spi_miso), - .spi_sdo_i (spi_mosi), - .spi_sdo_o (spi_mosi), - .rx_clk_in_n (rx_clk_in_n), - .rx_clk_in_p (rx_clk_in_p), - .rx_data_in_n (rx_data_in_n), - .rx_data_in_p (rx_data_in_p), - .rx_frame_in_n (rx_frame_in_n), - .rx_frame_in_p (rx_frame_in_p), - .tx_clk_out_n (tx_clk_out_n), - .tx_clk_out_p (tx_clk_out_p), - .tx_data_out_n (tx_data_out_n), - .tx_data_out_p (tx_data_out_p), - .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p), - .tdd_sync_i (1'b0), - .tdd_sync_o (), - .tdd_sync_t (), - .uart_sin (uart_sin), - .uart_sout (uart_sout), - .enable (enable), - .txnrx (txnrx), - .up_enable (gpio_o[47]), - .up_txnrx (gpio_o[48])); - -endmodule diff --git a/projects/scripts/adi_project_xilinx.tcl b/projects/scripts/adi_project_xilinx.tcl index d29c2eaf752..565f668cfcc 100644 --- a/projects/scripts/adi_project_xilinx.tcl +++ b/projects/scripts/adi_project_xilinx.tcl @@ -45,7 +45,7 @@ set p_prcfg_status "" # \param[parameter_list] - a list of global parameters (parameters of the # system_top module) # -# Supported carrier names are: ac701, kc705, vc707, vcu118, vcu128, kcu105, zed, +# Supported carrier names are: ac701, kc705, vcu118, vcu128, kcu105, zed, # microzed, zc702, zc706, mitx405, zcu102. # proc adi_project {project_name {mode 0} {parameter_list {}} } { @@ -62,10 +62,6 @@ proc adi_project {project_name {mode 0} {parameter_list {}} } { set device "xc7k325tffg900-2" set board [lindex [lsearch -all -inline [get_board_parts] *kc705*] end] } - if [regexp "_vc707" $project_name] { - set device "xc7vx485tffg1761-2" - set board [lindex [lsearch -all -inline [get_board_parts] *vc707*] end] - } if [regexp "_vcu118" $project_name] { set device "xcvu9p-flga2104-2L-e" set board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end]