From 54e316dac3238a030cde6e59618dd4d0f72181ee Mon Sep 17 00:00:00 2001
From: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Date: Thu, 5 Dec 2024 18:03:02 +0200
Subject: [PATCH 1/2] fmcomms8/zcu102: Replace dacfifo with data_offload

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
---
 projects/fmcomms8/common/fmcomms8_bd.tcl | 38 ++++++++++++------------
 projects/fmcomms8/zcu102/Makefile        |  9 ++++--
 projects/fmcomms8/zcu102/system_bd.tcl   | 13 ++++----
 projects/fmcomms8/zcu102/system_top.v    |  3 +-
 4 files changed, 33 insertions(+), 30 deletions(-)

diff --git a/projects/fmcomms8/common/fmcomms8_bd.tcl b/projects/fmcomms8/common/fmcomms8_bd.tcl
index 3c98a538713..42c53213867 100644
--- a/projects/fmcomms8/common/fmcomms8_bd.tcl
+++ b/projects/fmcomms8/common/fmcomms8_bd.tcl
@@ -9,8 +9,6 @@ create_bd_port -dir I ref_clk_d
 create_bd_port -dir I core_clk_c
 create_bd_port -dir I core_clk_d
 
-create_bd_port -dir I dac_fifo_bypass
-
 #
 # Parameter description:
 #   [TX/RX/RX_OS]_JESD_M  : Number of converters per link
@@ -25,6 +23,7 @@ set MAX_RX_OS_NUM_OF_LANES 4
 
 set DATAPATH_WIDTH 4
 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
+source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
 
 # TX parameters
 set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L)      ; # L
@@ -62,10 +61,18 @@ set RX_OS_TPL_WIDTH [ expr { [info exists ad_project_params(RX_OS_TPL_WIDTH)] \
 set RX_OS_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_OS_NUM_OF_LANES $RX_OS_NUM_OF_CONVERTERS $RX_OS_SAMPLES_PER_FRAME $RX_OS_SAMPLE_WIDTH $RX_OS_TPL_WIDTH]
 set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 8 * $RX_OS_DATAPATH_WIDTH / ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)]
 
-set dac_fifo_name axi_adrv9009_fmc_tx_fifo
+set dac_offload_name adrv9009_fmc_data_offload
 set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
 
-ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
+ad_data_offload_create $dac_offload_name \
+                       1 \
+                       $dac_offload_type \
+                       $dac_offload_size \
+                       $dac_data_width \
+                       $dac_data_width
+
+ad_ip_parameter $dac_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
+ad_connect $dac_offload_name/sync_ext GND
 
 ad_ip_instance axi_adxcvr axi_adrv9009_fmc_tx_xcvr
 ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.NUM_OF_LANES $MAX_TX_NUM_OF_LANES
@@ -300,23 +307,15 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
 
 ad_connect tx_adrv9009_fmc_tpl_core/dac_dunf util_fmc_tx_upack/fifo_rd_underflow
 
-ad_connect  core_clk_c axi_adrv9009_fmc_tx_fifo/dac_clk
-ad_connect  core_clk_c_rstgen/peripheral_reset axi_adrv9009_fmc_tx_fifo/dac_rst
+ad_connect  core_clk_c $dac_offload_name/m_axis_aclk
+ad_connect  core_clk_c_rstgen/peripheral_aresetn $dac_offload_name/m_axis_aresetn
+ad_connect  util_fmc_tx_upack/s_axis $dac_offload_name/m_axis
 
-ad_connect  util_fmc_tx_upack/s_axis_valid VCC
-ad_connect  util_fmc_tx_upack/s_axis_ready axi_adrv9009_fmc_tx_fifo/dac_valid
-ad_connect  util_fmc_tx_upack/s_axis_data axi_adrv9009_fmc_tx_fifo/dac_data
-
-ad_connect  core_clk_c axi_adrv9009_fmc_tx_fifo/dma_clk
-ad_connect  core_clk_c_rstgen/peripheral_reset axi_adrv9009_fmc_tx_fifo/dma_rst
+ad_connect  core_clk_c $dac_offload_name/s_axis_aclk
+ad_connect  core_clk_c_rstgen/peripheral_aresetn $dac_offload_name/s_axis_aresetn
 ad_connect  core_clk_c axi_adrv9009_fmc_tx_dma/m_axis_aclk
-ad_connect  axi_adrv9009_fmc_tx_fifo/dma_xfer_req axi_adrv9009_fmc_tx_dma/m_axis_xfer_req
-ad_connect  axi_adrv9009_fmc_tx_fifo/dma_ready axi_adrv9009_fmc_tx_dma/m_axis_ready
-ad_connect  axi_adrv9009_fmc_tx_fifo/dma_data axi_adrv9009_fmc_tx_dma/m_axis_data
-ad_connect  axi_adrv9009_fmc_tx_fifo/dma_valid axi_adrv9009_fmc_tx_dma/m_axis_valid
-ad_connect  axi_adrv9009_fmc_tx_fifo/dma_xfer_last axi_adrv9009_fmc_tx_dma/m_axis_last
-
-ad_connect  axi_adrv9009_fmc_tx_fifo/bypass dac_fifo_bypass
+ad_connect  $dac_offload_name/s_axis axi_adrv9009_fmc_tx_dma/m_axis
+ad_connect  $dac_offload_name/init_req axi_adrv9009_fmc_tx_dma/m_axis_xfer_req
 
 ad_connect  core_clk_d rx_adrv9009_fmc_tpl_core/link_clk
 ad_connect  axi_adrv9009_fmc_rx_jesd/rx_sof rx_adrv9009_fmc_tpl_core/link_sof
@@ -365,6 +364,7 @@ ad_cpu_interconnect 0x45A50000 axi_adrv9009_fmc_rx_jesd
 ad_cpu_interconnect 0x45A60000 axi_adrv9009_fmc_obs_xcvr
 ad_cpu_interconnect 0x45A70000 axi_adrv9009_fmc_obs_jesd
 ad_cpu_interconnect 0x7d400000 axi_adrv9009_fmc_tx_dma
+ad_cpu_interconnect 0x7d410000 $dac_offload_name
 ad_cpu_interconnect 0x7d420000 axi_adrv9009_fmc_rx_dma
 ad_cpu_interconnect 0x7d440000 axi_adrv9009_fmc_obs_dma
 
diff --git a/projects/fmcomms8/zcu102/Makefile b/projects/fmcomms8/zcu102/Makefile
index 752e6628f41..1a28728c73e 100644
--- a/projects/fmcomms8/zcu102/Makefile
+++ b/projects/fmcomms8/zcu102/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -11,12 +11,14 @@ M_DEPS += ../common/fmcomms8_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
 M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
-M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
 LIB_DEPS += axi_dmac
 LIB_DEPS += axi_sysid
+LIB_DEPS += data_offload
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
 LIB_DEPS += jesd204/axi_jesd204_rx
@@ -24,7 +26,8 @@ LIB_DEPS += jesd204/axi_jesd204_tx
 LIB_DEPS += jesd204/jesd204_rx
 LIB_DEPS += jesd204/jesd204_tx
 LIB_DEPS += sysid_rom
-LIB_DEPS += util_dacfifo
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
 LIB_DEPS += util_pack/util_cpack2
 LIB_DEPS += util_pack/util_upack2
 LIB_DEPS += xilinx/axi_adxcvr
diff --git a/projects/fmcomms8/zcu102/system_bd.tcl b/projects/fmcomms8/zcu102/system_bd.tcl
index 9897a2a70ee..31a2fe1c85f 100644
--- a/projects/fmcomms8/zcu102/system_bd.tcl
+++ b/projects/fmcomms8/zcu102/system_bd.tcl
@@ -1,15 +1,15 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
+## Offload attributes
+set dac_offload_type 0                   ; ## BRAM
+set dac_offload_size [expr 2*1024*1024]  ; ## 2 MB
+
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
-## FIFO depth is 8Mb - 500k samples
-set dac_fifo_address_width 16
-
 #system ID
 ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
@@ -24,7 +24,8 @@ S=$ad_project_params(TX_JESD_S)\
 RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
 L=$ad_project_params(RX_OS_JESD_L)\
 S=$ad_project_params(RX_OS_JESD_S)\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_offload_type\
+SIZE=$dac_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring
 
diff --git a/projects/fmcomms8/zcu102/system_top.v b/projects/fmcomms8/zcu102/system_top.v
index 519392998f0..c2efeaa5b9c 100644
--- a/projects/fmcomms8/zcu102/system_top.v
+++ b/projects/fmcomms8/zcu102/system_top.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -356,7 +356,6 @@ module system_top (
     .tx_data_7_p (tx_data_d_p[3]),
     .tx_sync_0 (tx_sync),
     .tx_sysref_0 (sysref_c),
-    .dac_fifo_bypass(gpio_o[68]),
 
     .spi0_sclk (spi_clk),
     .spi0_csn (spi_csn),

From 4d447ac6f2e9f2ed9dbcbc0db4a2ad89766b123e Mon Sep 17 00:00:00 2001
From: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Date: Fri, 28 Mar 2025 19:48:31 +0200
Subject: [PATCH 2/2] docs: fmcomms8: Update for Data Offload support

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
---
 docs/projects/fmcomms8/fmcomms8_jesd204b.svg | 828 ++++++++++---------
 docs/projects/fmcomms8/index.rst             |   1 +
 2 files changed, 436 insertions(+), 393 deletions(-)

diff --git a/docs/projects/fmcomms8/fmcomms8_jesd204b.svg b/docs/projects/fmcomms8/fmcomms8_jesd204b.svg
index 0f7f1f4261b..6be8558232a 100644
--- a/docs/projects/fmcomms8/fmcomms8_jesd204b.svg
+++ b/docs/projects/fmcomms8/fmcomms8_jesd204b.svg
@@ -2,12 +2,12 @@
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+   width="857.8125"
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@@ -20,9 +20,9 @@
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@@ -351,9 +351,9 @@
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-         d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(0.4)"
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@@ -367,9 +367,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(-0.4)"
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@@ -384,9 +384,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(-0.4)" />
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@@ -400,9 +400,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(0.4)" />
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@@ -415,9 +415,9 @@
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          inkscape:connector-curvature="0"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(-0.4)" />
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@@ -431,9 +431,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(0.4)" />
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@@ -444,9 +444,9 @@
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        inkscape:stockid="TriangleInM">
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+         transform="scale(-0.4)"
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@@ -459,9 +459,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -474,9 +474,9 @@
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        inkscape:stockid="TriangleInM">
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+         transform="scale(-0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -489,9 +489,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -504,9 +504,9 @@
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        inkscape:stockid="TriangleInM">
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+         transform="scale(-0.4)"
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@@ -519,9 +519,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -534,9 +534,9 @@
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        inkscape:stockid="TriangleInM">
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+         transform="scale(-0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -549,9 +549,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -564,9 +564,9 @@
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        inkscape:stockid="TriangleInM">
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+         transform="scale(-0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -581,9 +581,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(0.4)" />
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@@ -596,9 +596,9 @@
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+         transform="scale(-0.4)" />
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@@ -609,9 +609,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -626,9 +626,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(-0.4)" />
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@@ -639,9 +639,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -656,9 +656,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(-0.4)" />
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@@ -669,9 +669,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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@@ -686,9 +686,9 @@
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+         transform="scale(-0.4)" />
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@@ -699,9 +699,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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@@ -716,9 +716,9 @@
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+         transform="scale(-0.4)" />
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@@ -729,9 +729,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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@@ -746,9 +746,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(-0.4)" />
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@@ -759,9 +759,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -776,9 +776,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(-0.4)" />
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@@ -789,9 +789,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -806,9 +806,9 @@
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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+         transform="scale(-0.4)" />
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@@ -819,9 +819,9 @@
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        inkscape:stockid="TriangleOutM">
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+         transform="scale(0.4)"
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+         d="M 5.77,0 -2.88,5 V -5 Z"
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@@ -836,9 +836,9 @@
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+         transform="scale(-0.4)" />
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@@ -849,9 +849,9 @@
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+         transform="scale(0.4)"
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@@ -866,9 +866,9 @@
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+         transform="scale(-0.4)" />
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@@ -879,9 +879,9 @@
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+         transform="scale(-0.4)" />
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@@ -911,9 +911,9 @@
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+         transform="scale(-0.4)" />
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@@ -956,9 +956,9 @@
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+         transform="scale(0.4)" />
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@@ -984,9 +984,9 @@
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diff --git a/docs/projects/fmcomms8/index.rst b/docs/projects/fmcomms8/index.rst
index 205c89d46be..6a070b2a6bb 100644
--- a/docs/projects/fmcomms8/index.rst
+++ b/docs/projects/fmcomms8/index.rst
@@ -157,6 +157,7 @@ axi_adrv9009_fmc_rx_jesd  0x85A5_0000
 axi_adrv9009_fmc_obs_jesd 0x85A7_0000
 axi_adrv9009_fmc_rx_dma   0x9D42_0000
 axi_adrv9009_fmc_tx_dma   0x9D40_0000
+adrv9009_fmc_data_offload 0x9D41_0000
 axi_adrv9009_fmc_obs_dma  0x9D44_0000
 ========================= ===========