[BUG] ADRV 9009 ZCU102 Clocking/sampling rate mismatches.

[kdropucic-eridan]

Describe the bug
Clocking/sampling rate mismatches.

1. wrong constraint value for 245.76 MHz clock - 4.00 should be 4.069
   https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/zcu102/system_constr.xdc#L85
   https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/zcu102/system_constr.xdc#L86
   correct settings in a similar project (different dev board)
   https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/s10soc/system_constr.sdc#L7
   https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/s10soc/system_constr.sdc#L8

Think 250 MHz is not used anywhere since Petalinux gives us this:
root@analog:~# cat /sys/bus/iio/devices/iio\:device4/in_voltage_sampling_frequency_available
245760000 30720000
root@analog:~# cat /sys/bus/iio/devices/iio\:device4/in_voltage_sampling_frequency
245760000

2. Wrong clock/sampling frequency is actually mentioned/reported in FIR compiler
   It should be 245.76 MHz, but 122.88 MHz is actually reported:
   
   https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/common/adrv9009_bd.tcl#L91
   https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/common/adrv9009_bd.tcl#L92
   https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/common/adrv9009_bd.tcl#L158
   https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/common/adrv9009_bd.tcl#L159

Maybe because axi_adrv9009_rx_clkgen has CLK1 enabled and set to generate output = input / 2 after all the math is done (245.76 MHZ / 2 = 122.88), but CLK0 output (245.76 MHz) is connected and used:
https://github.com/analogdevicesinc/hdl/blob/main/projects/adrv9009/common/adrv9009_bd.tcl#L133

To Reproduce
Bugs are in the project's XDX and TCL files.
Petalinux also mentiones 245.76 MHz for JESD:
root@analog:~# cat /sys/bus/platform/devices/84aa0000.axi-jesd204-rx/status
Link is enabled
Measured Link Clock: 245.784 MHz
Reported Link Clock: 245.760 MHz
Measured Device Clock: 245.784 MHz
Reported Device Clock: 245.760 MHz
Desired Device Clock: 245.760 MHz
Lane rate: 9830.400 MHz
Lane rate / 40: 245.760 MHz
LMFC rate: 7.680 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No

Expected behavior
Everything works, it's just confusing and hard to follow which clk/sample rate is used in the design/project.
We want to change the design to use 122.88 MHz clk/sample rate.

Screenshots
Provided together with the bug explanation.

Desktop (please complete the following information):

• Project name and used carrier board ADRV 9009 ZCU102
• Used Software: (Peta)Linux
• Tool version: Vivado 2023.2
• HDL Release version: 2023_R2_p1
• Software Release version 2023_R2

Additional context
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