ad6676: Add VADJ values in README

StancaPop · StancaPop · commit dd39507095b6 · 2025-06-25T17:07:42.000+03:00
Signed-off-by: Stanca Pop &lt;stanca.pop@analog.com&gt;
diff --git a/projects/ad6676evb/README.md b/projects/ad6676evb/README.md
@@ -3,6 +3,7 @@
 - Evaluation board product page: [EVAL-AD6676](https://www.analog.com/eval-AD6676)
 - System documentation: https://wiki.analog.com/resources/eval/ad6676-wideband_rx_subsystem_ad6676ebz
 - HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad6676evb/index.html
+- Evaluation board VADJ: 2.5V
 
 ## Supported parts
 
@@ -12,4 +13,4 @@
 
 ## Building the project
 
-Please enter the folder for the FPGA carrier you want to use and read the README.md.
+Please enter the folder for the FPGA carrier you want to use and read the README.md.
diff --git a/projects/ad6676evb/vc707/README.md b/projects/ad6676evb/vc707/README.md
@@ -1,5 +1,9 @@
+<!-- no_no_os -->
+
 # AD6676-EVB/VC707 HDL Project
 
+- VADJ with which it was tested in hardware: 1.8V
+
 ## Building the project
 
 The parameter configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
diff --git a/projects/ad6676evb/zc706/README.md b/projects/ad6676evb/zc706/README.md
@@ -1,5 +1,9 @@
+<!-- no_no_os -->
+
 # AD6676-EVB/ZC706 HDL Project
 
+- VADJ with which it was tested in hardware: 2.5V
+
 ## Building the project
 
 The parameter configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
