New sections for IP's pages

cristianmihaipopa · web-flow · commit b19dd76f39b2 · 2024-09-02T11:04:13.000+03:00
Added two new sections at the end of each of the IP's documentation page &amp; fixed minor mistakes. New sections: 

- Software Support, refers to Linux/No-Os drivers and everything related
- References, general and useful info about the IP
diff --git a/docs/library/axi_ad9671/index.rst b/docs/library/axi_ad9671/index.rst
@@ -154,9 +154,8 @@ module (at IP level).
 References
 -------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_ad9671`
+* HDL IP core at :git-hdl:`library/axi_ad9671`
 * :adi:`AD9671`
-* :git-linux:`/`
 * :ref:`jesd204`
 * :adi:`Analog Device's JESD204B Survival Guide <media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf>`
 * :intel:`JESD204B Intel FPGA IP User Guide <content/dam/support/us/en/programmable/support-resources/bulk-container/pdfs/literature/ug/archives/ug-jesd204b-18-1.pdf>`
diff --git a/docs/library/axi_ad9783/index.rst b/docs/library/axi_ad9783/index.rst
@@ -295,19 +295,26 @@ registers relative address.
 Software Guidelines
 --------------------------------------------------------------------------------
 
-The software for this IP can be found as part of the ZCU102 Reference Design
-at :git-linux:`/`.
+The software for this IP can be found as part of the ZCU102 Reference Design.
 The IP expects the software run a calibration at least once. It has to find
 out what value for the SMP_DLY (see in datasheet) is good for the PRBS to
 work.
 
+Software Support
+--------------------------------------------------------------------------------
+
+* Linux device driver at :git-linux:`drivers/iio/adc/ad9783.c`
+* Linux device tree at :git-linux:`arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9783.dts`
+
 References
 -------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_ad9783`
+* HDL IP core at :git-hdl:`library/axi_ad9783`
+* HDL project at :git-hdl:`projects/ad9783_ebz`
+* HDL project documentation at :ref:`ad9783_ebz`
 * :adi:`AD9783`
-* :git-linux:`/`
 * :adi:`EVAL-AD9783 <en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9783.html>`
+* :dokuwiki:`AXI AD9783 on wiki <resources/fpga/docs/axi_ad9783>`
 * :dokuwiki:`EVAL-AD9783 with ZCU102 reference design description <resources/fpga/xilinx/interposer/ad9783>`
 * :xilinx:`Ultrascale SelectIO <support/documentation/user_guides/ug571-ultrascale-selectio.pdf>`
 * :xilinx:`UltraScale Architecture Clocking Resources User Guide <support/documentation/user_guides/ug572-ultrascale-clocking.pdf>`
diff --git a/docs/library/axi_ad9963/index.rst b/docs/library/axi_ad9963/index.rst
@@ -248,15 +248,17 @@ Software Support
 --------------------------------------------------------------------------------
 
 The software for this part can be found as part of the :adi:`ADALM2000`
-(or shortly, M2K) reference design. It is supported by both :git-linux:`/` and
-:git-no-os:`/`.
+(or shortly, M2K) reference design. 
+
+* Linux device driver at :git-linux:`drivers/iio/adc/ad9963.c`
 
 References
 -------------------------------------------------------------------------------
 
 * :adi:`AD9963`
-* HDL source code at :git-hdl:`library/axi_ad9963`
-* Linux device driver :git-linux:`ad9963.c <drivers/iio/adc/ad9963.c>`
+* HDL IP core at :git-hdl:`library/axi_ad9963`
+* HDL project at :git-hdl:`projects/m2k`
+* HDL project documentation at :ref:`m2k`
 * :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`
 * :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`
 * :xilinx:`7 Series libraries <support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf>`
diff --git a/docs/library/axi_adaq8092/index.rst b/docs/library/axi_adaq8092/index.rst
@@ -197,19 +197,22 @@ The example design uses a processor to program all the registers. If no
 processor is available in your system, you can create your own IP starting from
 the interface module.
 
-Software Guidelines
+Software Support
 --------------------------------------------------------------------------------
 
-The software for this IP can be found as part of the ADAQ8092 Native FMC Card
-Reference Design at :git-no-OS:`no-OS Software <projects/adaq8092>` and
-Linux is supported at :git-linux:`/`.
+* No-OS project at :git-no-OS:`drivers/adc/adaq8092`
+* No-OS device driver at  :git-no-OS:`drivers/adc/drivers/adc/adaq8092/adaq8092.c`
+* Linux device driver at :git-linux:`drivers/iio/adc/adaq8092.c`
+* Linux device tree at :git-linux:`arch/arm/boot/dts/zynq-zed-adv7511-adaq8092.dts`
+* Linux device driver documentation
+  :dokuwiki:`on wiki <resources/tools-software/linux-drivers/iio-adc/adaq8092>`
 
 References
 -------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_adaq8092`
+* HDL IP core at :git-hdl:`library/axi_adaq8092`
+* HDL project at :git-hdl:`projects/adaq8092_fmc`
+* HDL project documentation at :ref:`adaq8092_fmc`
 * :adi:`ADAQ8092`
-* :git-linux:`/`
-* :git-no-OS:`projects/adaq8092`
 * :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`
 * :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`
diff --git a/docs/library/axi_adc_decimate/index.rst b/docs/library/axi_adc_decimate/index.rst
@@ -111,6 +111,6 @@ Register Map
 References
 --------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_adc_decimate`
-* :git-linux:`/`
+* HDL IP core at :git-hdl:`library/axi_adc_decimate`
+* :dokuwiki:`AXI ADC DECIMATE on wiki <resources/fpga/docs/axi_adc_decimate>`
 * :xilinx:`7 Series libraries <support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf>`
diff --git a/docs/library/axi_adc_trigger/index.rst b/docs/library/axi_adc_trigger/index.rst
@@ -201,5 +201,5 @@ Register Map
 References
 --------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_adc_trigger`
-* :git-linux:`/`
+* HDL IP core at :git-hdl:`library/axi_adc_trigger`
+* :dokuwiki:`AXI ADC TRIGGER on wiki <resources/fpga/docs/axi_adc_trigger>`
diff --git a/docs/library/axi_adxcvr/index.rst b/docs/library/axi_adxcvr/index.rst
@@ -318,15 +318,25 @@ RX link procedure
    the internal error counter to get the number of errors received. See the
    transceiver guide for details.
 
-More Information
+Software Support
 --------------------------------------------------------------------------------
 
--  :ref:`jesd204`
--  :dokuwiki:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver <resources/tools-software/linux-drivers/jesd204/axi_adxcvr>`
+* No-OS project at :git-no-OS:`drivers/axi_core/jesd204`
+* No-OS device driver at  :git-no-OS:`drivers/axi_core/jesd204/axi_adxcvr.c`
+* No-OS device driver documentation
+  :dokuwiki:`on wiki <resources/tools-software/uc-drivers/jesd204/axi_adxcvr>`
+* Linux project at :git-linux:`linux/drivers/iio/jesd204`
+* Linux device driver at :git-linux:`drivers/iio/jesd204/axi_adxcvr.c`
+* Linux device driver documentation
+  :dokuwiki:`on wiki <resources/tools-software/linux-drivers/jesd204/axi_adxcvr>`
 
-Reference
+References
 --------------------------------------------------------------------------------
 
--  :intel:`Intel® Arria® 10 Transceiver PHY User Guide <content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf>`
--  `7 Series FPGAs GTX/GTH Transceivers User Guide - AMD Xilinx <https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers>`_
--  `Ultrascale Architecture GTH Transceivers User Guide - AMD Xilinx <https://docs.amd.com/v/u/en-US/ug576-ultrascale-gth-transceivers>`_
+* HDL Intel IP core at :git-hdl:`library/intel/axi_adxcvr`
+* HDL Xilinx IP core at :git-hdl:`library/xilinx/axi_adxcvr`
+* :dokuwiki:`AXI ADXCVR on wiki <resources/fpga/docs/axi_adxcvr>`
+* :ref:`jesd204`
+* :intel:`Intel® Arria® 10 Transceiver PHY User Guide <content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf>`
+* `7 Series FPGAs GTX/GTH Transceivers User Guide - AMD Xilinx <https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers>`_
+* `Ultrascale Architecture GTH Transceivers User Guide - AMD Xilinx <https://docs.amd.com/v/u/en-US/ug576-ultrascale-gth-transceivers>`_
diff --git a/docs/library/axi_clkgen/index.rst b/docs/library/axi_clkgen/index.rst
@@ -97,7 +97,7 @@ Register Map
 References
 --------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_clkgen`
-* :git-linux:`/`
+* HDL IP core at :git-hdl:`library/axi_clkgen`
+* :dokuwiki:`AXI CLKGEN on wiki <resources/fpga/docs/axi_clkgen>`
 * :xilinx:`7 Series Clocking <support/documentation/user_guides/ug472_7Series_Clocking.pdf>`
 * :xilinx:`MMCM and PLL Dynamic Reconfiguration <support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf>`
diff --git a/docs/library/axi_dac_interpolate/index.rst b/docs/library/axi_dac_interpolate/index.rst
@@ -145,6 +145,6 @@ Register Map
 References
 --------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_dac_interpolate`
-* :git-linux:`/`
+* HDL IP core at :git-hdl:`library/axi_dac_interpolate`
+* :dokuwiki:`AXI DAC INTEPOLATE on wiki <resources/fpga/docs/axi_dac_interpolate>`
 * :xilinx:`7 Series libraries <support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf>`
diff --git a/docs/library/axi_dmac/index.rst b/docs/library/axi_dmac/index.rst
@@ -816,3 +816,17 @@ Glossary
        is based on the ``X_LENGTH`` and ``Y_LENGTH`` registers. This can occur
        on AXIS source interfaces when TLAST asserts earlier than the programmed
        length.
+
+Software Support
+--------------------------------------------------------------------------------
+
+* No-OS project at :git-no-OS:`drivers/axi_core/axi_dmac`
+* No-OS device driver at  :git-no-OS:`drivers/axi_core/axi_dmac/axi_dmac.c`
+* No-OS device driver documentation
+  :dokuwiki:`on wiki <resources/tools-software/uc-drivers/jesd204/axi_adxcvr>`
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/axi_dmac`
+* :dokuwiki:`High-Speed DMA Controller Peripheral on wiki <resources/fpga/docs/axi_dmac>`
diff --git a/docs/library/axi_fan_control/index.rst b/docs/library/axi_fan_control/index.rst
@@ -259,6 +259,6 @@ Register Map
 References
 --------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_fan_control`
-* :git-linux:`/`
+* HDL IP core at :git-hdl:`library/axi_fan_control`
+* :dokuwiki:`AXI FAN CONTROL on wiki <resources/fpga/docs/axi_fan_control>`
 * :xilinx:`7 Series libraries <support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf>`
diff --git a/docs/library/axi_hdmi_rx/index.rst b/docs/library/axi_hdmi_rx/index.rst
@@ -128,7 +128,9 @@ The core can be controlled by no-Os or Linux
 References
 -------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_hdmi_rx`
-* :git-hdl:`projects/imageon`
+* HDL IP core at :git-hdl:`library/axi_hdmi_rx`
+* HDL project at :git-hdl:`projects/imageon`
+* HDL project documentation at :ref:`imageon`
+* :dokuwiki:`AXI HDMI RX on wiki <resources/fpga/docs/axi_hdmi_rx>`
 * :dokuwiki:`FMC-IMAGEON Xilinx Reference Design <resources/fpga/xilinx/fmc/fmc-imageon>`
 * :dokuwiki:`Zynq & Altera SoC Quick Start Guide <resources/tools-software/linux-software/kuiper-linux>`
diff --git a/docs/library/axi_hdmi_tx/index.rst b/docs/library/axi_hdmi_tx/index.rst
@@ -205,7 +205,8 @@ The core can be controlled by no-Os or Linux
 References
 -------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_hdmi_tx`
+* HDL IP core at :git-hdl:`library/axi_hdmi_tx`
+* :dokuwiki:`AXI HDMI TX on wiki <resources/fpga/docs/axi_hdmi_tx>`
 * :dokuwiki:`Zynq & Altera SoC Quick Start Guide <resources/tools-software/linux-software/kuiper-linux>`
 * :dokuwiki:`FMC-IMAGEON Xilinx Reference Design <resources/fpga/xilinx/fmc/fmc-imageon>`
 * :dokuwiki:`ADV7511 Xilinx Evaluation Boards Reference Design <resources/fpga/xilinx/kc705/adv7511>`
diff --git a/docs/library/axi_laser_driver/index.rst b/docs/library/axi_laser_driver/index.rst
@@ -79,3 +79,9 @@ Register Map
 
 .. hdl-regmap::
    :name: AXI_LASER_DRIVER 
+
+References
+-------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/axi_laser_driver`
+* :dokuwiki:`AXI Laser Driver on wiki <resources/fpga/docs/axi_laser_driver>`
diff --git a/docs/library/axi_logic_analyzer/index.rst b/docs/library/axi_logic_analyzer/index.rst
@@ -120,8 +120,8 @@ Register Map
 References
 --------------------------------------------------------------------------------
 
-* :git-hdl:`library/axi_logic_analyzer`
-* :git-linux:`/`
+* HDL IP core at :git-hdl:`library/axi_logic_analyzer`
+* :dokuwiki:`AXI LOGIC ANALYZER on wiki <resources/fpga/docs/axi_logic_analyzer>`
 * :xilinx:`7 Series IO <support/documentation/user_guides/ug471_7Series_SelectIO.pdf>`
 * :xilinx:`7 Series Clocking <support/documentation/user_guides/ug472_7Series_Clocking.pdf>`
 * :xilinx:`7 Series libraries <support/documentation/sw_manuals/xilinx2016_2/ug953-vivado-7series-libraries.pdf>`
diff --git a/docs/library/axi_pwm_gen/index.rst b/docs/library/axi_pwm_gen/index.rst
@@ -280,3 +280,9 @@ Register Map
 
 .. hdl-regmap::
    :name: axi_pwm_gen
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/axi_pwm_gen`
+* :dokuwiki:`AXI PWM GEN on wiki <resources/fpga/docs/axi_pwm_gen>`
diff --git a/docs/library/axi_sysid/index.rst b/docs/library/axi_sysid/index.rst
@@ -240,3 +240,15 @@ the information that will be written to the "Custom String" areas.
 
    set sys_cstring "sys rom custom string placeholder"
    sysid_gen_sys_init_file $sys_cstring
+
+Software Support
+--------------------------------------------------------------------------------
+
+* No-OS project at :git-no-OS:`drivers/axi_core/axi_sysid`
+* No-OS device driver at  :git-no-OS:`drivers/axi_core/axi_sysid/axi_sysid.c`
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/axi_sysid` and :git-hdl:`library/sysid_rom`
+* :dokuwiki:`System ID on wiki <resources/fpga/docs/axi_sysid>`
diff --git a/docs/library/axi_tdd/index.rst b/docs/library/axi_tdd/index.rst
@@ -190,3 +190,9 @@ Register Map
 
 .. hdl-regmap::
    :name: TDDN_CNTRL
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/axi_tdd`
+* :dokuwiki:`Generic Time-Division Duplexing Controller on wiki <resources/fpga/docs/axi_tdd>`
diff --git a/docs/library/common/ad_dds/index.rst b/docs/library/common/ad_dds/index.rst
@@ -324,3 +324,10 @@ It should be mentioned that after the phase init fall-edge, until the first
 valid sample, there is a delay caused by the phase to angle converter type and
 in the case of the CORDIC type, the number of rotation stages will also have a
 direct impact on this clock period delay.
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/common/ad_dds.v` and :git-hdl:`library/common/ad_dds_1.v`
+  and :git-hdl:`library/common/ad_dds_2.v` 
+* :dokuwiki:`Direct digital synthesis on wiki <resources/fpga/docs/dds>`
diff --git a/docs/library/corundum/index.rst b/docs/library/corundum/index.rst
@@ -64,7 +64,7 @@ and it needs to be cloned alongside this repository.
 References
 --------------------------------------------------------------------------------
 
-* :adi:`AD-GMSL2ETH-SL`
+* HDL IP core at :git-hdl:`library/corundum`
+* HDL project at :git-hdl:`projects/ad_gmsl2eth_sl`
 * :ref:`ad_gmsl2eth_sl`
-* :git-hdl:`projects/ad_gmsl2eth_sl`
-* :git-hdl:`library/corundum`
+* :adi:`AD-GMSL2ETH-SL`
diff --git a/docs/library/data_offload/index.rst b/docs/library/data_offload/index.rst
@@ -489,3 +489,9 @@ The latter is addressed by the integration into
 which allow the drivers to control the oneshot functionality of the data offload
 based on what was requested with the current IIO buffer, assuming that bypass
 was disabled.
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/data_offload`
+* :dokuwiki:`Data Offload Engine on wiki <resources/fpga/docs/data_offload>`
diff --git a/docs/library/i3c_controller/index.rst b/docs/library/i3c_controller/index.rst
@@ -39,10 +39,15 @@ Interfaces
 * :ref:`i3c_controller offload-interface`: Command descriptors for cyclic operation,
   with SDI data generally consumed by a DMA.
 
-Software
+Software support
 --------------------------------------------------------------------------------
 
 * :git-linux:`Linux Driver <i3c:drivers/i3c/master/adi-i3c-master.c>`:
   Linux driver for the I3C Controller.
 * :ref:`i3c_controller instruction-format`: Overview of the I3C Controller
   instruction format.
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/i3c_controller`
diff --git a/docs/library/jesd204/index.rst b/docs/library/jesd204/index.rst
@@ -480,3 +480,16 @@ JESD204B Clocking Solutions
    JESD204B/JESD204C
 -  :adi:`ADF 4371 <en/products/ADF4371>`: Microwave Wideband Synthesizer
    with Integrated VCO
+
+Software Support
+--------------------------------------------------------------------------------
+
+* No-OS JESD204 project at :git-no-OS:`jesd204`
+* Linux JESD204 project at :git-linux:`drivers/jesd204`
+* Linux JESD204 IIO project at :git-linux:`drivers/iio/jesd204`
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/jesd204`
+* :dokuwiki:`JESD204 Interface Framework on wiki <resources/fpga/peripherals/jesd204>`
diff --git a/docs/library/spi_engine/index.rst b/docs/library/spi_engine/index.rst
@@ -96,3 +96,17 @@ Additional Resources
 * :download:`Presentation: SPI Engine Design Philosophy <https://wiki.analog.com/_media/resources/fpga/peripherals/spi-engine3.pdf>`.
 * :ref:`spi_engine pipeline-delays`
 * :ref:`spi_engine tutorial`.
+
+Software Support
+--------------------------------------------------------------------------------
+
+* No-OS project at :git-no-OS:`drivers/axi_core/spi_engine`
+* No-OS driver at :git-no-OS:`drivers/axi_core/spi_engine/spi_engine.c`
+* Linux project at :git-linux:`drivers/spi`
+* Linux driver at :git-linux:`drivers/spi/spi-axi-spi-engine.c`
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/spi_engine`
+* :dokuwiki:`SPI Engine on wiki <resources/fpga/peripherals/spi_engine>`
diff --git a/docs/library/util_axis_fifo/index.rst b/docs/library/util_axis_fifo/index.rst
@@ -124,3 +124,10 @@ logic:
    should take this into account when controlling the data stream into and from the
    FIFO. Carefully adjusting the ALMOST_EMPTY/ALMOST_FULL indicators can provide a
    safe operating margin.
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/util_axis_fifo`
+* :dokuwiki:`AXI Stream FIFO Core on wiki <resources/fpga/docs/util_axis_fifo>`
+* :dokuwiki:`Asymmetric AXI Stream FIFO Core on wiki <resources/fpga/docs/util_axis_fifo_asym>`
diff --git a/docs/library/util_axis_fifo_asym/index.rst b/docs/library/util_axis_fifo_asym/index.rst
@@ -167,3 +167,15 @@ ADDRESS_WIDTH, FIFO_LIMITED and ADDRESS_WIDTH_PERSPECTIVE:
   address specified is from the perspective of the Slave interface. Since
   the limit is disable the FIFO size will remain the same if the S_DATA_WIDTH
   is < M_DATA_WIDTH, leading to a bigger FIFO implementation.
+
+Software Support
+--------------------------------------------------------------------------------
+
+* Linux project at :git-linux:`drivers/staging/axis-fifo`
+* Linux driver at :git-linux:`drivers/staging/axis-fifo/axis-fifo.c`
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/util_axis_fifo_asym`
+* :dokuwiki:`Asymmetric AXI Stream FIFO Core on wiki <resources/fpga/docs/util_axis_fifo_asym>`
diff --git a/docs/library/util_extract/index.rst b/docs/library/util_extract/index.rst
diff --git a/docs/library/util_mii_to_rmii/index.rst b/docs/library/util_mii_to_rmii/index.rst
diff --git a/docs/library/util_pack/util_cpack2.rst b/docs/library/util_pack/util_cpack2.rst
diff --git a/docs/library/util_pack/util_upack2.rst b/docs/library/util_pack/util_upack2.rst
diff --git a/docs/library/util_rfifo/index.rst b/docs/library/util_rfifo/index.rst
diff --git a/docs/library/util_var_fifo/index.rst b/docs/library/util_var_fifo/index.rst
diff --git a/docs/library/util_wfifo/index.rst b/docs/library/util_wfifo/index.rst
