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ad4062: coraz7s: Add project
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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‎projects/ad4062_ardz/Makefile

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####################################################################################
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## Copyright (c) 2018 - 2025 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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include ../scripts/project-toplevel.mk

‎projects/ad4062_ardz/README.md

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# AD4062-ARDZ HDL Project
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- Evaluation board product page: [EVAL-AD4060/EVAL-AD4062](https://www.analog.com/eval-ad4060-eval-ad4062)
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- System documentation:TO BE ADDED
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- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad4062_ardz/index.html
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## Supported parts
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| Part name | Description |
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|--------------------------------------------|------------------------------------------------------------|
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| [AD4060](https://www.analog.com/ad4060) | Compact, Low Power, 12-Bit, 2 MSPS kSPS Easy Drive SAR ADC |
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| [AD4062](https://www.analog.com/ad4062) | Compact, Low Power, 16-Bit, 2 MSPS kSPS Easy Drive SAR ADC |
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## Building the project
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Please enter the folder for the FPGA carrier you want to use and read the README.md.

‎projects/ad4062_ardz/common/ad4062_bd.tcl

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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create_bd_intf_port -mode Master -vlnv analog.com:interface:i3c_controller_rtl:1.0 i3c
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source $ad_hdl_dir/library/i3c_controller/scripts/i3c_controller_bd.tcl
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set async_clk 0
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set i2c_mod 4
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set offload $ad_project_params(OFFLOAD)
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set max_devs 16
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i3c_controller_create i3c $async_clk $i2c_mod $offload $max_devs
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if {$offload == 1} {
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# pwm to trigger on offload data burst
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ad_ip_instance axi_pwm_gen i3c_offload_pwm
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ad_ip_parameter i3c_offload_pwm CONFIG.PULSE_0_PERIOD 120
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ad_ip_parameter i3c_offload_pwm CONFIG.PULSE_0_WIDTH 1
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# dma to receive offload data stream
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ad_ip_instance axi_dmac i3c_offload_dma
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter i3c_offload_dma CONFIG.CYCLIC 0
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ad_ip_parameter i3c_offload_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter i3c_offload_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter i3c_offload_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter i3c_offload_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect sys_cpu_clk i3c_offload_pwm/ext_clk
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ad_connect sys_cpu_clk i3c_offload_pwm/s_axi_aclk
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ad_connect sys_cpu_resetn i3c_offload_pwm/s_axi_aresetn
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ad_connect i3c_offload_pwm/pwm_0 i3c/trigger
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ad_connect i3c_offload_dma/s_axis i3c/offload_sdi
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}
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ad_connect i3c/m_i3c i3c
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ad_connect sys_cpu_clk i3c/clk
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ad_connect sys_cpu_resetn i3c/reset_n
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if {$offload == 1} {
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ad_connect sys_cpu_clk i3c_offload_dma/s_axis_aclk
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ad_connect sys_cpu_resetn i3c_offload_dma/m_dest_axi_aresetn
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}
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ad_cpu_interconnect 0x44a00000 i3c/host_interface
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if {$offload == 1} {
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ad_cpu_interconnect 0x44a30000 i3c_offload_dma
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ad_cpu_interconnect 0x44b00000 i3c_offload_pwm
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}
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if {$offload == 1} {
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ad_cpu_interrupt "ps-13" "mb-13" i3c_offload_dma/irq
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}
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ad_cpu_interrupt "ps-12" "mb-12" i3c/irq
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if {$offload == 1} {
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ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect sys_cpu_clk i3c_offload_dma/m_dest_axi
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}

‎projects/ad4062_ardz/coraz7s/Makefile

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####################################################################################
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## Copyright (c) 2018 - 2025 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad4062_ardz_coraz7s
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M_DEPS += ../common/ad4062_bd.tcl
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M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
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M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
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M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
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M_DEPS += ../../../library/i3c_controller/scripts/i3c_controller_bd.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_pwm_gen
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LIB_DEPS += axi_sysid
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LIB_DEPS += i3c_controller/i3c_controller_core
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LIB_DEPS += i3c_controller/i3c_controller_host_interface
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LIB_DEPS += sysid_rom
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include ../../scripts/project-xilinx.mk

‎projects/ad4062_ardz/coraz7s/README.md

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# AD4062-ARDZ/CORAZ7S HDL Project
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## Building the project
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```
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cd projects/ad4062_ardz/coraz7s
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make
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```

‎projects/ad4062_ardz/coraz7s/system_bd.tcl

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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# Remove common IIC interface to add I3C controller
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delete_bd_objs [get_bd_intf_nets axi_iic_ard_IIC] [get_bd_intf_ports iic_ard]
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delete_bd_objs [get_bd_nets axi_iic_ard_iic2intc_irpt] [get_bd_intf_nets axi_gp0_interconnect_M00_AXI] [get_bd_cells axi_iic_ard]
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source ../common/ad4062_bd.tcl
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path";
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file

‎projects/ad4062_ardz/coraz7s/system_constr.xdc

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports adc_gp0]
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set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports adc_gp1]
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# clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
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set i3c_clk clk_fpga_0
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# Input data driven the peripherals toggles every 4 cycles max (PP) of the capture clock
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# gets registered by rx_reg
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set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -setup 4
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set_multicycle_path -from [get_ports i3c_sda] -to [get_clocks $i3c_clk] -hold 3
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# Output data toggles every 2 cycles max of the capture clock (PP)
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set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -setup 2
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set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_sda] -hold 1
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set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -setup 2
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set_multicycle_path -from [get_clocks $i3c_clk] -to [get_ports i3c_scl] -hold 1
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# Notes
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# tcr/tcf rising/fall time for SCL is 150e06 * 1 / fSCL, at fSCL = 12.5 MHz => 12ns, at fSCL = 6.25 MHz, 24ns.
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# and t_SCO has a minimum/default value of 8ns and max of 12 ns
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# The input_delay and output_delay are selected for the worst case scenario.
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# One i3c_clk clock cycle is included in the sdo signal to ensure thd_pp(min) is met.
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set tsco_max 12;
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set tsco_min 8;
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set trc_dly_max 1;
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set trc_dly_min 0;
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set_input_delay -clock $i3c_clk -max [expr $tsco_max + $trc_dly_max] [get_ports i3c_sda]
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set_input_delay -clock $i3c_clk -min [expr $tsco_min + $trc_dly_min] [get_ports i3c_sda]
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set tsu 2;
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set thd 0;
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set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_sda]
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set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_sda]
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set_output_delay -clock $i3c_clk -max [expr $trc_dly_max + $tsu] [get_ports i3c_scl]
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set_output_delay -clock $i3c_clk -min [expr $trc_dly_min - $thd] [get_ports i3c_scl]

‎projects/ad4062_ardz/coraz7s/system_project.tcl

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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# get_env_param retrieves parameter value from the environment if exists,
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# other case use the default value.
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#
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# How to use over-writable parameters from the environment:
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#
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# e.g.
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# make OFFLOAD=1
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#
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# Parameter description:
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#
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# OFFLOAD : Enable offload mode, includes AXI_DMAC and AXI_PWM to the design
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# 1 - enabled
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# 0 - disabled (default)
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adi_project ad4062_ardz_coraz7s 0 [list \
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OFFLOAD [get_env_param OFFLOAD 0]]
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adi_project_files ad4062_ardz_coraz7s [list \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
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adi_project_run ad4062_ardz_coraz7s

‎projects/ad4062_ardz/coraz7s/system_top.v

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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [ 1:0] btn,
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inout [ 5:0] led,
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output iic_ard_scl,
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inout iic_ard_sda,
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inout adc_gp1,
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inout adc_gp0
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);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire i3c_sdo;
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wire i3c_sdi;
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wire i3c_t;
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// instantiations
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assign gpio_i[31:8] = gpio_o[31:8];
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assign gpio_i[63:34] = gpio_o[63:34];
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iobuf_gp (
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.dio_t(gpio_t[33:32]),
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.dio_i(gpio_o[33:32]),
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.dio_o(gpio_i[33:32]),
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.dio_p({adc_gp1, // device ready then ~data ready
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adc_gp0})); // threshold event
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_iobuf_sda (
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.dio_t(i3c_t),
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.dio_i(i3c_sdo),
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.dio_o(i3c_sdi),
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.dio_p(iic_ard_sda));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iobuf_buttons (
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.dio_t(gpio_t[1:0]),
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.dio_i(gpio_o[1:0]),
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.dio_o(gpio_i[1:0]),
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.dio_p(btn));
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ad_iobuf #(
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.DATA_WIDTH(6)
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) i_iobuf_leds (
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.dio_t(gpio_t[7:2]),
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.dio_i(gpio_o[7:2]),
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.dio_o(gpio_i[7:2]),
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.dio_p(led));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (),
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.spi0_csn_0_o (),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (1'b0),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o (),
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.i3c_scl (iic_ard_scl),
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.i3c_sdi (i3c_sdi),
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.i3c_sdo (i3c_sdo),
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.i3c_t (i3c_t));
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endmodule

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