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library/corundum/ethernet: Changed IP creation to be in subfolders
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
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docs/library/corundum/corundum_core/index.rst

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@@ -74,4 +74,4 @@ repository, which needs to be cloned alongside the HDL repository.
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References
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--------------------------------------------------------------------------------
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* HDL IP core at :git-hdl:`library/corundum`
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* HDL IP core at :git-hdl:`library/corundum/corundum_core`

docs/library/corundum/ethernet/index.rst

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@@ -3,7 +3,10 @@
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Corundum Ethernet Core
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================================================================================
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.. hdl-component-diagram::
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.. toctree::
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:hidden:
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VCU118 <vcu118/index>
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The :git-hdl:`Corundum Ethernet Core <library/corundum/ethernet_core>` is used
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by the Corundum Network Stack. The Ethernet Core is specific to each FPGA board
@@ -12,6 +15,11 @@ as SPI and I2C that are required by the Corundum system. The configurations are
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based on `Corundum NIC <https://github.com/ucsdsysnet/corundum>`__ reference
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designs that were adapted to suit the ADI workflow.
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Depending on the board for which the IP is built, different HDL component
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diagrams will be available.
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* :ref:`corundum_ethernet_core_vcu118`
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Features
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--------------------------------------------------------------------------------
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@@ -21,25 +29,20 @@ Features
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/corundum/ethernet_core/ethernet_core_vcu118.v`
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- Verilog source for the Ethernet Core top module for the VCU118 board.
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* - :git-hdl:`library/corundum/ethernet_core/eternet_ip.tcl`
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- TCL script to generate the Vivado IP-integrator project.
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Depending on the board for which the IP is built, different source files will
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be available.
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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Depending on the board for which the IP is built, different HDL parameters will
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be available.
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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Depending on the board for which the IP is built, different HDL interfaces and
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ports will be available.
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Building
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--------------------------------------------------------------------------------
@@ -104,4 +107,4 @@ appropriate configuration.
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References
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--------------------------------------------------------------------------------
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* HDL IP core at :git-hdl:`library/corundum`
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* HDL IP core at :git-hdl:`library/corundum/ethernet`
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.. _corundum_ethernet_core_vcu118:
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Corundum Ethernet Core for VCU118
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================================================================================
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.. hdl-component-diagram::
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/corundum/ethernet_core/ethernet_core_vcu118.v`
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- Verilog source for the Ethernet Core top module for the VCU118 board.
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* - :git-hdl:`library/corundum/ethernet_core/eternet_ip.tcl`
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- TCL script to generate the Vivado IP-integrator project.
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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Interface
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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References
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--------------------------------------------------------------------------------
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* HDL IP core at :git-hdl:`library/corundum/ethernet_core`

library/corundum/ethernet/ethernet_ip.tcl

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@@ -8,10 +8,15 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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global VIVADO_IP_LIBRARY
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adi_ip_create ethernet
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if [info exists ::env(BOARD)] {
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set board $::env(BOARD)
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set board_lowercase [string tolower $board]
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set ethernet_ip "ethernet_${board_lowercase}"
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adi_ip_create $ethernet_ip $board_lowercase
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cd ./$board_lowercase
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if [string equal $board VCU118] {
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set_property part xcvu9p-flga2104-2L-e [current_project]
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@@ -20,7 +25,7 @@ if [info exists ::env(BOARD)] {
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# Corundum sources
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adi_ip_files ethernet_core_vcu118 [list \
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"ethernet_core_vcu118.v" \
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"../ethernet_core_vcu118.v" \
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"$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/rtl/sync_signal.v" \
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"$ad_hdl_dir/../corundum/fpga/common/rtl/mqnic_port_map_mac_axis.v" \
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"$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v" \
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error "Missing BOARD environment variable definition from Makefile!"
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}
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adi_ip_properties_lite ethernet
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set_property company_url {https://analogdevicesinc.github.io/hdl/library/corundum} [ipx::current_core]
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adi_ip_properties_lite $ethernet_ip
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set cc [ipx::current_core]
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set_property display_name "Corundum Ethernet" $cc
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set_property display_name "Corundum Ethernet $board" $cc
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set_property description "Corundum Ethernet Core IP" $cc
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set_property company_url {https://analogdevicesinc.github.io/hdl/library/corundum} [ipx::current_core]
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# Remove all inferred interfaces and address spaces
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ipx::remove_all_bus_interface [ipx::current_core]

library/corundum/scripts/corundum.tcl

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@@ -196,7 +196,9 @@ ad_ip_instance corundum_core corundum_core [list \
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AXIS_IF_RX_USER_WIDTH_APP $AXIS_IF_RX_USER_WIDTH_APP \
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]
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ad_ip_instance ethernet ethernet_core [list \
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set board [string tolower $::env(BOARD)]
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ad_ip_instance ethernet_${board} ethernet_core [list \
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TDMA_BER_ENABLE $TDMA_BER_ENABLE \
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QSFP_CNT $QSFP_CNT \
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IF_COUNT $IF_COUNT \

library/scripts/adi_ip_xilinx.tcl

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@@ -253,7 +253,7 @@ proc adi_ip_add_core_dependencies {vlnvs} {
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#
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# \param[ip_name] - IP name
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#
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proc adi_ip_create {ip_name} {
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proc adi_ip_create {ip_name {folder_name {}}} {
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global ad_hdl_dir
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global ad_ghdl_dir
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}
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}
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create_project $ip_name . -force
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if {$folder_name == {}} {
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create_project $ip_name . -force
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} else {
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create_project $ip_name $folder_name -force
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}
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## Load custom message severity definitions
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