ad485x_fmcz: Add project README

Signed-off-by: Stanca Pop <stanca.pop@analog.com>

Author: StancaPop

projects/ad485x_fmcz/README.md

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+# AD485X-FMCZ HDL Project
+
+- Evaluation boards product pages:
+  - [EVAL-AD4857](https://www.analog.com/eval-ad4857)
+  - [EVAL-AD4858](https://www.analog.com/eval-ad4858)
+
+- System documentation: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
+- HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/ad585x_fmcz/index.html
+- Evaluation board VADJ range: 1.8V - 3.3V
+
+:warning: Make sure the power supplies on the evaluation board are configured as expected, from jumper selection. In particular, pay attention to JVIO to be equal to VADJ, otherwise you risk damaging the FPGA and EVAL-AD485x board.
+
+## Supported parts
+
+| Part name                               | Resolution | Description                                      |
+|-----------------------------------------|:----------:|--------------------------------------------------|
+| [AD4851](https://www.analog.com/ad4851) | 16-bit     | Buffered, 4-Channel Simultaneous Sampling, 250kSPS DAS |
+| [AD4852](https://www.analog.com/ad4852) | 20-bit     | Buffered, 4-Channel Simultaneous Sampling, 250kSPS DAS |
+| [AD4853](https://www.analog.com/ad4853) | 16-bit     | Buffered, 4-Channel Simultaneous Sampling, 1MSPS DAS |
+| [AD4854](https://www.analog.com/ad4854) | 20-bit     | Buffered, 4-Channel Simultaneous Sampling, 1MSPS DAS|
+| [AD4855](https://www.analog.com/ad4855) | 16-bit     | Buffered, 8-Channel Simultaneous Sampling, 250 kSPS DAS |
+| [AD4856](https://www.analog.com/ad4856) | 20-bit     | Buffered, 8-Channel Simultaneous Sampling, 250 kSPS DAS|
+| [AD4857](https://www.analog.com/ad4857) | 16-bit     | Buffered, 8-Channel Simultaneous Sampling, 1 MSPS DAS |
+| [AD4858](https://www.analog.com/ad4858) | 20-bit     | Buffered, 8-Channel Simultaneous Sampling, 1 MSPS DAS |
+
+## Building the project
+
+Please enter the folder for the FPGA carrier you want to use and read the README.md.

projects/ad485x_fmcz/Readme.md

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+<!-- no_no_os, no_dts -->
+
+# AD485X-FMCZ/ZED HDL Project
+
+- VADJ with which it was tested in hardware: 2.5V
+
+## Building the project
+
+The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
+
+```
+cd projects/ad485x/zed
+make
+```
+
+The overwritable parameters from the environment are:
+
+- LVDS_CMOS_N - selects the interface type to be used:
+  - 0 - CMOS interface (default)
+  - 1 - LVDS interface
+  
+- THREE_W_SPI - selects the SPI configuration to be used:
+  - 0 - 4 wire SPI (default)
+  - 1 - 3 wire SPI
+  
+- DEVICE - selects the device to be used:
+  - AD4857
+  - AD4858 (default)
+
+### Example configurations
+
+#### Configuration using CMOS interface, 4 wire SPI (default)
+
+Connect the evaluation board FMC to the FMC connector of Zedboard.
+
+This specific command is equivalent to running "make" only:
+
+```
+make LVDS_CMOS_N=0 THREE_W_SPI=0
+```
+
+#### Configurations using LVDS interface
+
+To build the LVDS interface - 4 wire SPI:
+
+```
+make LVDS_CMOS_N=1 THREE_W_SPI=0
+```
+
+To build the LVDS interface - 3 wire SPI:
+
+```
+make LVDS_CMOS_N=1 THREE_W_SPI=1
+```
+
+#### Configurations using LVDS interface
+
+To build a specific part configuration:
+
+```
+make DEVICE=AD4851
+```