docs/library/corundum: Add K26 support

Signed-off-by: alin724 <alin-tudor.sferle@analog.com>

Author: alin724

docs/library/corundum/ethernet/index.rst

@@ -8,6 +8,8 @@ Corundum Ethernet Core
 
    VCU118 <vcu118/index>
 
+   K26 <k26/index>
+
 The :git-hdl:`Corundum Ethernet Core <library/corundum/ethernet_core>` is used
 by the Corundum Network Stack. The Ethernet Core is specific to each FPGA board
 and encompasses the Ethernet physical layer and other auxiliary structures such
@@ -19,12 +21,12 @@ Depending on the board for which the IP is built, different HDL component
 diagrams will be available.
 
 * :ref:`corundum_ethernet_core_vcu118`
+* :ref:`corundum_ethernet_core_k26`
 
 Features
 --------------------------------------------------------------------------------
 
-* Supports 100G Ethernet-based systems that uses the CMAC core on the VCU118
-  board
+* Supports 10/100 GbE implementations as follows: 100 GbE by leveraging on the Xilinx's CMAC IP core (on the VCU118 evaluation kit) and 10 GbE by using the Corundum's support (on the K26-based AD-GMSL2ETH-SL evaluation kit).
 
 Files
 --------------------------------------------------------------------------------

docs/library/corundum/ethernet/k26/index.rst

@@ -0,0 +1,34 @@
+.. _corundum_ethernet_core_k26:
+
+Corundum Ethernet Core for K26
+================================================================================
+
+.. hdl-component-diagram::
+
+Files
+--------------------------------------------------------------------------------
+
+.. list-table::
+   :header-rows: 1
+
+   * - Name
+     - Description
+   * - :git-hdl:`library/corundum/ethernet_core/ethernet_core_k26.v`
+     - Verilog source for the Ethernet Core top module for the K26-based AD-GMSL2ETH-SL evaluation kit.
+   * - :git-hdl:`library/corundum/ethernet_core/ethernet_ip.tcl`
+     - TCL script to generate the Vivado IP-integrator project.
+
+Configuration Parameters
+--------------------------------------------------------------------------------
+
+.. hdl-parameters::
+
+Interface
+--------------------------------------------------------------------------------
+
+.. hdl-interfaces::
+
+References
+--------------------------------------------------------------------------------
+
+* HDL IP core at :git-hdl:`library/corundum/ethernet_core`

docs/library/corundum/ethernet/vcu118/index.rst

@@ -15,7 +15,7 @@ Files
      - Description
    * - :git-hdl:`library/corundum/ethernet_core/ethernet_core_vcu118.v`
      - Verilog source for the Ethernet Core top module for the VCU118 board.
-   * - :git-hdl:`library/corundum/ethernet_core/eternet_ip.tcl`
+   * - :git-hdl:`library/corundum/ethernet_core/ethernet_ip.tcl`
      - TCL script to generate the Vivado IP-integrator project.
 
 Configuration Parameters