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ada4355: Functional calibration
Detect when it is encounter a frame or data error. Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
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6 files changed

+217
-28
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6 files changed

+217
-28
lines changed

‎library/axi_ada4355/Makefile

+3
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,10 @@ GENERIC_DEPS += ../common/up_xfer_cntrl.v
1818
GENERIC_DEPS += ../common/up_xfer_status.v
1919
GENERIC_DEPS += axi_ada4355.v
2020
GENERIC_DEPS += axi_ada4355_if.v
21+
GENERIC_DEPS += axi_ada4355_regmap.v
2122

23+
XILINX_DEPS += axi_ada4355_constr.ttcl
24+
XILINX_DEPS += ../util_cdc/sync_bits.v
2225
XILINX_DEPS += ../xilinx/common/ad_data_clk.v
2326
XILINX_DEPS += ../xilinx/common/ad_data_in.v
2427
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v

‎library/axi_ada4355/axi_ada4355.v

+35-9
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,10 @@ module axi_ada4355 #(
6262

6363
input delay_clk,
6464

65+
// error monitoring
66+
67+
output up_adc_pn_err,
68+
6569
// AXI interface
6670

6771
input s_axi_aclk,
@@ -102,6 +106,10 @@ module axi_ada4355 #(
102106
wire adc_clk_s;
103107
wire adc_rst_s;
104108
wire delay_rst;
109+
wire adc_pn_err_s;
110+
wire up_adc_pn_err_s;
111+
wire up_adc_pn_oos_s;
112+
wire [ 2:0] enable_error_s;
105113

106114
wire up_rstn;
107115
wire up_clk;
@@ -111,9 +119,9 @@ module axi_ada4355 #(
111119
wire up_wr_s;
112120
wire [13:0] up_addr_s;
113121
wire [31:0] up_wdata_s;
114-
wire [31:0] up_rdata_s [0:2];
115-
wire up_rack_s [0:2];
116-
wire up_wack_s [0:2];
122+
wire [31:0] up_rdata_s [0:3];
123+
wire up_rack_s [0:3];
124+
wire up_wack_s [0:3];
117125

118126
reg [31:0] up_rdata_r;
119127
reg up_rack_r;
@@ -127,12 +135,13 @@ module axi_ada4355 #(
127135
assign adc_clk = adc_clk_s;
128136
assign up_clk = s_axi_aclk;
129137
assign up_rstn = s_axi_aresetn;
138+
assign up_adc_pn_err = up_adc_pn_err_s;
130139

131140
always @(*) begin
132141
up_rdata_r = 'h00;
133142
up_rack_r = 'h00;
134143
up_wack_r = 'h00;
135-
for(j = 0; j <= 2; j=j+1) begin
144+
for(j = 0; j <= 3; j=j+1) begin
136145
up_rack_r = up_rack_r | up_rack_s[j];
137146
up_wack_r = up_wack_r | up_wack_s[j];
138147
up_rdata_r = up_rdata_r | up_rdata_s[j];
@@ -168,15 +177,15 @@ module axi_ada4355 #(
168177
.adc_iqcor_coeff_2(),
169178
.adc_pnseq_sel(),
170179
.adc_data_sel(),
171-
.adc_pn_err(1'b0),
180+
.adc_pn_err(adc_pn_err_s),
172181
.adc_pn_oos(1'b0),
173182
.adc_or(),
174183
.adc_read_data(),
175184
.adc_status_header('b0),
176185
.adc_crc_err('b0),
177186
.up_adc_crc_err(),
178-
.up_adc_pn_err(),
179-
.up_adc_pn_oos(),
187+
.up_adc_pn_err(up_adc_pn_err_s),
188+
.up_adc_pn_oos(up_adc_pn_oos_s),
180189
.up_adc_or(),
181190
.up_usr_datatype_be(),
182191
.up_usr_datatype_signed(),
@@ -224,8 +233,8 @@ module axi_ada4355 #(
224233
.up_pps_status(1'b0),
225234
.up_pps_irq_mask(),
226235
.up_adc_ce(),
227-
.up_status_pn_err(1'b0),
228-
.up_status_pn_oos(1'b0),
236+
.up_status_pn_err(up_adc_pn_err_s),
237+
.up_status_pn_oos(up_adc_pn_oos_s),
229238
.up_status_or(1'b0),
230239
.up_drp_sel(),
231240
.up_drp_wr(),
@@ -279,6 +288,8 @@ module axi_ada4355 #(
279288
.adc_data(adc_data),
280289
.adc_valid(adc_valid),
281290
.aresetn(up_rstn),
291+
.adc_pn_err(adc_pn_err_s),
292+
.enable_error(enable_error_s),
282293
.sync_n(sync_n));
283294

284295
// adc delay control
@@ -305,6 +316,21 @@ module axi_ada4355 #(
305316
.up_rdata(up_rdata_s[2]),
306317
.up_rack(up_rack_s[2]));
307318

319+
axi_ada4355_regmap i_regmap(
320+
.up_rstn(up_rstn),
321+
.up_clk(up_clk),
322+
.up_wreq(up_wreq_s),
323+
.up_waddr(up_waddr_s),
324+
.up_wdata(up_wdata_s),
325+
.up_wack(up_wack_s[3]),
326+
.up_rreq(up_rreq_s),
327+
.up_raddr(up_raddr_s),
328+
.up_rdata(up_rdata_s[3]),
329+
.up_rack(up_rack_s[3]),
330+
.clk_div(adc_clk_s),
331+
.enable_error_sync(enable_error_s),
332+
.adc_rst(adc_rst_s));
333+
308334
// up bus interface
309335

310336
up_axi i_up_axi(

‎library/axi_ada4355/axi_ada4355_constr.ttcl

+17
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
###############################################################################
2+
## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
3+
# SPDX short identifier: ADIBSD
4+
###############################################################################
5+
6+
<: set ComponentName [getComponentNameString] :>
7+
<: setOutputDirectory "./" :>
8+
<: setFileName [ttcl_add $ComponentName "_constr"] :>
9+
<: setFileExtension ".xdc" :>
10+
<: setFileProcessingOrder late :>
11+
12+
set_property ASYNC_REG TRUE \
13+
[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
14+
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
15+
16+
set_false_path -quiet \
17+
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_enable_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]

‎library/axi_ada4355/axi_ada4355_if.v

+56-19
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,9 @@ module axi_ada4355_if #(
7474

7575
// Output data
7676
output [15:0] adc_data,
77-
output adc_valid
77+
output adc_valid,
78+
output adc_pn_err,
79+
input [ 2:0] enable_error
7880
);
7981

8082
// Use always DDR mode for SERDES, useful for SDR mode to adjust capture
@@ -86,6 +88,8 @@ module axi_ada4355_if #(
8688
FRAME_SHIFTED = 3'h2,
8789
RESET = 3'h3;
8890
localparam [ 7:0] pattern_value = 8'hF0;
91+
localparam [15:0] expected_pattern_lane_0 = 16'h5554;
92+
localparam [15:0] expected_pattern_lane_1 = 16'hAAA8;
8993

9094
wire clk_in_s;
9195
wire out_ibufmrce_clock;
@@ -120,6 +124,7 @@ module axi_ada4355_if #(
120124
reg [ 1:0] serdes_valid = 2'b00;
121125
reg [ 1:0] serdes_valid_d = 2'b00;
122126
reg [ 2:0] shift_cnt = 3'd0;
127+
reg [ 4:0] delay = 5'd0;
123128
reg [15:0] serdes_data;
124129
reg [15:0] serdes_data_d;
125130
reg [ 7:0] serdes_frame;
@@ -130,6 +135,12 @@ module axi_ada4355_if #(
130135
reg bufr_alignment;
131136
reg bufr_alignment_bufr;
132137
reg [ 2:0] state = 3'h0;
138+
reg frame_err_r;
139+
reg data_err_lane_0_r;
140+
reg data_err_lane_1_r;
141+
reg [15:0] lane_0_mask = 16'h5555;
142+
reg [15:0] lane_1_mask = 16'hAAAA;
143+
reg [15:0] test_pattern;
133144

134145
IBUFGDS i_clk_in_ibuf(
135146
.I(dco_p),
@@ -275,38 +286,40 @@ module axi_ada4355_if #(
275286
end
276287

277288
assign adc_clk = adc_clk_div;
289+
assign adc_pn_err = ((data_err_lane_0_r & enable_error[0]) | (data_err_lane_1_r & enable_error[1]) |
290+
(frame_err_r & enable_error[2]));
278291

279292
assign data_in_p = {d1a_p, d0a_p};
280293
assign data_in_n = {d1a_n, d0a_n};
281294

282-
assign {data_0[0],data_1[0]} = data_s0; // f-e latest bit received
283-
assign {data_0[1],data_1[1]} = data_s1; // r-e
284-
assign {data_0[2],data_1[2]} = data_s2; // f-e
285-
assign {data_0[3],data_1[3]} = data_s3; // r-e
286-
assign {data_0[4],data_1[4]} = data_s4; // f-e
287-
assign {data_0[5],data_1[5]} = data_s5; // r-e
288-
assign {data_0[6],data_1[6]} = data_s6; // f-e
289-
assign {data_0[7],data_1[7]} = data_s7; // r-e oldest bit received
295+
assign {data_1[0],data_0[0]} = data_s0; // f-e latest bit received
296+
assign {data_1[1],data_0[1]} = data_s1; // r-e
297+
assign {data_1[2],data_0[2]} = data_s2; // f-e
298+
assign {data_1[3],data_0[3]} = data_s3; // r-e
299+
assign {data_1[4],data_0[4]} = data_s4; // f-e
300+
assign {data_1[5],data_0[5]} = data_s5; // r-e
301+
assign {data_1[6],data_0[6]} = data_s6; // f-e
302+
assign {data_1[7],data_0[7]} = data_s7; // r-e oldest bit received
290303

291304
// For DDR dual lane interleave the two sedres outputs;
292305

293306
always @(posedge adc_clk_div) begin
294-
serdes_data = {data_0[7],
295-
data_1[7],
296-
data_0[6],
307+
serdes_data = {data_1[7],
308+
data_0[7],
297309
data_1[6],
298-
data_0[5],
310+
data_0[6],
299311
data_1[5],
300-
data_0[4],
312+
data_0[5],
301313
data_1[4],
302-
data_0[3],
314+
data_0[4],
303315
data_1[3],
304-
data_0[2],
316+
data_0[3],
305317
data_1[2],
306-
data_0[1],
318+
data_0[2],
307319
data_1[1],
308-
data_0[0],
309-
data_1[0]};
320+
data_0[1],
321+
data_1[0],
322+
data_0[0]};
310323

311324
serdes_frame = {frame_s7,
312325
frame_s6,
@@ -325,6 +338,10 @@ module axi_ada4355_if #(
325338
end
326339
end
327340

341+
always @(posedge adc_clk_div) begin
342+
test_pattern <= adc_data_shifted;
343+
end
344+
328345
always @(posedge adc_clk_div) begin
329346
if (serdes_reset_d) begin
330347
state <= INIT;
@@ -337,10 +354,27 @@ module axi_ada4355_if #(
337354
state <= CNT_UPDATE;
338355
end else begin
339356
frame_shifted <= {serdes_frame, serdes_frame_d} >> shift_cnt;
357+
if (expected_pattern_lane_0 == (test_pattern & lane_0_mask)) begin
358+
data_err_lane_0_r <= 1'b0;
359+
end else begin
360+
data_err_lane_0_r <= 1'b1;
361+
end
362+
if (expected_pattern_lane_1 == (test_pattern & lane_1_mask)) begin
363+
data_err_lane_1_r <= 1'b0;
364+
end else begin
365+
data_err_lane_1_r <= 1'b1;
366+
end
340367
state <= INIT;
341368
end
342369
end
343370
CNT_UPDATE : begin
371+
if (shift_cnt == 3'b111) begin
372+
frame_err_r <= 1'b1;
373+
state <= RESET;
374+
end
375+
else begin
376+
frame_err_r <= 1'b0;
377+
end
344378
shift_cnt <= shift_cnt + 1;
345379
state <= FRAME_SHIFTED;
346380
end
@@ -351,6 +385,9 @@ module axi_ada4355_if #(
351385
RESET : begin
352386
shift_cnt <= 0;
353387
state <= INIT;
388+
frame_err_r <= 1'b0;
389+
data_err_lane_0_r <= 1'b0;
390+
data_err_lane_1_r <= 1'b0;
354391
end
355392
default :
356393
state <= INIT;

‎library/axi_ada4355/axi_ada4355_ip.tcl

+4
Original file line numberDiff line numberDiff line change
@@ -23,14 +23,18 @@ adi_ip_files axi_ada4355 [list \
2323
"$ad_hdl_dir/library/common/up_adc_common.v" \
2424
"$ad_hdl_dir/library/common/up_adc_channel.v" \
2525
"$ad_hdl_dir/library/common/up_axi.v" \
26+
"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
2627
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
2728
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
2829
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
2930
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
31+
"axi_ada4355_constr.ttcl" \
32+
"axi_ada4355_regmap.v" \
3033
"axi_ada4355_if.v" \
3134
"axi_ada4355.v" ]
3235

3336
adi_ip_properties axi_ada4355
37+
adi_ip_ttcl axi_ada4355 "axi_ada4355_constr.ttcl"
3438

3539
adi_ip_add_core_dependencies [list \
3640
analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \

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