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projects/adrv9009zu11eg:Update READMEs with VADJ
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projects/adrv9009zu11eg/README.md

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- Evaluation board product page: [ADRV9009-ZU11EG](https://www.analog.com/adrv9009-zu11eg)
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- System documentation: https://analogdevicesinc.github.io/documentation/eval/user-guide/transceiver/adrv9009/index.html
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- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/adrv9009zu11eg/index.html
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- Evaluation board VADJ: 1.8V
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## Supported parts
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## Building the project
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Please enter the folder for the FPGA carrier you want to use and read the README.md.
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Please enter the folder for the FPGA carrier you want to use and read the README.md.
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<!-- no_no_os -->
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# ADRV9009ZU11EG/ADRV2CRR-FMC HDL Project
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Attach the [ADRV9009ZU11EG](https://www.analog.com/adrv9009-zu11eg) SoM to the mother board [ADRV2CRR-FMC](https://www.analog.com/adrv2crr-fmc).
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- VADJ with which it was tested in hardware: 1.8V
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## Building the project
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```
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If other configurations are desired, then the parameters from the HDL project (found in *adrv2crr_fmc/system_project.tcl*) need to be changed, as well as the Linux/no-OS project configurations.
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The parameters from the environment:
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The overwritable parameters from the environment are:
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- [RX/TX/RX_OS]_JESD_M: [RX/TX/RX_OS] number of converters per link
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- [RX/TX/RX_OS]_JESD_L: [RX/TX/RX_OS] number of lanes per link
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- [RX/TX/RX_OS]_JESD_S: [RX/TX/RX_OS] number of samples per converter per frame
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### Example configurations
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- [RX/TX]_JESD_M: RX: **8** & TX: **8**; [RX/TX] number of converters per link
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- [RX/TX]_JESD_L: RX: **4** & TX: **8**; [RX/TX] number of lanes per link
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- [RX/TX]_JESD_S: RX: **1** & TX: **1**; [RX/TX] number of samples per converter per frame
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- RX_OS_JESD_M: **4**; number of converters per link
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- RX_OS_JESD_L: **4**; number of lanes per link
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- RX_OS_JESD_S: **1**; number of samples per frame
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#### Default configuration
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This specific command is equivalent to running `make` only:
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```
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make RX_JESD_M=8 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=8 \
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TX_JESD_L=8 \
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TX_JESD_S=1 \
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RX_OS_JESD_M=4 \
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RX_OS_JESD_L=4 \
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RX_OS_JESD_S=1
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```
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Corresponding device tree: [zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm.dts)
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Corresponding device tree: [zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm.dts)
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# ADRV9009ZU11EG/ADRV2CRR-FMC HDL Project
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<!-- no_no_os -->
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# ADRV9009ZU11EG/ADRV2CRR-FMCOMMS8 HDL Project
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Aside from the [ADRV9009ZU11EG](https://www.analog.com/adrv9009-zu11eg) SoM attached to the mother board [ADRV2CRR-FMC](https://www.analog.com/adrv2crr-fmc), an extra evaluation board [FMCOMMS8](https://www.analog.com/eval-ad-fmcomms8-ebz) should be attached on the FMC HPC connecter.
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## Building the project
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- VADJ with which it was tested in hardware: 1.8V
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This project is not parameterizable, it has a fixed configuration.
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## Building the project
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```
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cd projects/adrv9009zu11eg/adrv2crr_fmcomms8
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All of the RX/TX link modes can be found in the [ADRV9009 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADRV9009.pdf). We offer support for only a few of them.
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The parameters from the environment:
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The overwritable parameters from the environment are:
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- [RX/TX/RX_OS]_JESD_M: [RX/TX/RX_OS] number of converters per link
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- [RX/TX/RX_OS]_JESD_L: [RX/TX/RX_OS] number of lanes per link
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- [RX/TX/RX_OS]_JESD_S: [RX/TX/RX_OS] number of samples per converter per frame
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### Example configurations
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#### L=8 (default)
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This specific command is equivalent to running `make` only:
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```
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make RX_JESD_M=16 \
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RX_JESD_L=8 \
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RX_JESD_S=1 \
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TX_JESD_M=16 \
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TX_JESD_L=16 \
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TX_JESD_S=1 \
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RX_OS_JESD_M=8 \
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RX_OS_JESD_L=8 \
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RX_OS_JESD_S=1
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```
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Corresponding device tree: [zynqmp-adrv9009-zu11eg-fmcomms8-tx-l8.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-fmcomms8-tx-l8.dts)
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#### L=4
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```
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make RX_JESD_M=4 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=2 \
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TX_JESD_L=4 \
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TX_JESD_S=1 \
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RX_OS_JESD_M=2 \
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RX_OS_JESD_L=4 \
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RX_OS_JESD_S=1
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```
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Corresponding device tree: [zynqmp-adrv9009-zu11eg-fmcomms8-tx-l4-rx-l4-orx-l4.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-fmcomms8-tx-l4-rx-l4-orx-l4.dts)
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#### TX L=8, RX L=4, RX_OS L=4
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- [RX/TX]_JESD_M: RX: **16** & TX: **16**; [RX/TX] number of converters per link
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- [RX/TX]_JESD_L: RX: **8** & TX: **16**; [RX/TX] number of lanes per link
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- [RX/TX]_JESD_S: RX: **1** & TX: **1**; [RX/TX] number of samples per converter per frame
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- RX_OS_JESD_M: **8**; number of converters per link
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- RX_OS_JESD_L: **8**; number of lanes per link
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- RX_OS_JESD_S: **1**; number of samples per frame
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```
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make RX_JESD_M=4 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=4 \
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TX_JESD_L=8 \
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TX_JESD_S=1 \
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RX_OS_JESD_M=2 \
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RX_OS_JESD_L=4 \
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RX_OS_JESD_S=1
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```
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Corresponding device tree: [zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm.dts)
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Corresponding device tree: [zynqmp-adrv9009-zu11eg-fmcomms8-tx-l8-rx-l4-orx-l4.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-fmcomms8-tx-l8-rx-l4-orx-l4.dts)

projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_project.tcl

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RX_OS_JESD_S [get_env_param RX_OS_JESD_S 1 ] \
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] "xczu11eg-ffvf1517-2-i"
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adi_project_files fmcomms8_adrv9009zu11eg [list \
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"system_top.v" \
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"fmcomms8_constr.xdc"\
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<!-- no_no_os -->
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# ADRV9009ZU11EG/ADRV2CRR-FMCXMWBR1 HDL Project
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Aside from the [ADRV9009ZU11EG](https://www.analog.com/adrv9009-zu11eg) SoM attached to the mother board [ADRV2CRR-FMC](https://www.analog.com/adrv2crr-fmc), an extra evaluation board [FMCXMWBR1](https://www.analog.com/ad-fmcxmwbr1-ebz) should be attached on the FMC HPC connecter.
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- VADJ with which it was tested in hardware: 1.8V
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## Building the project
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This project is not parameterizable, it has a fixed configuration.
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All of the RX/TX link modes can be found in the [ADRV9009 data sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/ADRV9009.pdf). We offer support for only a few of them.
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The parameters from the environment:
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The overwritable parameters from the environment are:
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- [RX/TX/RX_OS]_JESD_M: [RX/TX/RX_OS] number of converters per link
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- [RX/TX/RX_OS]_JESD_L: [RX/TX/RX_OS] number of lanes per link
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- [RX/TX/RX_OS]_JESD_S: [RX/TX/RX_OS] number of samples per converter per frame
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### Example configurations
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- [RX/TX]_JESD_M: RX: **8** & TX: **8**; [RX/TX] number of converters per link
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- [RX/TX]_JESD_L: RX: **4** & TX: **8**; [RX/TX] number of lanes per link
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- [RX/TX]_JESD_S: RX: **1** & TX: **1**; [RX/TX] number of samples per converter per frame
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- RX_OS_JESD_M: **4**; number of converters per link
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- RX_OS_JESD_L: **4**; number of lanes per link
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- RX_OS_JESD_S: **1**; number of samples per frame
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#### Default configuration
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This specific command is equivalent to running `make` only:
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```
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make RX_JESD_M=8 \
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RX_JESD_L=4 \
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RX_JESD_S=1 \
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TX_JESD_M=8 \
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TX_JESD_L=8 \
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TX_JESD_S=1 \
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RX_OS_JESD_M=4 \
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RX_OS_JESD_L=4 \
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RX_OS_JESD_S=1
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```
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Corresponding device tree: [zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm-xmicrowave.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm-xmicrowave.dts)
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Corresponding device tree: [zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm-xmicrowave.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm-xmicrowave.dts)

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