docs/ada4355: Update documentation

Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>

Author: PIoandan

docs/library/axi_ada4355/index.rst

@@ -48,6 +48,9 @@ Configuration Parameters
      - Core ID should be unique for each IP in the system
    * - FPGA_TECHNOLOGY
      - Used to select between FPGA devices, auto set in project.
+   * - BUFMRCE_EN
+     - Used to select between evaluation boards that are differentiated
+       by how the frame clock signals are distributed.
 
 Interface
 --------------------------------------------------------------------------------
@@ -83,6 +86,8 @@ Interface
      - Received data output
    * - adc_dovf
      - Data overflow. Must be connected to the DMA
+   * - up_adc_pn_err
+     - Error monitoring
    * - s_axi
      - Standard AXI Slave Memory Map interface
 

docs/projects/ada4355_fmc/index.rst

@@ -66,6 +66,32 @@ The data path and clock domains are depicted in the below diagram:
    :align: center
    :alt: ADA4355_FMC/ZedBoard block diagram
 
+Configuration modes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The BUFMRCE_EN configuration parameter defines the type of evaluation board
+used, which are differentiated by how the frame clock signals are distributed.
+For the older evaluation board, the XDC constraints are not optimized for
+ISERDES, as the frame clock signals are located in a different I/O bank from
+the other related signals. To address this, a BUFMRCE buffer is used to
+distribute the frame clock to all ISERDES instances.
+
+By default it is set to 0. Depending on the type of evaluation board, some
+hardware modifications need to be done on the board and/or ``make`` command:
+
+In case of the Eval-Board with optimized xdc:
+
+.. shell:: bash
+
+   $make BUFMRCE_EN=0
+
+In case of the Eval-Board with non optimized xdc:
+
+.. shell:: bash
+
+   $make BUFMRCE_EN=1
+
+
 CPU/Memory interconnects addresses
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -121,19 +147,55 @@ The Software GPIO number is calculated as follows:
      - (from FPGA view)
      -
      - Zynq-7000
-   * - gpio_1p8va_en
+   * - apd_supp_en **
+     - INOUT
+     - 42
+     - 96
+   * - trig_fmc_out **
+     - INOUT
+     - 41
+     - 95
+   * - trig_fmc_in **
+     - INOUT
+     - 40
+     - 94
+   * - freq_sel1 **
+     - INOUT
+     - 39
+     - 93
+   * - gain_sel3 **
+     - INOUT
+     - 38
+     - 92
+   * - gpio_test **
+     - INOUT
+     - 37
+     - 91
+   * - gpio_1p8va_en *
      - IN
      - 37
      - 91
-   * - gain_sel2
+   * - gain_sel2 **
+     - INOUT
+     - 36
+     - 90
+   * - gain_sel2 *
      - IN
      - 36
      - 90
-   * - gpio_1p8vd_en
+   * - gpio_vld_en **
      - INOUT
      - 35
      - 89
-   * - fsel
+   * - gpio_1p8vd_en *
+     - INOUT
+     - 35
+     - 89
+   * - freq_sel0 **
+     - INOUT
+     - 34
+     - 88
+   * - fsel *
      - INOUT
      - 34
      - 88
@@ -146,6 +208,12 @@ The Software GPIO number is calculated as follows:
      - 32
      - 86
 
+.. admonition:: Legend
+   :class: note
+
+   - ``*`` instantiated only for BUFMRCE_EN=1
+   - ``**`` instantiated only for BUFMRCE_EN=0
+
 Interrupts
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -186,14 +254,25 @@ ADI distributes the bit/elf files of these projects as part of the
 If you want to build the sources, ADI makes them available on the
 :git-hdl:`HDL repository </>`. To get the source you must
 `clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
-the HDL repository.
+the HDL repository, and then build the project as follows:
 
 **Linux/Cygwin/WSL**
 
 .. shell::
 
    $cd hdl/projects/ada4355_fmc/zed
-   $make
+   $make BUFMRCE_EN=0
+
+The result of the build, if parameters were used, will be in a folder named
+by the configuration used:
+
+if the following command was run
+
+``make BUFMRCE_EN=0``
+
+then the folder name will be:
+
+``BUFMRCEEN0``
 
 A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.