projects/common: Remove kc705 support

Signed-off-by: sarpadi <sergiu.arpadi@analog.com>

Author: sarpadi

docs/library/jesd204/index.rst

@@ -421,7 +421,6 @@ HDL Example Projects
 
   - :git-hdl:`Intel Arria 10 SoC <projects/daq2/a10soc>`
   - :git-hdl:`Intel A10Gx (RETIRED) <hdl_2021_r1:projects/daq2/a10gx>`
-  - :git-hdl:`AMD Xilinx KC705 <projects/daq2/kc705>`
   - :git-hdl:`AMD Xilinx KCU105 <projects/daq2/kcu105>`
   - :git-hdl:`AMD Xilinx VC707 (RETIRED) <hdl_2018_r2:projects/daq2/vc707>`
   - :git-hdl:`AMD Xilinx ZC706 <projects/daq2/zc706>`

docs/user_guide/build_hdl.rst

@@ -1038,7 +1038,7 @@ In general, always run ``make`` within a project folder such as
 not be a need for you to run ``make`` inside the library or root folders.
 The ``make`` framework passes the top level 'targets' to any sub-makes
 inside its sub-folders. What this means, is that if you run ``make`` inside
-**hdl/projects/daq2**, it builds all the carriers (**kc705**, **a10soc**,
+**hdl/projects/daq2**, it builds all the carriers (**a10soc**,
 **kcu105**, **zc706** to **zcu102**) instead of just the target carrier.
 
 The following targets/arguments are supported:

projects/adv7511/README.md

@@ -12,4 +12,4 @@
 
 ## Building the project
 
-Please enter the folder for the FPGA carrier you want to use and read the README.md.
+Please enter the folder for the FPGA carrier you want to use and read the README.md.