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IstvanZsSzekelyIstvanZsSzekely
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projects/ad9081: Added a parameter to include Corundum Network Stack
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
1 parent 8a6892e commit 656e090

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-443
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6 files changed

+823
-443
lines changed

‎projects/ad9081_fmca_ebz/vcu118/system_bd.tcl

Lines changed: 98 additions & 93 deletions
Original file line numberDiff line numberDiff line change
@@ -147,134 +147,139 @@ if {$ad_project_params(JESD_MODE) == "64B66B"} {
147147
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_250mhz_clk1
148148
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram_c1_062
149149

150-
set INPUT_CHANNELS $RX_NUM_OF_CONVERTERS
151-
set INPUT_SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL
152-
set INPUT_SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH
150+
if {$ad_project_params(CORUNDUM) == "1"} {
153151

154-
set INPUT_WIDTH [expr $INPUT_CHANNELS*$INPUT_SAMPLES_PER_CHANNEL*$INPUT_SAMPLE_DATA_WIDTH]
152+
set INPUT_CHANNELS $RX_NUM_OF_CONVERTERS
153+
set INPUT_SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL
154+
set INPUT_SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH
155155

156-
set OUTPUT_CHANNELS $TX_NUM_OF_CONVERTERS
157-
set OUTPUT_SAMPLES $TX_SAMPLES_PER_CHANNEL
158-
set OUTPUT_SAMPLE_WIDTH $TX_DMA_SAMPLE_WIDTH
156+
set INPUT_WIDTH [expr $INPUT_CHANNELS*$INPUT_SAMPLES_PER_CHANNEL*$INPUT_SAMPLE_DATA_WIDTH]
159157

160-
set OUTPUT_WIDTH [expr $OUTPUT_CHANNELS*$OUTPUT_SAMPLES*$OUTPUT_SAMPLE_WIDTH]
158+
set OUTPUT_CHANNELS $TX_NUM_OF_CONVERTERS
159+
set OUTPUT_SAMPLES $TX_SAMPLES_PER_CHANNEL
160+
set OUTPUT_SAMPLE_WIDTH $TX_DMA_SAMPLE_WIDTH
161161

162-
set CPU MB
162+
set OUTPUT_WIDTH [expr $OUTPUT_CHANNELS*$OUTPUT_SAMPLES*$OUTPUT_SAMPLE_WIDTH]
163163

164-
source $ad_hdl_dir/library/corundum/scripts/corundum_vcu118_cfg.tcl
165-
source $ad_hdl_dir/library/corundum/scripts/corundum.tcl
164+
set CPU MB
166165

167-
ad_ip_parameter axi_dp_interconnect CONFIG.NUM_CLKS 3
168-
ad_connect axi_dp_interconnect/aclk2 sys_250m_clk
166+
source $ad_hdl_dir/library/corundum/scripts/corundum_vcu118_cfg.tcl
167+
set APP_ENABLE 0
168+
source $ad_hdl_dir/library/corundum/scripts/corundum.tcl
169169

170-
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 125
171-
set_property name sys_125m_rstgen [get_bd_cells sys_500m_rstgen]
170+
ad_ip_parameter axi_dp_interconnect CONFIG.NUM_CLKS 3
171+
ad_connect axi_dp_interconnect/aclk2 sys_250m_clk
172172

173-
ad_connect corundum_rstgen/slowest_sync_clk sys_250m_clk
174-
ad_connect corundum_rstgen/ext_reset_in axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst
173+
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 125
174+
set_property name sys_125m_rstgen [get_bd_cells sys_500m_rstgen]
175175

176-
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi0
177-
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi1
178-
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qsfp_rtl:1.0 qsfp
176+
ad_connect corundum_rstgen/slowest_sync_clk sys_250m_clk
177+
ad_connect corundum_rstgen/ext_reset_in axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst
179178

180-
create_bd_port -dir O -from 0 -to 0 -type rst qsfp_rst
181-
create_bd_port -dir O fpga_boot
182-
create_bd_port -dir O -type clk qspi_clk
183-
create_bd_port -dir I -type rst ptp_rst
184-
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports ptp_rst]
185-
create_bd_port -dir I -type clk qsfp_mgt_refclk
186-
create_bd_port -dir I -type clk qsfp_mgt_refclk_bufg
179+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi0
180+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi1
181+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qsfp_rtl:1.0 qsfp
187182

188-
create_bd_port -dir O -type clk clk_125mhz
189-
create_bd_port -dir O -type clk clk_250mhz
183+
create_bd_port -dir O -from 0 -to 0 -type rst qsfp_rst
184+
create_bd_port -dir O fpga_boot
185+
create_bd_port -dir O -type clk qspi_clk
186+
create_bd_port -dir I -type rst ptp_rst
187+
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports ptp_rst]
188+
create_bd_port -dir I -type clk qsfp_mgt_refclk
189+
create_bd_port -dir I -type clk qsfp_mgt_refclk_bufg
190190

191-
ad_connect sys_500m_clk clk_125mhz
192-
ad_connect sys_250m_clk clk_250mhz
191+
create_bd_port -dir O -type clk clk_125mhz
192+
create_bd_port -dir O -type clk clk_250mhz
193193

194-
ad_connect corundum_hierarchy/clk_125mhz clk_125mhz
195-
ad_connect corundum_hierarchy/clk_corundum sys_250m_clk
194+
ad_connect sys_500m_clk clk_125mhz
195+
ad_connect sys_250m_clk clk_250mhz
196196

197-
ad_connect corundum_hierarchy/rst_125mhz sys_125m_rstgen/peripheral_reset
197+
ad_connect corundum_hierarchy/clk_125mhz clk_125mhz
198+
ad_connect corundum_hierarchy/clk_corundum sys_250m_clk
198199

199-
ad_connect corundum_hierarchy/qspi0 qspi0
200-
ad_connect corundum_hierarchy/qspi1 qspi1
201-
ad_connect corundum_hierarchy/qsfp qsfp
202-
ad_connect corundum_hierarchy/qsfp_rst qsfp_rst
203-
ad_connect corundum_hierarchy/fpga_boot fpga_boot
204-
ad_connect corundum_hierarchy/qspi_clk qspi_clk
205-
ad_connect corundum_hierarchy/ptp_rst ptp_rst
206-
ad_connect corundum_hierarchy/qsfp_mgt_refclk qsfp_mgt_refclk
207-
ad_connect corundum_hierarchy/qsfp_mgt_refclk_bufg qsfp_mgt_refclk_bufg
200+
ad_connect corundum_hierarchy/rst_125mhz sys_125m_rstgen/peripheral_reset
208201

209-
ad_cpu_interconnect 0x50000000 corundum_hierarchy s_axil_corundum
210-
ad_cpu_interconnect 0x52000000 corundum_gpio_reset
202+
ad_connect corundum_hierarchy/qspi0 qspi0
203+
ad_connect corundum_hierarchy/qspi1 qspi1
204+
ad_connect corundum_hierarchy/qsfp qsfp
205+
ad_connect corundum_hierarchy/qsfp_rst qsfp_rst
206+
ad_connect corundum_hierarchy/fpga_boot fpga_boot
207+
ad_connect corundum_hierarchy/qspi_clk qspi_clk
208+
ad_connect corundum_hierarchy/ptp_rst ptp_rst
209+
ad_connect corundum_hierarchy/qsfp_mgt_refclk qsfp_mgt_refclk
210+
ad_connect corundum_hierarchy/qsfp_mgt_refclk_bufg qsfp_mgt_refclk_bufg
211211

212-
ad_mem_hp1_interconnect sys_250m_clk corundum_hierarchy/m_axi
212+
ad_cpu_interconnect 0x50000000 corundum_hierarchy s_axil_corundum
213+
ad_cpu_interconnect 0x52000000 corundum_gpio_reset
213214

214-
ad_cpu_interrupt "ps-5" "mb-5" corundum_hierarchy/irq
215+
ad_mem_hp1_interconnect sys_250m_clk corundum_hierarchy/m_axi
215216

216-
if {$APP_ENABLE == 1} {
217-
ad_cpu_interconnect 0x51000000 corundum_hierarchy s_axil_application
217+
ad_cpu_interrupt "ps-5" "mb-5" corundum_hierarchy/irq
218218

219-
ad_ip_instance util_cpack2 util_corundum_cpack [list \
220-
NUM_OF_CHANNELS $INPUT_CHANNELS \
221-
SAMPLES_PER_CHANNEL $INPUT_SAMPLES_PER_CHANNEL \
222-
SAMPLE_DATA_WIDTH $INPUT_SAMPLE_DATA_WIDTH \
223-
]
219+
if {$APP_ENABLE == 1} {
220+
ad_cpu_interconnect 0x51000000 corundum_hierarchy s_axil_application
224221

225-
ad_connect util_corundum_cpack/clk rx_device_clk
226-
ad_connect util_corundum_cpack/fifo_wr_en rx_mxfe_tpl_core/adc_valid_0
227-
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
228-
ad_connect util_corundum_cpack/enable_${i} rx_mxfe_tpl_core/adc_enable_${i}
229-
ad_connect util_corundum_cpack/fifo_wr_data_${i} rx_mxfe_tpl_core/adc_data_${i}
230-
}
222+
ad_ip_instance util_cpack2 util_corundum_cpack [list \
223+
NUM_OF_CHANNELS $INPUT_CHANNELS \
224+
SAMPLES_PER_CHANNEL $INPUT_SAMPLES_PER_CHANNEL \
225+
SAMPLE_DATA_WIDTH $INPUT_SAMPLE_DATA_WIDTH \
226+
]
231227

232-
ad_connect corundum_hierarchy/input_clk axi_mxfe_rx_jesd/device_clk
233-
ad_connect corundum_hierarchy/input_rstn rx_device_clk_rstgen/peripheral_aresetn
228+
ad_connect util_corundum_cpack/clk rx_device_clk
229+
ad_connect util_corundum_cpack/fifo_wr_en rx_mxfe_tpl_core/adc_valid_0
230+
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
231+
ad_connect util_corundum_cpack/enable_${i} rx_mxfe_tpl_core/adc_enable_${i}
232+
ad_connect util_corundum_cpack/fifo_wr_data_${i} rx_mxfe_tpl_core/adc_data_${i}
233+
}
234234

235-
ad_connect corundum_hierarchy/output_clk axi_mxfe_tx_jesd/device_clk
236-
ad_connect corundum_hierarchy/output_rstn tx_device_clk_rstgen/peripheral_aresetn
235+
ad_connect corundum_hierarchy/input_clk axi_mxfe_rx_jesd/device_clk
236+
ad_connect corundum_hierarchy/input_rstn rx_device_clk_rstgen/peripheral_aresetn
237237

238-
ad_connect corundum_hierarchy/input_axis_tvalid util_corundum_cpack/packed_fifo_wr_en
239-
ad_connect corundum_hierarchy/input_axis_tdata util_corundum_cpack/packed_fifo_wr_data
240-
ad_connect corundum_hierarchy/input_axis_tready util_corundum_cpack/packed_fifo_wr_overflow
238+
ad_connect corundum_hierarchy/output_clk axi_mxfe_tx_jesd/device_clk
239+
ad_connect corundum_hierarchy/output_rstn tx_device_clk_rstgen/peripheral_aresetn
241240

242-
ad_ip_instance util_reduced_logic cpack_rst_logic_corundum
243-
ad_ip_parameter cpack_rst_logic_corundum config.c_operation {or}
244-
ad_ip_parameter cpack_rst_logic_corundum config.c_size {4}
241+
ad_connect corundum_hierarchy/input_axis_tvalid util_corundum_cpack/packed_fifo_wr_en
242+
ad_connect corundum_hierarchy/input_axis_tdata util_corundum_cpack/packed_fifo_wr_data
243+
ad_connect corundum_hierarchy/input_axis_tready util_corundum_cpack/packed_fifo_wr_overflow
245244

246-
ad_ip_instance util_vector_logic rx_do_rstout_logic_corundum
247-
ad_ip_parameter rx_do_rstout_logic_corundum config.c_operation {not}
248-
ad_ip_parameter rx_do_rstout_logic_corundum config.c_size {1}
245+
ad_ip_instance util_reduced_logic cpack_rst_logic_corundum
246+
ad_ip_parameter cpack_rst_logic_corundum config.c_operation {or}
247+
ad_ip_parameter cpack_rst_logic_corundum config.c_size {4}
249248

250-
ad_ip_instance xlconcat cpack_reset_sources_corundum
251-
ad_ip_parameter cpack_reset_sources_corundum config.num_ports {4}
249+
ad_ip_instance util_vector_logic rx_do_rstout_logic_corundum
250+
ad_ip_parameter rx_do_rstout_logic_corundum config.c_operation {not}
251+
ad_ip_parameter rx_do_rstout_logic_corundum config.c_size {1}
252252

253-
ad_connect corundum_hierarchy/input_axis_tready rx_do_rstout_logic_corundum/Op1
253+
ad_ip_instance xlconcat cpack_reset_sources_corundum
254+
ad_ip_parameter cpack_reset_sources_corundum config.num_ports {4}
254255

255-
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources_corundum/in0
256-
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources_corundum/in1
257-
ad_connect rx_do_rstout_logic_corundum/res cpack_reset_sources_corundum/in2
258-
ad_connect corundum_hierarchy/input_packer_reset cpack_reset_sources_corundum/in3
256+
ad_connect corundum_hierarchy/input_axis_tready rx_do_rstout_logic_corundum/Op1
259257

260-
ad_connect cpack_reset_sources_corundum/dout cpack_rst_logic_corundum/op1
261-
ad_connect cpack_rst_logic_corundum/res util_corundum_cpack/reset
258+
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources_corundum/in0
259+
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources_corundum/in1
260+
ad_connect rx_do_rstout_logic_corundum/res cpack_reset_sources_corundum/in2
261+
ad_connect corundum_hierarchy/input_packer_reset cpack_reset_sources_corundum/in3
262262

263-
ad_ip_instance xlconcat input_enable_concat_corundum
264-
ad_ip_parameter input_enable_concat_corundum config.num_ports $INPUT_CHANNELS
263+
ad_connect cpack_reset_sources_corundum/dout cpack_rst_logic_corundum/op1
264+
ad_connect cpack_rst_logic_corundum/res util_corundum_cpack/reset
265265

266-
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
267-
ad_connect input_enable_concat_corundum/In${i} rx_mxfe_tpl_core/adc_enable_${i}
268-
}
266+
ad_ip_instance xlconcat input_enable_concat_corundum
267+
ad_ip_parameter input_enable_concat_corundum config.num_ports $INPUT_CHANNELS
268+
269+
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
270+
ad_connect input_enable_concat_corundum/In${i} rx_mxfe_tpl_core/adc_enable_${i}
271+
}
272+
273+
ad_connect input_enable_concat_corundum/dout corundum_hierarchy/input_enable
269274

270-
ad_connect input_enable_concat_corundum/dout corundum_hierarchy/input_enable
275+
ad_ip_instance xlconcat output_enable_concat_corundum
276+
ad_ip_parameter output_enable_concat_corundum config.num_ports $OUTPUT_CHANNELS
271277

272-
ad_ip_instance xlconcat output_enable_concat_corundum
273-
ad_ip_parameter output_enable_concat_corundum config.num_ports $OUTPUT_CHANNELS
278+
for {set i 0} {$i<$OUTPUT_CHANNELS} {incr i} {
279+
ad_connect output_enable_concat_corundum/In${i} tx_mxfe_tpl_core/dac_enable_${i}
280+
}
274281

275-
for {set i 0} {$i<$OUTPUT_CHANNELS} {incr i} {
276-
ad_connect output_enable_concat_corundum/In${i} tx_mxfe_tpl_core/dac_enable_${i}
282+
ad_connect output_enable_concat_corundum/dout corundum_hierarchy/output_enable
277283
}
278284

279-
ad_connect output_enable_concat_corundum/dout corundum_hierarchy/output_enable
280285
}

‎projects/ad9081_fmca_ebz/vcu118/system_constr.xdc

Lines changed: 0 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -94,71 +94,3 @@ set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18
9494
set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_43
9595

9696
set_property -dict {PACKAGE_PIN AK35 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports vadj_1v8_pgood ] ; ## IO_T1U_N12_43_AK35
97-
98-
# U145 QSFP+ Module QSFP1
99-
# set_property -dict {PACKAGE_PIN Y2} [get_ports {qsfp_rx_p[0]}]
100-
# set_property -dict {PACKAGE_PIN Y1} [get_ports {qsfp_rx_n[0]}]
101-
# set_property -dict {PACKAGE_PIN V7} [get_ports {qsfp_tx_p[0]}]
102-
# set_property -dict {PACKAGE_PIN V6} [get_ports {qsfp_tx_n[0]}]
103-
# set_property -dict {PACKAGE_PIN W4} [get_ports {qsfp_rx_p[1]}]
104-
# set_property -dict {PACKAGE_PIN W3} [get_ports {qsfp_rx_n[1]}]
105-
# set_property -dict {PACKAGE_PIN T7} [get_ports {qsfp_tx_p[1]}]
106-
# set_property -dict {PACKAGE_PIN T6} [get_ports {qsfp_tx_n[1]}]
107-
# set_property -dict {PACKAGE_PIN V2} [get_ports {qsfp_rx_p[2]}]
108-
# set_property -dict {PACKAGE_PIN V1} [get_ports {qsfp_rx_n[2]}]
109-
# set_property -dict {PACKAGE_PIN P7} [get_ports {qsfp_tx_p[2]}]
110-
# set_property -dict {PACKAGE_PIN P6} [get_ports {qsfp_tx_n[2]}]
111-
# set_property -dict {PACKAGE_PIN U4} [get_ports {qsfp_rx_p[3]}]
112-
# set_property -dict {PACKAGE_PIN U3} [get_ports {qsfp_rx_n[3]}]
113-
# set_property -dict {PACKAGE_PIN M7} [get_ports {qsfp_tx_p[3]}]
114-
# set_property -dict {PACKAGE_PIN M6} [get_ports {qsfp_tx_n[3]}]
115-
116-
# U145 QSFP+ Module QSFP2
117-
set_property -dict {PACKAGE_PIN T2} [get_ports {qsfp_rx_p[0]}]
118-
set_property -dict {PACKAGE_PIN T1} [get_ports {qsfp_rx_n[0]}]
119-
set_property -dict {PACKAGE_PIN L5} [get_ports {qsfp_tx_p[0]}]
120-
set_property -dict {PACKAGE_PIN L4} [get_ports {qsfp_tx_n[0]}]
121-
set_property -dict {PACKAGE_PIN R4} [get_ports {qsfp_rx_p[1]}]
122-
set_property -dict {PACKAGE_PIN R3} [get_ports {qsfp_rx_n[1]}]
123-
set_property -dict {PACKAGE_PIN K7} [get_ports {qsfp_tx_p[1]}]
124-
set_property -dict {PACKAGE_PIN K6} [get_ports {qsfp_tx_n[1]}]
125-
set_property -dict {PACKAGE_PIN P2} [get_ports {qsfp_rx_p[2]}]
126-
set_property -dict {PACKAGE_PIN P1} [get_ports {qsfp_rx_n[2]}]
127-
set_property -dict {PACKAGE_PIN J5} [get_ports {qsfp_tx_p[2]}]
128-
set_property -dict {PACKAGE_PIN J4} [get_ports {qsfp_tx_n[2]}]
129-
set_property -dict {PACKAGE_PIN M2} [get_ports {qsfp_rx_p[3]}]
130-
set_property -dict {PACKAGE_PIN M1} [get_ports {qsfp_rx_n[3]}]
131-
set_property -dict {PACKAGE_PIN H7} [get_ports {qsfp_tx_p[3]}]
132-
set_property -dict {PACKAGE_PIN H6} [get_ports {qsfp_tx_n[3]}]
133-
134-
# REF clock
135-
set_property -dict {PACKAGE_PIN W9} [get_ports qsfp_mgt_refclk_p]
136-
set_property -dict {PACKAGE_PIN W8} [get_ports qsfp_mgt_refclk_n]
137-
138-
# 156.25 MHz MGT reference clock
139-
create_clock -period 6.400 -name qsfp_mgt_refclk [get_ports qsfp_mgt_refclk_p]
140-
141-
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_modsell]
142-
set_property -dict {PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_resetl]
143-
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_lpmode]
144-
set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports qsfp_modprsl]
145-
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports qsfp_intl]
146-
147-
set_false_path -to [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
148-
set_output_delay 0.000 [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
149-
set_false_path -from [get_ports {qsfp_modprsl qsfp_intl}]
150-
set_input_delay 0.000 [get_ports {qsfp_modprsl qsfp_intl}]
151-
152-
# QSPI flash
153-
set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[0]}]
154-
set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[1]}]
155-
set_property -dict {PACKAGE_PIN AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[2]}]
156-
set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[3]}]
157-
set_property -dict {PACKAGE_PIN BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports qspi1_cs]
158-
159-
set_false_path -to [get_ports {{qspi1_dq[*]} qspi1_cs}]
160-
set_output_delay 0.000 [get_ports {{qspi1_dq[*]} qspi1_cs}]
161-
set_false_path -from [get_ports qspi1_dq]
162-
set_input_delay 0.000 [get_ports qspi1_dq]
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set_property LOC CMACE4_X0Y7 [get_cells -hierarchical -filter {NAME =~ */qsfp[0].qsfp_cmac_inst/cmac_inst/inst/i_cmac_usplus_top/* && REF_NAME==CMACE4}]

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