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IstvanZsSzekelyIstvanZsSzekely
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ad9081: Updated to support Corundum Network Stack
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
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‎projects/ad9081_fmca_ebz/vcu118/Makefile

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
####################################################################################
2-
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
2+
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
33
### SPDX short identifier: BSD-1-Clause
44
## Auto-generated, do not modify!
55
####################################################################################
@@ -21,6 +21,21 @@ M_DEPS += ../../../library/common/ad_iobuf.v
2121
M_DEPS += ../../../library/common/ad_3w_spi.v
2222
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
2323

24+
M_DEPS += ../../../library/corundum/scripts/corundum_vcu118_cfg.tcl
25+
M_DEPS += ../../../library/corundum/scripts/corundum.tcl
26+
27+
M_DEPS += ../../../library/corundum/scripts/sync_reset.tcl
28+
29+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/rb_drp.tcl
30+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/cmac_gty_wrapper.tcl
31+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
32+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
33+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl
34+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_port.tcl
35+
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
36+
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl
37+
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl
38+
2439
LIB_DEPS += axi_dmac
2540
LIB_DEPS += axi_sysid
2641
LIB_DEPS += axi_tdd
@@ -42,5 +57,9 @@ LIB_DEPS += util_pack/util_cpack2
4257
LIB_DEPS += util_pack/util_upack2
4358
LIB_DEPS += xilinx/axi_adxcvr
4459
LIB_DEPS += xilinx/util_adxcvr
60+
LIB_DEPS += corundum/corundum_core
61+
LIB_DEPS += corundum/ethernet
62+
63+
export BOARD := VCU118
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4665
include ../../scripts/project-xilinx.mk

‎projects/ad9081_fmca_ebz/vcu118/README.md

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ All of the RX/TX link modes can be found in the [AD9081 data sheet](https://www.
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1616
The overwritable parameters from the environment are:
1717

18-
- JESD_MODE: link layer encoder mode used;
18+
- JESD_MODE: link layer encoder mode used;
1919
- 8B10B - 8b10b link layer defined in JESD204B
2020
- 64B66B - 64b66b link layer defined in JESD204C
2121
- [RX/TX]_LANE_RATE: lane rate of the [RX/TX] link (RX: MxFE to FPGA/TX: FPGA to MxFE)
@@ -25,6 +25,7 @@ The overwritable parameters from the environment are:
2525
- [RX/TX]_JESD_NP: [RX/TX] number of bits per sample, only 16 is supported
2626
- [RX/TX]_NUM_LINKS: [RX/TX] number of links, which matches the number of MxFE devices
2727
- [RX/TX]_KS_PER_CHANNEL: [RX/TX] number of samples stored in internal buffers in kilosamples per converter (M), for each channel in a block RAM, for a contiguous capture
28+
- CORUNDUM: includes and enables the Corundum Network Stack in the design
2829

2930
### Example configurations
3031

@@ -158,3 +159,26 @@ TX_NUM_LINKS=1
158159
```
159160

160161
Corresponding device tree: [vcu118_ad9081_204c_txmode_24_rxmode_26_lr_24_75Gbps.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/microblaze/boot/dts/vcu118_ad9081_204c_txmode_24_rxmode_26_lr_24_75Gbps.dts)
162+
163+
#### JESD204B subclass 1, TX mode 9, RX mode 10 (default) with Corundum Network Stack
164+
165+
This specific command is equivalent to running `make CORUNDUM=1`:
166+
167+
```
168+
make JESD_MODE=8B10B \
169+
RX_LANE_RATE=10 \
170+
TX_LANE_RATE=10 \
171+
RX_JESD_M=8 \
172+
RX_JESD_L=4 \
173+
RX_JESD_S=1 \
174+
RX_JESD_NP=16 \
175+
RX_NUM_LINKS=1 \
176+
TX_JESD_M=8 \
177+
TX_JESD_L=4 \
178+
TX_JESD_S=1 \
179+
TX_JESD_NP=16 \
180+
TX_NUM_LINKS=1 \
181+
RX_KS_PER_CHANNEL=64 \
182+
TX_KS_PER_CHANNEL=64 \
183+
CORUNDUM = 1
184+
```

‎projects/ad9081_fmca_ebz/vcu118/system_bd.tcl

Lines changed: 141 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -143,3 +143,143 @@ if {$ad_project_params(JESD_MODE) == "64B66B"} {
143143
}
144144

145145
}
146+
147+
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_250mhz_clk1
148+
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram_c1_062
149+
150+
if {$ad_project_params(CORUNDUM) == "1"} {
151+
152+
set INPUT_CHANNELS $RX_NUM_OF_CONVERTERS
153+
set INPUT_SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL
154+
set INPUT_SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH
155+
156+
set INPUT_WIDTH [expr $INPUT_CHANNELS*$INPUT_SAMPLES_PER_CHANNEL*$INPUT_SAMPLE_DATA_WIDTH]
157+
158+
set OUTPUT_CHANNELS $TX_NUM_OF_CONVERTERS
159+
set OUTPUT_SAMPLES $TX_SAMPLES_PER_CHANNEL
160+
set OUTPUT_SAMPLE_WIDTH $TX_DMA_SAMPLE_WIDTH
161+
162+
set OUTPUT_WIDTH [expr $OUTPUT_CHANNELS*$OUTPUT_SAMPLES*$OUTPUT_SAMPLE_WIDTH]
163+
164+
set CPU MB
165+
166+
source $ad_hdl_dir/library/corundum/scripts/corundum_vcu118_cfg.tcl
167+
set APP_ENABLE 0
168+
source $ad_hdl_dir/library/corundum/scripts/corundum.tcl
169+
170+
ad_ip_parameter axi_dp_interconnect CONFIG.NUM_CLKS 3
171+
ad_connect axi_dp_interconnect/aclk2 sys_250m_clk
172+
173+
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 125
174+
set_property name sys_125m_rstgen [get_bd_cells sys_500m_rstgen]
175+
176+
ad_connect corundum_rstgen/slowest_sync_clk sys_250m_clk
177+
ad_connect corundum_rstgen/ext_reset_in axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst
178+
179+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi0
180+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi1
181+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qsfp_rtl:1.0 qsfp
182+
183+
create_bd_port -dir O -from 0 -to 0 -type rst qsfp_rst
184+
create_bd_port -dir O fpga_boot
185+
create_bd_port -dir O -type clk qspi_clk
186+
create_bd_port -dir I -type rst ptp_rst
187+
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports ptp_rst]
188+
create_bd_port -dir I -type clk qsfp_mgt_refclk
189+
create_bd_port -dir I -type clk qsfp_mgt_refclk_bufg
190+
191+
create_bd_port -dir O -type clk clk_125mhz
192+
create_bd_port -dir O -type clk clk_250mhz
193+
194+
ad_connect sys_500m_clk clk_125mhz
195+
ad_connect sys_250m_clk clk_250mhz
196+
197+
ad_connect corundum_hierarchy/clk_125mhz clk_125mhz
198+
ad_connect corundum_hierarchy/clk_corundum sys_250m_clk
199+
200+
ad_connect corundum_hierarchy/rst_125mhz sys_125m_rstgen/peripheral_reset
201+
202+
ad_connect corundum_hierarchy/qspi0 qspi0
203+
ad_connect corundum_hierarchy/qspi1 qspi1
204+
ad_connect corundum_hierarchy/qsfp qsfp
205+
ad_connect corundum_hierarchy/qsfp_rst qsfp_rst
206+
ad_connect corundum_hierarchy/fpga_boot fpga_boot
207+
ad_connect corundum_hierarchy/qspi_clk qspi_clk
208+
ad_connect corundum_hierarchy/ptp_rst ptp_rst
209+
ad_connect corundum_hierarchy/qsfp_mgt_refclk qsfp_mgt_refclk
210+
ad_connect corundum_hierarchy/qsfp_mgt_refclk_bufg qsfp_mgt_refclk_bufg
211+
212+
ad_cpu_interconnect 0x50000000 corundum_hierarchy s_axil_corundum
213+
ad_cpu_interconnect 0x52000000 corundum_gpio_reset
214+
215+
ad_mem_hp1_interconnect sys_250m_clk corundum_hierarchy/m_axi
216+
217+
ad_cpu_interrupt "ps-5" "mb-5" corundum_hierarchy/irq
218+
219+
if {$APP_ENABLE == 1} {
220+
ad_cpu_interconnect 0x51000000 corundum_hierarchy s_axil_application
221+
222+
ad_ip_instance util_cpack2 util_corundum_cpack [list \
223+
NUM_OF_CHANNELS $INPUT_CHANNELS \
224+
SAMPLES_PER_CHANNEL $INPUT_SAMPLES_PER_CHANNEL \
225+
SAMPLE_DATA_WIDTH $INPUT_SAMPLE_DATA_WIDTH \
226+
]
227+
228+
ad_connect util_corundum_cpack/clk rx_device_clk
229+
ad_connect util_corundum_cpack/fifo_wr_en rx_mxfe_tpl_core/adc_valid_0
230+
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
231+
ad_connect util_corundum_cpack/enable_${i} rx_mxfe_tpl_core/adc_enable_${i}
232+
ad_connect util_corundum_cpack/fifo_wr_data_${i} rx_mxfe_tpl_core/adc_data_${i}
233+
}
234+
235+
ad_connect corundum_hierarchy/input_clk axi_mxfe_rx_jesd/device_clk
236+
ad_connect corundum_hierarchy/input_rstn rx_device_clk_rstgen/peripheral_aresetn
237+
238+
ad_connect corundum_hierarchy/output_clk axi_mxfe_tx_jesd/device_clk
239+
ad_connect corundum_hierarchy/output_rstn tx_device_clk_rstgen/peripheral_aresetn
240+
241+
ad_connect corundum_hierarchy/input_axis_tvalid util_corundum_cpack/packed_fifo_wr_en
242+
ad_connect corundum_hierarchy/input_axis_tdata util_corundum_cpack/packed_fifo_wr_data
243+
ad_connect corundum_hierarchy/input_axis_tready util_corundum_cpack/packed_fifo_wr_overflow
244+
245+
ad_ip_instance util_reduced_logic cpack_rst_logic_corundum
246+
ad_ip_parameter cpack_rst_logic_corundum config.c_operation {or}
247+
ad_ip_parameter cpack_rst_logic_corundum config.c_size {4}
248+
249+
ad_ip_instance util_vector_logic rx_do_rstout_logic_corundum
250+
ad_ip_parameter rx_do_rstout_logic_corundum config.c_operation {not}
251+
ad_ip_parameter rx_do_rstout_logic_corundum config.c_size {1}
252+
253+
ad_ip_instance xlconcat cpack_reset_sources_corundum
254+
ad_ip_parameter cpack_reset_sources_corundum config.num_ports {4}
255+
256+
ad_connect corundum_hierarchy/input_axis_tready rx_do_rstout_logic_corundum/Op1
257+
258+
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources_corundum/in0
259+
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources_corundum/in1
260+
ad_connect rx_do_rstout_logic_corundum/res cpack_reset_sources_corundum/in2
261+
ad_connect corundum_hierarchy/input_packer_reset cpack_reset_sources_corundum/in3
262+
263+
ad_connect cpack_reset_sources_corundum/dout cpack_rst_logic_corundum/op1
264+
ad_connect cpack_rst_logic_corundum/res util_corundum_cpack/reset
265+
266+
ad_ip_instance xlconcat input_enable_concat_corundum
267+
ad_ip_parameter input_enable_concat_corundum config.num_ports $INPUT_CHANNELS
268+
269+
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
270+
ad_connect input_enable_concat_corundum/In${i} rx_mxfe_tpl_core/adc_enable_${i}
271+
}
272+
273+
ad_connect input_enable_concat_corundum/dout corundum_hierarchy/input_enable
274+
275+
ad_ip_instance xlconcat output_enable_concat_corundum
276+
ad_ip_parameter output_enable_concat_corundum config.num_ports $OUTPUT_CHANNELS
277+
278+
for {set i 0} {$i<$OUTPUT_CHANNELS} {incr i} {
279+
ad_connect output_enable_concat_corundum/In${i} tx_mxfe_tpl_core/dac_enable_${i}
280+
}
281+
282+
ad_connect output_enable_concat_corundum/dout corundum_hierarchy/output_enable
283+
}
284+
285+
}

‎projects/ad9081_fmca_ebz/vcu118/system_constr.xdc

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
###############################################################################
2-
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
2+
## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved.
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

@@ -17,11 +17,11 @@ set_property -dict {PACKAGE_PIN M35 IOSTANDARD LVCMOS18
1717
set_property -dict {PACKAGE_PIN L35 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L24N_T3U_N11_45
1818
set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## IO_L14N_T2L_N3_GC_45
1919
set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## IO_L14P_T2L_N2_GC_45
20-
set_property -dict {PACKAGE_PIN AM39 } [get_ports clkin8_n ] ; ## MGTREFCLK1N_120
21-
set_property -dict {PACKAGE_PIN AM38 } [get_ports clkin8_p ] ; ## MGTREFCLK1P_120
22-
set_property -dict {PACKAGE_PIN AK39 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_121
23-
set_property -dict {PACKAGE_PIN AK38 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_121
24-
set_property -dict {PACKAGE_PIN V39 } [get_ports fpga_refclk_in_replica_n ] ; ## MGTREFCLK0N_126
20+
set_property -dict {PACKAGE_PIN AM39 } [get_ports clkin8_n ] ; ## MGTREFCLK1N_120
21+
set_property -dict {PACKAGE_PIN AM38 } [get_ports clkin8_p ] ; ## MGTREFCLK1P_120
22+
set_property -dict {PACKAGE_PIN AK39 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_121
23+
set_property -dict {PACKAGE_PIN AK38 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_121
24+
set_property -dict {PACKAGE_PIN V39 } [get_ports fpga_refclk_in_replica_n ] ; ## MGTREFCLK0N_126
2525
set_property -dict {PACKAGE_PIN V38 } [get_ports fpga_refclk_in_replica_p ] ; ## MGTREFCLK0P_126
2626
set_property -quiet -dict {PACKAGE_PIN AL46 } [get_ports rx_data_n[2] ] ; ## MGTYRXN2_121 FPGA_SERDIN_0_N
2727
set_property -quiet -dict {PACKAGE_PIN AL45 } [get_ports rx_data_p[2] ] ; ## MGTYRXP2_121 FPGA_SERDIN_0_P
@@ -55,7 +55,7 @@ set_property -quiet -dict {PACKAGE_PIN T43
5555
set_property -quiet -dict {PACKAGE_PIN T42 } [get_ports tx_data_p[4] ] ; ## MGTYTXP0_126 FPGA_SERDOUT_6_P
5656
set_property -quiet -dict {PACKAGE_PIN AL41 } [get_ports tx_data_n[3] ] ; ## MGTYTXN3_121 FPGA_SERDOUT_7_N
5757
set_property -quiet -dict {PACKAGE_PIN AL40 } [get_ports tx_data_p[3] ] ; ## MGTYTXP3_121 FPGA_SERDOUT_7_P
58-
set_property -quiet -dict {PACKAGE_PIN AK32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[0] ] ; ## IO_L14N_T2L_N3_GC_43
58+
set_property -quiet -dict {PACKAGE_PIN AK32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[0] ] ; ## IO_L14N_T2L_N3_GC_43
5959
set_property -quiet -dict {PACKAGE_PIN AJ32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_p[0] ] ; ## IO_L14P_T2L_N2_GC_43
6060
set_property -quiet -dict {PACKAGE_PIN AT40 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[1] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_43
6161
set_property -quiet -dict {PACKAGE_PIN AT39 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_p[1] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_43
@@ -93,7 +93,4 @@ set_property -dict {PACKAGE_PIN AL32 IOSTANDARD LVDS DIFF_TERM_ADV T
9393
set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_43
9494
set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_43
9595

96-
set_property -dict {PACKAGE_PIN AK35 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports vadj_1v8_pgood ] ; ## IO_T1U_N12_43_AK35
97-
98-
99-
96+
set_property -dict {PACKAGE_PIN AK35 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports vadj_1v8_pgood ] ; ## IO_T1U_N12_43_AK35

‎projects/ad9081_fmca_ebz/vcu118/system_constr_corundum.xdc

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
###############################################################################
2+
## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
3+
### SPDX short identifier: ADIBSD
4+
###############################################################################
5+
6+
# U145 QSFP+ Module QSFP1
7+
# set_property -dict {PACKAGE_PIN Y2} [get_ports {qsfp_rx_p[0]}]
8+
# set_property -dict {PACKAGE_PIN Y1} [get_ports {qsfp_rx_n[0]}]
9+
# set_property -dict {PACKAGE_PIN V7} [get_ports {qsfp_tx_p[0]}]
10+
# set_property -dict {PACKAGE_PIN V6} [get_ports {qsfp_tx_n[0]}]
11+
# set_property -dict {PACKAGE_PIN W4} [get_ports {qsfp_rx_p[1]}]
12+
# set_property -dict {PACKAGE_PIN W3} [get_ports {qsfp_rx_n[1]}]
13+
# set_property -dict {PACKAGE_PIN T7} [get_ports {qsfp_tx_p[1]}]
14+
# set_property -dict {PACKAGE_PIN T6} [get_ports {qsfp_tx_n[1]}]
15+
# set_property -dict {PACKAGE_PIN V2} [get_ports {qsfp_rx_p[2]}]
16+
# set_property -dict {PACKAGE_PIN V1} [get_ports {qsfp_rx_n[2]}]
17+
# set_property -dict {PACKAGE_PIN P7} [get_ports {qsfp_tx_p[2]}]
18+
# set_property -dict {PACKAGE_PIN P6} [get_ports {qsfp_tx_n[2]}]
19+
# set_property -dict {PACKAGE_PIN U4} [get_ports {qsfp_rx_p[3]}]
20+
# set_property -dict {PACKAGE_PIN U3} [get_ports {qsfp_rx_n[3]}]
21+
# set_property -dict {PACKAGE_PIN M7} [get_ports {qsfp_tx_p[3]}]
22+
# set_property -dict {PACKAGE_PIN M6} [get_ports {qsfp_tx_n[3]}]
23+
24+
# set_property -dict {PACKAGE_PIN AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_modsell]
25+
# set_property -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_resetl]
26+
# set_property -dict {PACKAGE_PIN AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_lpmode]
27+
# set_property -dict {PACKAGE_PIN AN24 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports qsfp_modprsl]
28+
# set_property -dict {PACKAGE_PIN AT21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports qsfp_intl]
29+
30+
# U145 QSFP+ Module QSFP2
31+
set_property -dict {PACKAGE_PIN T2} [get_ports {qsfp_rx_p[0]}]
32+
set_property -dict {PACKAGE_PIN T1} [get_ports {qsfp_rx_n[0]}]
33+
set_property -dict {PACKAGE_PIN L5} [get_ports {qsfp_tx_p[0]}]
34+
set_property -dict {PACKAGE_PIN L4} [get_ports {qsfp_tx_n[0]}]
35+
set_property -dict {PACKAGE_PIN R4} [get_ports {qsfp_rx_p[1]}]
36+
set_property -dict {PACKAGE_PIN R3} [get_ports {qsfp_rx_n[1]}]
37+
set_property -dict {PACKAGE_PIN K7} [get_ports {qsfp_tx_p[1]}]
38+
set_property -dict {PACKAGE_PIN K6} [get_ports {qsfp_tx_n[1]}]
39+
set_property -dict {PACKAGE_PIN P2} [get_ports {qsfp_rx_p[2]}]
40+
set_property -dict {PACKAGE_PIN P1} [get_ports {qsfp_rx_n[2]}]
41+
set_property -dict {PACKAGE_PIN J5} [get_ports {qsfp_tx_p[2]}]
42+
set_property -dict {PACKAGE_PIN J4} [get_ports {qsfp_tx_n[2]}]
43+
set_property -dict {PACKAGE_PIN M2} [get_ports {qsfp_rx_p[3]}]
44+
set_property -dict {PACKAGE_PIN M1} [get_ports {qsfp_rx_n[3]}]
45+
set_property -dict {PACKAGE_PIN H7} [get_ports {qsfp_tx_p[3]}]
46+
set_property -dict {PACKAGE_PIN H6} [get_ports {qsfp_tx_n[3]}]
47+
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set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_modsell]
49+
set_property -dict {PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_resetl]
50+
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_lpmode]
51+
set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports qsfp_modprsl]
52+
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports qsfp_intl]
53+
54+
# REF clock
55+
set_property -dict {PACKAGE_PIN W9} [get_ports qsfp_mgt_refclk_p]
56+
set_property -dict {PACKAGE_PIN W8} [get_ports qsfp_mgt_refclk_n]
57+
58+
# 156.25 MHz MGT reference clock
59+
create_clock -period 6.400 -name qsfp_mgt_refclk [get_ports qsfp_mgt_refclk_p]
60+
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set_false_path -to [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
62+
set_output_delay 0.000 [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
63+
set_false_path -from [get_ports {qsfp_modprsl qsfp_intl}]
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set_input_delay 0.000 [get_ports {qsfp_modprsl qsfp_intl}]
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# QSPI flash
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set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[0]}]
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set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[1]}]
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set_property -dict {PACKAGE_PIN AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[2]}]
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set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[3]}]
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set_property -dict {PACKAGE_PIN BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports qspi1_cs]
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set_false_path -to [get_ports {{qspi1_dq[*]} qspi1_cs}]
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set_output_delay 0.000 [get_ports {{qspi1_dq[*]} qspi1_cs}]
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set_false_path -from [get_ports qspi1_dq]
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set_input_delay 0.000 [get_ports qspi1_dq]
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set_property LOC CMACE4_X0Y7 [get_cells -hierarchical -filter {NAME =~ */qsfp[0].qsfp_cmac_inst/cmac_inst/inst/i_cmac_usplus_top/* && REF_NAME==CMACE4}]

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