library:axi_ad408x: Fix filter capture

Fix shift register issue caused by filter_ready_n timing
The filter_ready_n signal stays HIGH for 2.5 adc_clk_div periods,
which causes the shift register to capture either 2 or 3 HIGH periods.
The solution is to activate the filter_ready signal at the fall edge
of the filter_ready_n and deactivate it after the first data valid.

Signed-off-by: PopPaul2021 <paul.pop@analog.com>

Author: PopPaul2021

library/axi_ad408x/ad408x_phy.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL(Verilog or VHDL) components. The individual modules are
@@ -134,6 +134,8 @@ module ad408x_phy #(
   wire [19:0]          pattern_value;
   wire [19:0]          packed_16_20;
   wire [19:0]          packed_8_20;
+  wire                 pack16_valid;
+  wire                 pack8_valid;
   wire                 adc_clk_div;
   wire [NUM_LANES-1:0] serdes_in_p;
   wire [NUM_LANES-1:0] serdes_in_n;
@@ -150,7 +152,8 @@ module ad408x_phy #(
   reg  [5:0]  serdes_reset = 6'b000110;
   reg         sync_status_int = 1'b0;
   reg  [1:0]  serdes_valid = 2'b00;
-  reg  [3:0]  filter_rdy_n_d = 'b0;
+  reg  [1:0]  filter_rdy_n_d = 'b0;
+  reg         filter_ready = 1'b0;
   reg         shift_cnt_en = 1'b0;
   reg         packed_data_valid_d;
   reg         packed_data_valid;
@@ -161,7 +164,7 @@ module ad408x_phy #(
   reg         slip_dd;
   reg         slip_d;
 
-  assign fall_filter_ready = filter_rdy_n_d[3] & ~filter_rdy_n_d[2];
+  assign fall_filter_ready = filter_rdy_n_d[1] & ~filter_rdy_n_d[0];
   assign sync_status       = sync_status_int;
   assign single_lane       = num_lanes[0];
   assign adc_clk           = adc_clk_div;
@@ -380,12 +383,20 @@ module ad408x_phy #(
   always @(posedge adc_clk_div) begin
     adc_data_shifted <= {packed_data_d,packed_data} >> shift_cnt;
     packed_data_valid_d <= packed_data_valid;
-    filter_rdy_n_d <= {filter_rdy_n_d[2:0], filter_rdy_n};
+  end
+
+  always @(posedge adc_clk_div) begin
+   filter_rdy_n_d <= {filter_rdy_n_d[0], filter_rdy_n};
+   if(fall_filter_ready) begin
+     filter_ready <= 1'b1;
+   end else if (packed_data_valid_d == 1'b1) begin
+     filter_ready <= 1'b0;
+   end
   end
 
   // Sign extend to 32 bits
 
   assign adc_data  = {{12{adc_data_shifted[19]}},adc_data_shifted};
-  assign adc_valid = filter_enable ?  (packed_data_valid_d & fall_filter_ready) : packed_data_valid_d;
+  assign adc_valid = filter_enable ?  (packed_data_valid_d & filter_ready) : packed_data_valid_d;
 
 endmodule