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| 1 | +.. _ad4062-ardz: |
| 2 | + |
| 3 | +AD4062-ARDZ HDL project |
| 4 | +================================================================================ |
| 5 | + |
| 6 | +Overview |
| 7 | +-------------------------------------------------------------------------------- |
| 8 | + |
| 9 | +The HDL reference design for the :adi:`AD4060`, :adi:`AD4062`. |
| 10 | +They are versatile, 16-bit/12-bit, successive approximation register (SAR) |
| 11 | +analog-to-digital converters (ADCs) that enable low-power, high-density data |
| 12 | +acquisition solutions without sacrificing precision. These ADCs offer a unique |
| 13 | +balance of performance and power efficiency, plus innovative features for |
| 14 | +seamlessly switching between high-resolution and low-power modes tailored to the |
| 15 | +immediate needs of the system. |
| 16 | + |
| 17 | +The :adi:`AD4060 <eval-ad4060-eval-ad4062>`/:adi:`AD4062 <eval-ad4060-eval-ad4062>` |
| 18 | +evaluation boards enable quick and easy evaluation of the performance and |
| 19 | +features of the :adi:`AD4060` or the :adi:`AD4062`, respectively. |
| 20 | + |
| 21 | +This project has an :ref:`i3c_controller` instance to control and acquire data |
| 22 | +from the precision ADC. |
| 23 | + |
| 24 | +Supported boards |
| 25 | +------------------------------------------------------------------------------- |
| 26 | + |
| 27 | +- :adi:`EVAL-AD4060` |
| 28 | +- :adi:`EVAL-AD4062` |
| 29 | + |
| 30 | +Supported devices |
| 31 | +------------------------------------------------------------------------------- |
| 32 | + |
| 33 | +- :adi:`AD4060` |
| 34 | +- :adi:`AD4062` |
| 35 | + |
| 36 | +Supported carriers |
| 37 | +------------------------------------------------------------------------------- |
| 38 | + |
| 39 | +- `Cora Z7S <https://digilent.com/shop/cora-z7-zynq-7000-single-core-for-arm-fpga-soc-development>`__ |
| 40 | + Arduino shield connector |
| 41 | +- :intel:`DE10-Nano <content/www/us/en/developer/topic-technology/edge-5g/hardware/fpga-de10-nano.html>` |
| 42 | + Arduino shield connector |
| 43 | + |
| 44 | +Block design |
| 45 | +------------------------------------------------------------------------------- |
| 46 | + |
| 47 | +Block diagram |
| 48 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 49 | + |
| 50 | +The data path and clock domains are depicted in the below diagram: |
| 51 | + |
| 52 | +.. image:: ad4062_hdl.svg |
| 53 | + :width: 800 |
| 54 | + :align: center |
| 55 | + :alt: AD4062-ARDZ block diagram |
| 56 | + |
| 57 | +CPU/Memory interconnects addresses |
| 58 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 59 | + |
| 60 | +The addresses are dependent on the architecture of the FPGA, having an offset |
| 61 | +added to the base address from HDL (see more at :ref:`architecture`). |
| 62 | + |
| 63 | +.. table:: Cora Z7S |
| 64 | + |
| 65 | + ============== =========== |
| 66 | + Instance Address |
| 67 | + ============== =========== |
| 68 | + i3c_controller 0x44A0_0000 |
| 69 | + ============== =========== |
| 70 | + |
| 71 | +.. table:: DE10-Nano |
| 72 | + |
| 73 | + ============== =========== |
| 74 | + Instance Address |
| 75 | + ============== =========== |
| 76 | + i3c_controller 0x0003_0000 |
| 77 | + ============== =========== |
| 78 | + |
| 79 | +I3C/I2C connections |
| 80 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 81 | + |
| 82 | +.. list-table:: Cora Z7s |
| 83 | + :header-rows: 1 |
| 84 | + |
| 85 | + * - I2C/I3C subordinate |
| 86 | + - address |
| 87 | + - I3C manager |
| 88 | + * - EEPROM |
| 89 | + - 0x52 |
| 90 | + - i3c_controller |
| 91 | + * - ADC |
| 92 | + - i3c_controller |
| 93 | + - Provisioned PID |
| 94 | + |
| 95 | +.. list-table:: DE10-Nano |
| 96 | + :header-rows: 1 |
| 97 | + |
| 98 | + * - I2C/I3C subordinate |
| 99 | + - EEPROM |
| 100 | + - I3C manager |
| 101 | + * - EEPROM |
| 102 | + - 0x52 |
| 103 | + - i3c_controller |
| 104 | + * - ADC |
| 105 | + - i3c_controller |
| 106 | + - Provisioned PID |
| 107 | + |
| 108 | + |
| 109 | +.. caution:: |
| 110 | + |
| 111 | + By default, the DE10-Nano does not populate the passive pull-up in the SDA |
| 112 | + lane (DNI). Either populate the DE10-Nano's resistor R1 with a 2.2k ohm |
| 113 | + resistor, or use the ``WEAK_PULL_UP_RESISTOR`` to the ``i3c_sda`` pin. |
| 114 | + |
| 115 | +Device address considering the EEPROM address pins ``A0=0``, ``A1=1``, ``A2=0``. |
| 116 | +For the ADC, check the part datasheet and the set address pins. |
| 117 | + |
| 118 | +GPIOs |
| 119 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 120 | + |
| 121 | +The Software GPIO number is calculated as follows: |
| 122 | + |
| 123 | +- Cora Z7S: the offset is 54 |
| 124 | + |
| 125 | +.. list-table:: |
| 126 | + :widths: 25 25 25 25 |
| 127 | + :header-rows: 2 |
| 128 | + |
| 129 | + * - GPIO signal |
| 130 | + - Direction |
| 131 | + - HDL GPIO EMIO |
| 132 | + - Software GPIO |
| 133 | + * - |
| 134 | + - (from FPGA view) |
| 135 | + - |
| 136 | + - Zynq-7000 |
| 137 | + * - adc_gp1 |
| 138 | + - INOUT |
| 139 | + - 33 |
| 140 | + - 87 |
| 141 | + * - adc_gp0 |
| 142 | + - INOUT |
| 143 | + - 32 |
| 144 | + - 86 |
| 145 | + |
| 146 | +- DE10-Nano: the offset is 32 |
| 147 | + |
| 148 | +.. list-table:: |
| 149 | + :widths: 25 25 25 25 |
| 150 | + :header-rows: 2 |
| 151 | + |
| 152 | + * - GPIO signal |
| 153 | + - Direction |
| 154 | + - HDL GPIO EMIO |
| 155 | + - Software GPIO |
| 156 | + * - |
| 157 | + - (from FPGA view) |
| 158 | + - |
| 159 | + - |
| 160 | + * - adc_gp1 |
| 161 | + - INPUT |
| 162 | + - 33 |
| 163 | + - 1 |
| 164 | + * - adc_gp0 |
| 165 | + - INPUT |
| 166 | + - 32 |
| 167 | + - 0 |
| 168 | + |
| 169 | +Interrupts |
| 170 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 171 | + |
| 172 | +Below are the Programmable Logic interrupts used in this project. |
| 173 | + |
| 174 | +=================== === ========== =========== |
| 175 | +Instance name HDL Linux Zynq Actual Zynq |
| 176 | +=================== === ========== =========== |
| 177 | +i3c_controller 12 56 88 |
| 178 | +=================== === ========== =========== |
| 179 | + |
| 180 | +================ === =============== ================ |
| 181 | +Instance name HDL Linux DE10-Nano Actual DE10-Nano |
| 182 | +================ === =============== ================ |
| 183 | +i3c_controller 5 45 77 |
| 184 | +================ === =============== ================ |
| 185 | + |
| 186 | +Building the HDL project |
| 187 | +------------------------------------------------------------------------------- |
| 188 | + |
| 189 | +The design is built upon ADI's generic HDL reference design framework. |
| 190 | +ADI distributes the bit/elf files of these projects as part of the |
| 191 | +:dokuwiki:`ADI Kuiper Linux <resources/tools-software/linux-software/kuiper-linux>`. |
| 192 | +If you want to build the sources, ADI makes them available on the |
| 193 | +:git-hdl:`HDL repository </>`. To get the source you must |
| 194 | +`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__ |
| 195 | +the HDL repository, and then build the project as follows: |
| 196 | + |
| 197 | +**Linux/Cygwin/WSL** |
| 198 | + |
| 199 | +.. shell:: |
| 200 | + |
| 201 | + $cd hdl/projects/ad4062_ardz/coraz7s |
| 202 | + $make |
| 203 | + |
| 204 | +.. shell:: |
| 205 | + |
| 206 | + $cd hdl/projects/ad4062_ardz/de10nano |
| 207 | + $make |
| 208 | + |
| 209 | +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. |
| 210 | + |
| 211 | +Resources |
| 212 | +------------------------------------------------------------------------------- |
| 213 | + |
| 214 | +Hardware related |
| 215 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 216 | + |
| 217 | +- Product datasheets: |
| 218 | + |
| 219 | + - :adi:`AD4060` |
| 220 | + - :adi:`AD4062` |
| 221 | + |
| 222 | +HDL related |
| 223 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 224 | + |
| 225 | +- :git-hdl:`AD4062-ARDZ HDL project source code <projects/ad4062-ardz>` |
| 226 | + |
| 227 | +.. list-table:: |
| 228 | + :widths: 30 35 35 |
| 229 | + :header-rows: 1 |
| 230 | + |
| 231 | + * - IP name |
| 232 | + - Source code link |
| 233 | + - Documentation link |
| 234 | + * - AXI_SYSID |
| 235 | + - :git-hdl:`library/axi_sysid <library/axi_sysid>` |
| 236 | + - :ref:`here <axi_sysid>` |
| 237 | + * - AXI_HDMI_TX |
| 238 | + - :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>` * |
| 239 | + - :ref:`here <axi_hdmi_tx>` |
| 240 | + * - I3C_CONTROLLER_HOST_INTERFACE |
| 241 | + - :git-hdl:`library/i3c_controller/i3c_controller_host_interface` |
| 242 | + - :ref:`here <i3c_controller host_interface>` |
| 243 | + * - I3C_CONTROLLER_CORE |
| 244 | + - :git-hdl:`library/i3c_controller/i3c_controller_core` |
| 245 | + - :ref:`here <i3c_controller core>` |
| 246 | + * - SYSID_ROM |
| 247 | + - :git-hdl:`library/sysid_rom <library/sysid_rom>` |
| 248 | + - :ref:`here <axi_sysid>` |
| 249 | + |
| 250 | + |
| 251 | +.. admonition:: Legend |
| 252 | + :class: note |
| 253 | + |
| 254 | + - ``*`` instantiated only for DE10-Nano |
| 255 | + |
| 256 | +- :ref:`I3C Controller documentation <i3c_controller>` |
| 257 | + |
| 258 | +.. include:: ../common/more_information.rst |
| 259 | + |
| 260 | +.. include:: ../common/support.rst |
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