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IstvanZsSzekelyIstvanZsSzekely
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ad9081: Updated to support Corundum Network Stack
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
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+512
-11
lines changed

5 files changed

+512
-11
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‎projects/ad9081_fmca_ebz/vcu118/Makefile

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,21 @@ M_DEPS += ../../../library/common/ad_iobuf.v
2121
M_DEPS += ../../../library/common/ad_3w_spi.v
2222
M_DEPS += ../../../library/axi_tdd/scripts/axi_tdd.tcl
2323

24+
M_DEPS += ../../../library/corundum/scripts/corundum_vcu118_cfg.tcl
25+
M_DEPS += ../../../library/corundum/scripts/corundum.tcl
26+
27+
M_DEPS += ../../../library/corundum/scripts/sync_reset.tcl
28+
29+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/rb_drp.tcl
30+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/cmac_gty_wrapper.tcl
31+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
32+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
33+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl
34+
EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_port.tcl
35+
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
36+
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl
37+
EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl
38+
2439
LIB_DEPS += axi_dmac
2540
LIB_DEPS += axi_sysid
2641
LIB_DEPS += axi_tdd
@@ -42,5 +57,9 @@ LIB_DEPS += util_pack/util_cpack2
4257
LIB_DEPS += util_pack/util_upack2
4358
LIB_DEPS += xilinx/axi_adxcvr
4459
LIB_DEPS += xilinx/util_adxcvr
60+
LIB_DEPS += corundum/corundum_core
61+
LIB_DEPS += corundum/ethernet
62+
63+
export BOARD := VCU118
4564

4665
include ../../scripts/project-xilinx.mk

‎projects/ad9081_fmca_ebz/vcu118/system_bd.tcl

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,3 +143,138 @@ if {$ad_project_params(JESD_MODE) == "64B66B"} {
143143
}
144144

145145
}
146+
147+
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_250mhz_clk1
148+
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram_c1_062
149+
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set INPUT_CHANNELS $RX_NUM_OF_CONVERTERS
151+
set INPUT_SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL
152+
set INPUT_SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH
153+
154+
set INPUT_WIDTH [expr $INPUT_CHANNELS*$INPUT_SAMPLES_PER_CHANNEL*$INPUT_SAMPLE_DATA_WIDTH]
155+
156+
set OUTPUT_CHANNELS $TX_NUM_OF_CONVERTERS
157+
set OUTPUT_SAMPLES $TX_SAMPLES_PER_CHANNEL
158+
set OUTPUT_SAMPLE_WIDTH $TX_DMA_SAMPLE_WIDTH
159+
160+
set OUTPUT_WIDTH [expr $OUTPUT_CHANNELS*$OUTPUT_SAMPLES*$OUTPUT_SAMPLE_WIDTH]
161+
162+
set CPU MB
163+
164+
source $ad_hdl_dir/library/corundum/scripts/corundum_vcu118_cfg.tcl
165+
source $ad_hdl_dir/library/corundum/scripts/corundum.tcl
166+
167+
ad_ip_parameter axi_dp_interconnect CONFIG.NUM_CLKS 3
168+
ad_connect axi_dp_interconnect/aclk2 sys_250m_clk
169+
170+
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 125
171+
set_property name sys_125m_rstgen [get_bd_cells sys_500m_rstgen]
172+
173+
ad_connect corundum_rstgen/slowest_sync_clk sys_250m_clk
174+
ad_connect corundum_rstgen/ext_reset_in axi_ddr_cntrl/c0_ddr4_ui_clk_sync_rst
175+
176+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi0
177+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qspi_rtl:1.0 qspi1
178+
create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qsfp_rtl:1.0 qsfp
179+
180+
create_bd_port -dir O -from 0 -to 0 -type rst qsfp_rst
181+
create_bd_port -dir O fpga_boot
182+
create_bd_port -dir O -type clk qspi_clk
183+
create_bd_port -dir I -type rst ptp_rst
184+
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports ptp_rst]
185+
create_bd_port -dir I -type clk qsfp_mgt_refclk
186+
create_bd_port -dir I -type clk qsfp_mgt_refclk_bufg
187+
188+
create_bd_port -dir O -type clk clk_125mhz
189+
create_bd_port -dir O -type clk clk_250mhz
190+
191+
ad_connect sys_500m_clk clk_125mhz
192+
ad_connect sys_250m_clk clk_250mhz
193+
194+
ad_connect corundum_hierarchy/clk_125mhz clk_125mhz
195+
ad_connect corundum_hierarchy/clk_corundum sys_250m_clk
196+
197+
ad_connect corundum_hierarchy/rst_125mhz sys_125m_rstgen/peripheral_reset
198+
199+
ad_connect corundum_hierarchy/qspi0 qspi0
200+
ad_connect corundum_hierarchy/qspi1 qspi1
201+
ad_connect corundum_hierarchy/qsfp qsfp
202+
ad_connect corundum_hierarchy/qsfp_rst qsfp_rst
203+
ad_connect corundum_hierarchy/fpga_boot fpga_boot
204+
ad_connect corundum_hierarchy/qspi_clk qspi_clk
205+
ad_connect corundum_hierarchy/ptp_rst ptp_rst
206+
ad_connect corundum_hierarchy/qsfp_mgt_refclk qsfp_mgt_refclk
207+
ad_connect corundum_hierarchy/qsfp_mgt_refclk_bufg qsfp_mgt_refclk_bufg
208+
209+
ad_cpu_interconnect 0x50000000 corundum_hierarchy s_axil_corundum
210+
ad_cpu_interconnect 0x52000000 corundum_gpio_reset
211+
212+
ad_mem_hp1_interconnect sys_250m_clk corundum_hierarchy/m_axi
213+
214+
ad_cpu_interrupt "ps-5" "mb-5" corundum_hierarchy/irq
215+
216+
if {$APP_ENABLE == 1} {
217+
ad_cpu_interconnect 0x51000000 corundum_hierarchy s_axil_application
218+
219+
ad_ip_instance util_cpack2 util_corundum_cpack [list \
220+
NUM_OF_CHANNELS $INPUT_CHANNELS \
221+
SAMPLES_PER_CHANNEL $INPUT_SAMPLES_PER_CHANNEL \
222+
SAMPLE_DATA_WIDTH $INPUT_SAMPLE_DATA_WIDTH \
223+
]
224+
225+
ad_connect util_corundum_cpack/clk rx_device_clk
226+
ad_connect util_corundum_cpack/fifo_wr_en rx_mxfe_tpl_core/adc_valid_0
227+
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
228+
ad_connect util_corundum_cpack/enable_${i} rx_mxfe_tpl_core/adc_enable_${i}
229+
ad_connect util_corundum_cpack/fifo_wr_data_${i} rx_mxfe_tpl_core/adc_data_${i}
230+
}
231+
232+
ad_connect corundum_hierarchy/input_clk axi_mxfe_rx_jesd/device_clk
233+
ad_connect corundum_hierarchy/input_rstn rx_device_clk_rstgen/peripheral_aresetn
234+
235+
ad_connect corundum_hierarchy/output_clk axi_mxfe_tx_jesd/device_clk
236+
ad_connect corundum_hierarchy/output_rstn tx_device_clk_rstgen/peripheral_aresetn
237+
238+
ad_connect corundum_hierarchy/input_axis_tvalid util_corundum_cpack/packed_fifo_wr_en
239+
ad_connect corundum_hierarchy/input_axis_tdata util_corundum_cpack/packed_fifo_wr_data
240+
ad_connect corundum_hierarchy/input_axis_tready util_corundum_cpack/packed_fifo_wr_overflow
241+
242+
ad_ip_instance util_reduced_logic cpack_rst_logic_corundum
243+
ad_ip_parameter cpack_rst_logic_corundum config.c_operation {or}
244+
ad_ip_parameter cpack_rst_logic_corundum config.c_size {4}
245+
246+
ad_ip_instance util_vector_logic rx_do_rstout_logic_corundum
247+
ad_ip_parameter rx_do_rstout_logic_corundum config.c_operation {not}
248+
ad_ip_parameter rx_do_rstout_logic_corundum config.c_size {1}
249+
250+
ad_ip_instance xlconcat cpack_reset_sources_corundum
251+
ad_ip_parameter cpack_reset_sources_corundum config.num_ports {4}
252+
253+
ad_connect corundum_hierarchy/input_axis_tready rx_do_rstout_logic_corundum/Op1
254+
255+
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources_corundum/in0
256+
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources_corundum/in1
257+
ad_connect rx_do_rstout_logic_corundum/res cpack_reset_sources_corundum/in2
258+
ad_connect corundum_hierarchy/input_packer_reset cpack_reset_sources_corundum/in3
259+
260+
ad_connect cpack_reset_sources_corundum/dout cpack_rst_logic_corundum/op1
261+
ad_connect cpack_rst_logic_corundum/res util_corundum_cpack/reset
262+
263+
ad_ip_instance xlconcat input_enable_concat_corundum
264+
ad_ip_parameter input_enable_concat_corundum config.num_ports $INPUT_CHANNELS
265+
266+
for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
267+
ad_connect input_enable_concat_corundum/In${i} rx_mxfe_tpl_core/adc_enable_${i}
268+
}
269+
270+
ad_connect input_enable_concat_corundum/dout corundum_hierarchy/input_enable
271+
272+
ad_ip_instance xlconcat output_enable_concat_corundum
273+
ad_ip_parameter output_enable_concat_corundum config.num_ports $OUTPUT_CHANNELS
274+
275+
for {set i 0} {$i<$OUTPUT_CHANNELS} {incr i} {
276+
ad_connect output_enable_concat_corundum/In${i} tx_mxfe_tpl_core/dac_enable_${i}
277+
}
278+
279+
ad_connect output_enable_concat_corundum/dout corundum_hierarchy/output_enable
280+
}

‎projects/ad9081_fmca_ebz/vcu118/system_constr.xdc

Lines changed: 72 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -17,11 +17,11 @@ set_property -dict {PACKAGE_PIN M35 IOSTANDARD LVCMOS18
1717
set_property -dict {PACKAGE_PIN L35 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## IO_L24N_T3U_N11_45
1818
set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_n ] ; ## IO_L14N_T2L_N3_GC_45
1919
set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports clkin6_p ] ; ## IO_L14P_T2L_N2_GC_45
20-
set_property -dict {PACKAGE_PIN AM39 } [get_ports clkin8_n ] ; ## MGTREFCLK1N_120
21-
set_property -dict {PACKAGE_PIN AM38 } [get_ports clkin8_p ] ; ## MGTREFCLK1P_120
22-
set_property -dict {PACKAGE_PIN AK39 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_121
23-
set_property -dict {PACKAGE_PIN AK38 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_121
24-
set_property -dict {PACKAGE_PIN V39 } [get_ports fpga_refclk_in_replica_n ] ; ## MGTREFCLK0N_126
20+
set_property -dict {PACKAGE_PIN AM39 } [get_ports clkin8_n ] ; ## MGTREFCLK1N_120
21+
set_property -dict {PACKAGE_PIN AM38 } [get_ports clkin8_p ] ; ## MGTREFCLK1P_120
22+
set_property -dict {PACKAGE_PIN AK39 } [get_ports fpga_refclk_in_n ] ; ## MGTREFCLK0N_121
23+
set_property -dict {PACKAGE_PIN AK38 } [get_ports fpga_refclk_in_p ] ; ## MGTREFCLK0P_121
24+
set_property -dict {PACKAGE_PIN V39 } [get_ports fpga_refclk_in_replica_n ] ; ## MGTREFCLK0N_126
2525
set_property -dict {PACKAGE_PIN V38 } [get_ports fpga_refclk_in_replica_p ] ; ## MGTREFCLK0P_126
2626
set_property -quiet -dict {PACKAGE_PIN AL46 } [get_ports rx_data_n[2] ] ; ## MGTYRXN2_121 FPGA_SERDIN_0_N
2727
set_property -quiet -dict {PACKAGE_PIN AL45 } [get_ports rx_data_p[2] ] ; ## MGTYRXP2_121 FPGA_SERDIN_0_P
@@ -55,7 +55,7 @@ set_property -quiet -dict {PACKAGE_PIN T43
5555
set_property -quiet -dict {PACKAGE_PIN T42 } [get_ports tx_data_p[4] ] ; ## MGTYTXP0_126 FPGA_SERDOUT_6_P
5656
set_property -quiet -dict {PACKAGE_PIN AL41 } [get_ports tx_data_n[3] ] ; ## MGTYTXN3_121 FPGA_SERDOUT_7_N
5757
set_property -quiet -dict {PACKAGE_PIN AL40 } [get_ports tx_data_p[3] ] ; ## MGTYTXP3_121 FPGA_SERDOUT_7_P
58-
set_property -quiet -dict {PACKAGE_PIN AK32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[0] ] ; ## IO_L14N_T2L_N3_GC_43
58+
set_property -quiet -dict {PACKAGE_PIN AK32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[0] ] ; ## IO_L14N_T2L_N3_GC_43
5959
set_property -quiet -dict {PACKAGE_PIN AJ32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_p[0] ] ; ## IO_L14P_T2L_N2_GC_43
6060
set_property -quiet -dict {PACKAGE_PIN AT40 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[1] ] ; ## IO_L4N_T0U_N7_DBC_AD7N_43
6161
set_property -quiet -dict {PACKAGE_PIN AT39 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_p[1] ] ; ## IO_L4P_T0U_N6_DBC_AD7P_43
@@ -93,7 +93,72 @@ set_property -dict {PACKAGE_PIN AL32 IOSTANDARD LVDS DIFF_TERM_ADV T
9393
set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## IO_L19P_T3L_N0_DBC_AD9P_43
9494
set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## IO_L19N_T3L_N1_DBC_AD9N_43
9595

96-
set_property -dict {PACKAGE_PIN AK35 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports vadj_1v8_pgood ] ; ## IO_T1U_N12_43_AK35
96+
set_property -dict {PACKAGE_PIN AK35 IOSTANDARD LVCMOS18 PULLTYPE PULLUP } [get_ports vadj_1v8_pgood ] ; ## IO_T1U_N12_43_AK35
9797

98+
# U145 QSFP+ Module QSFP1
99+
# set_property -dict {PACKAGE_PIN Y2} [get_ports {qsfp_rx_p[0]}]
100+
# set_property -dict {PACKAGE_PIN Y1} [get_ports {qsfp_rx_n[0]}]
101+
# set_property -dict {PACKAGE_PIN V7} [get_ports {qsfp_tx_p[0]}]
102+
# set_property -dict {PACKAGE_PIN V6} [get_ports {qsfp_tx_n[0]}]
103+
# set_property -dict {PACKAGE_PIN W4} [get_ports {qsfp_rx_p[1]}]
104+
# set_property -dict {PACKAGE_PIN W3} [get_ports {qsfp_rx_n[1]}]
105+
# set_property -dict {PACKAGE_PIN T7} [get_ports {qsfp_tx_p[1]}]
106+
# set_property -dict {PACKAGE_PIN T6} [get_ports {qsfp_tx_n[1]}]
107+
# set_property -dict {PACKAGE_PIN V2} [get_ports {qsfp_rx_p[2]}]
108+
# set_property -dict {PACKAGE_PIN V1} [get_ports {qsfp_rx_n[2]}]
109+
# set_property -dict {PACKAGE_PIN P7} [get_ports {qsfp_tx_p[2]}]
110+
# set_property -dict {PACKAGE_PIN P6} [get_ports {qsfp_tx_n[2]}]
111+
# set_property -dict {PACKAGE_PIN U4} [get_ports {qsfp_rx_p[3]}]
112+
# set_property -dict {PACKAGE_PIN U3} [get_ports {qsfp_rx_n[3]}]
113+
# set_property -dict {PACKAGE_PIN M7} [get_ports {qsfp_tx_p[3]}]
114+
# set_property -dict {PACKAGE_PIN M6} [get_ports {qsfp_tx_n[3]}]
98115

116+
# U145 QSFP+ Module QSFP2
117+
set_property -dict {PACKAGE_PIN T2} [get_ports {qsfp_rx_p[0]}]
118+
set_property -dict {PACKAGE_PIN T1} [get_ports {qsfp_rx_n[0]}]
119+
set_property -dict {PACKAGE_PIN L5} [get_ports {qsfp_tx_p[0]}]
120+
set_property -dict {PACKAGE_PIN L4} [get_ports {qsfp_tx_n[0]}]
121+
set_property -dict {PACKAGE_PIN R4} [get_ports {qsfp_rx_p[1]}]
122+
set_property -dict {PACKAGE_PIN R3} [get_ports {qsfp_rx_n[1]}]
123+
set_property -dict {PACKAGE_PIN K7} [get_ports {qsfp_tx_p[1]}]
124+
set_property -dict {PACKAGE_PIN K6} [get_ports {qsfp_tx_n[1]}]
125+
set_property -dict {PACKAGE_PIN P2} [get_ports {qsfp_rx_p[2]}]
126+
set_property -dict {PACKAGE_PIN P1} [get_ports {qsfp_rx_n[2]}]
127+
set_property -dict {PACKAGE_PIN J5} [get_ports {qsfp_tx_p[2]}]
128+
set_property -dict {PACKAGE_PIN J4} [get_ports {qsfp_tx_n[2]}]
129+
set_property -dict {PACKAGE_PIN M2} [get_ports {qsfp_rx_p[3]}]
130+
set_property -dict {PACKAGE_PIN M1} [get_ports {qsfp_rx_n[3]}]
131+
set_property -dict {PACKAGE_PIN H7} [get_ports {qsfp_tx_p[3]}]
132+
set_property -dict {PACKAGE_PIN H6} [get_ports {qsfp_tx_n[3]}]
99133

134+
# REF clock
135+
set_property -dict {PACKAGE_PIN W9} [get_ports qsfp_mgt_refclk_p]
136+
set_property -dict {PACKAGE_PIN W8} [get_ports qsfp_mgt_refclk_n]
137+
138+
# 156.25 MHz MGT reference clock
139+
create_clock -period 6.400 -name qsfp_mgt_refclk [get_ports qsfp_mgt_refclk_p]
140+
141+
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_modsell]
142+
set_property -dict {PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_resetl]
143+
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_lpmode]
144+
set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports qsfp_modprsl]
145+
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports qsfp_intl]
146+
147+
set_false_path -to [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
148+
set_output_delay 0.000 [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
149+
set_false_path -from [get_ports {qsfp_modprsl qsfp_intl}]
150+
set_input_delay 0.000 [get_ports {qsfp_modprsl qsfp_intl}]
151+
152+
# QSPI flash
153+
set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[0]}]
154+
set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[1]}]
155+
set_property -dict {PACKAGE_PIN AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[2]}]
156+
set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi1_dq[3]}]
157+
set_property -dict {PACKAGE_PIN BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports qspi1_cs]
158+
159+
set_false_path -to [get_ports {{qspi1_dq[*]} qspi1_cs}]
160+
set_output_delay 0.000 [get_ports {{qspi1_dq[*]} qspi1_cs}]
161+
set_false_path -from [get_ports qspi1_dq]
162+
set_input_delay 0.000 [get_ports qspi1_dq]
163+
164+
set_property LOC CMACE4_X0Y7 [get_cells -hierarchical -filter {NAME =~ */qsfp[0].qsfp_cmac_inst/cmac_inst/inst/i_cmac_usplus_top/* && REF_NAME==CMACE4}]

‎projects/ad9081_fmca_ebz/vcu118/system_project.tcl

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,14 +60,28 @@ adi_project_files ad9081_fmca_ebz_vcu118 [list \
6060
"timing_constr.xdc"\
6161
"../../../library/common/ad_3w_spi.v"\
6262
"$ad_hdl_dir/library/common/ad_iobuf.v" \
63-
"$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ]
63+
"$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" \
64+
"$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/boot.xdc" \
65+
"$ad_hdl_dir/../corundum/fpga/mqnic/VCU118/fpga_100g/rtl/sync_signal.v" \
66+
]
67+
68+
add_files -fileset constrs_1 -norecurse [list \
69+
"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/rb_drp.tcl" \
70+
"$ad_hdl_dir/library/corundum/scripts/sync_reset.tcl" \
71+
"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/cmac_gty_wrapper.tcl" \
72+
"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl" \
73+
"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl" \
74+
"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl" \
75+
"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_port.tcl" \
76+
"$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl" \
77+
"$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl" \
78+
"$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl" \
79+
]
6480

6581
# Avoid critical warning in OOC mode from the clock definitions
6682
# since at that stage the submodules are not stiched together yet
6783
if {$ADI_USE_OOC_SYNTHESIS == 1} {
6884
set_property used_in_synthesis false [get_files timing_constr.xdc]
6985
}
7086

71-
set_property strategy Performance_RefinePlacement [get_runs impl_1]
72-
7387
adi_project_run ad9081_fmca_ebz_vcu118

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