ad9213_evb: Add VADJ value

Signed-off-by: Stanca Pop <stanca.pop@analog.com>

Author: StancaPop

projects/ad9213_evb/README.md

@@ -3,6 +3,7 @@
 - Evaluation board product page: [EVAL-AD213](https://www.analog.com/eval-ad9213)
 - System documentation: TO BE ADDED
 - HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad9213_evb/index.html
+- Evaluation board VADJ: 1.8V
 
 ## Supported parts
 
@@ -12,4 +13,4 @@
 
 ## Building the project
 
-Please enter the folder for the FPGA carrier you want to use and read the README.md.
+Please enter the folder for the FPGA carrier you want to use and read the README.md.

projects/ad9213_evb/vcu118/README.md

@@ -1,5 +1,9 @@
+<!-- no_build_example, no_no_os, no_dts -->
+
 # AD9213/VCU118 HDL Project
 
+- VADJ with which it was tested in hardware: 1.8V
+
 ## Building the project
 
 ```
@@ -17,4 +21,4 @@ The parameters from the environment:
 - RX_NUM_OF_LANES: **16**; RX number of lanes per link
 - RX_SAMPLES_PER_FRAME: **16**; RX number of samples per converter per frame
 - RX_JESD_NP: **16**; RX number of bits per sample
-- RX_SAMPLE_WIDTH: **16**; RX data width
+- RX_SAMPLE_WIDTH: **16**; RX data width