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library/ada4355: Fix indentation issues
Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
1 parent 9bb01af commit 06f7d4b

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+75
-76
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+75
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‎library/axi_ada4355/axi_ada4355_if.v

+38-39
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,8 @@ module axi_ada4355_if #(
9090
localparam [ 7:0] pattern_value = 8'hF0;
9191
localparam [15:0] expected_pattern_lane_0 = 16'h5554;
9292
localparam [15:0] expected_pattern_lane_1 = 16'hAAA8;
93+
localparam [15:0] lane_0_mask = 16'h5555;
94+
localparam [15:0] lane_1_mask = 16'hAAAA;
9395

9496
wire clk_in_s;
9597
wire out_ibufmrce_clock;
@@ -123,8 +125,8 @@ module axi_ada4355_if #(
123125
reg [ 9:0] serdes_reset = 10'b0000000110;
124126
reg [ 1:0] serdes_valid = 2'b00;
125127
reg [ 1:0] serdes_valid_d = 2'b00;
126-
reg [ 2:0] shift_cnt = 3'd0;
127-
reg [ 4:0] delay = 5'd0;
128+
reg [ 2:0] shift_cnt = 3'h0;
129+
reg [ 4:0] delay = 5'h0;
128130
reg [15:0] serdes_data;
129131
reg [15:0] serdes_data_d;
130132
reg [ 7:0] serdes_frame;
@@ -138,8 +140,6 @@ module axi_ada4355_if #(
138140
reg frame_err_r;
139141
reg data_err_lane_0_r;
140142
reg data_err_lane_1_r;
141-
reg [15:0] lane_0_mask = 16'h5555;
142-
reg [15:0] lane_1_mask = 16'hAAAA;
143143
reg [15:0] test_pattern;
144144

145145
IBUFGDS i_clk_in_ibuf(
@@ -254,10 +254,10 @@ module axi_ada4355_if #(
254254
always @(posedge adc_clk_div or negedge sync_n) begin
255255
if(~sync_n) begin
256256
serdes_reset <= 10'b0000000110;
257-
end else begin
258-
serdes_reset <= {serdes_reset[8:0],1'b0};
259-
end
257+
end else begin
258+
serdes_reset <= {serdes_reset[8:0],1'b0};
260259
end
260+
end
261261

262262
assign serdes_reset_s = serdes_reset[5];
263263
assign serdes_reset_d = serdes_reset[9];
@@ -349,48 +349,47 @@ module axi_ada4355_if #(
349349
frame_shifted <= serdes_frame;
350350
end else begin
351351
case (state)
352-
INIT : begin
353-
if (frame_shifted != pattern_value) begin
354-
state <= CNT_UPDATE;
355-
end else begin
356-
frame_shifted <= {serdes_frame, serdes_frame_d} >> shift_cnt;
357-
if (expected_pattern_lane_0 == (test_pattern & lane_0_mask)) begin
358-
data_err_lane_0_r <= 1'b0;
352+
INIT : begin
353+
if (frame_shifted != pattern_value) begin
354+
state <= CNT_UPDATE;
359355
end else begin
360-
data_err_lane_0_r <= 1'b1;
356+
frame_shifted <= {serdes_frame, serdes_frame_d} >> shift_cnt;
357+
if (expected_pattern_lane_0 == (test_pattern & lane_0_mask)) begin
358+
data_err_lane_0_r <= 1'b0;
359+
end else begin
360+
data_err_lane_0_r <= 1'b1;
361+
end
362+
if (expected_pattern_lane_1 == (test_pattern & lane_1_mask)) begin
363+
data_err_lane_1_r <= 1'b0;
364+
end else begin
365+
data_err_lane_1_r <= 1'b1;
366+
end
367+
state <= INIT;
361368
end
362-
if (expected_pattern_lane_1 == (test_pattern & lane_1_mask)) begin
363-
data_err_lane_1_r <= 1'b0;
364-
end else begin
365-
data_err_lane_1_r <= 1'b1;
366-
end
367-
state <= INIT;
368369
end
369-
end
370-
CNT_UPDATE : begin
371-
if (shift_cnt == 3'b111) begin
372-
frame_err_r <= 1'b1;
373-
state <= RESET;
370+
CNT_UPDATE : begin
371+
if (shift_cnt == 3'b111) begin
372+
frame_err_r <= 1'b1;
373+
state <= RESET;
374+
end
375+
else begin
376+
frame_err_r <= 1'b0;
377+
end
378+
shift_cnt <= shift_cnt + 1;
379+
state <= FRAME_SHIFTED;
374380
end
375-
else begin
376-
frame_err_r <= 1'b0;
381+
FRAME_SHIFTED : begin
382+
frame_shifted <= {serdes_frame, serdes_frame_d} >> shift_cnt;
383+
state <= INIT;
377384
end
378-
shift_cnt <= shift_cnt + 1;
379-
state <= FRAME_SHIFTED;
380-
end
381-
FRAME_SHIFTED : begin
382-
frame_shifted <= {serdes_frame, serdes_frame_d} >> shift_cnt;
383-
state <= INIT;
384-
end
385-
RESET : begin
385+
RESET : begin
386386
shift_cnt <= 0;
387387
state <= INIT;
388388
frame_err_r <= 1'b0;
389389
data_err_lane_0_r <= 1'b0;
390390
data_err_lane_1_r <= 1'b0;
391-
end
392-
default :
393-
state <= INIT;
391+
end
392+
default: state <= INIT;
394393
endcase
395394
end
396395
end

‎library/axi_ada4355/axi_ada4355_regmap.v

+37-37
Original file line numberDiff line numberDiff line change
@@ -38,56 +38,56 @@ module axi_ada4355_regmap (
3838

3939
// processor interface
4040

41-
input up_rstn,
42-
input up_clk,
43-
input up_wreq,
44-
input [13:0] up_waddr,
45-
input [31:0] up_wdata,
46-
output reg up_wack,
47-
input up_rreq,
48-
input [13:0] up_raddr,
49-
output reg [31:0] up_rdata,
50-
output reg up_rack,
51-
input clk_div,
52-
output [ 2:0] enable_error_sync,
53-
input adc_rst
41+
input up_rstn,
42+
input up_clk,
43+
input up_wreq,
44+
input [13:0] up_waddr,
45+
input [31:0] up_wdata,
46+
output reg up_wack,
47+
input up_rreq,
48+
input [13:0] up_raddr,
49+
output reg [31:0] up_rdata,
50+
output reg up_rack,
51+
input clk_div,
52+
output [ 2:0] enable_error_sync,
53+
input adc_rst
5454
);
5555

5656
// internal registers
5757

5858
reg [ 2:0] up_enable_error = 'd0;
5959

60-
// processor write interface
60+
// processor write interface
6161

6262
always @(posedge up_clk) begin
63-
if (up_rstn == 0) begin
64-
up_wack <= 'd0;
65-
up_enable_error <= 'd0;
66-
end else begin
67-
up_wack <= up_wreq;
68-
if ((up_wreq == 1'b1) && (up_waddr[6:0] == 7'h32)) begin
69-
up_enable_error <= up_wdata[2:0];
70-
end
71-
end
63+
if (up_rstn == 0) begin
64+
up_wack <= 'd0;
65+
up_enable_error <= 'd0;
66+
end else begin
67+
up_wack <= up_wreq;
68+
if ((up_wreq == 1'b1) && (up_waddr[6:0] == 7'h32)) begin
69+
up_enable_error <= up_wdata[2:0];
70+
end
71+
end
7272
end
7373

7474
// processor read interface
7575

7676
always @(posedge up_clk) begin
77-
if (up_rstn == 0) begin
78-
up_rack <= 'd0;
79-
up_rdata <= 'd0;
80-
end else begin
81-
up_rack <= up_rreq;
82-
if (up_rreq == 1'b1) begin
83-
case (up_raddr)
84-
7'h32: up_rdata <= {29'd0, up_enable_error};
85-
default: up_rdata <= 0;
86-
endcase
87-
end else begin
88-
up_rdata <= 32'd0;
89-
end
90-
end
77+
if (up_rstn == 0) begin
78+
up_rack <= 'd0;
79+
up_rdata <= 'd0;
80+
end else begin
81+
up_rack <= up_rreq;
82+
if (up_rreq == 1'b1) begin
83+
case (up_raddr)
84+
7'h32: up_rdata <= {29'd0, up_enable_error};
85+
default: up_rdata <= 0;
86+
endcase
87+
end else begin
88+
up_rdata <= 32'd0;
89+
end
90+
end
9191
end
9292

9393
sync_bits #(

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