From 562f7e9bc851fb4e7f0b54bce26ea2884ce9a40b Mon Sep 17 00:00:00 2001 From: Wanda Date: Tue, 27 Feb 2024 11:44:06 +0100 Subject: [PATCH] back.rtlil: Emit proper source location for port-signals. --- amaranth/back/rtlil.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py index 6a1d8cc8b..34e4db023 100644 --- a/amaranth/back/rtlil.py +++ b/amaranth/back/rtlil.py @@ -289,6 +289,7 @@ def __init__(self, builder, netlist, module, name_map, empty_checker): self.memories = {} # cell idx -> MemoryInfo self.value_names = {} # value -> signal or port name self.value_attrs = {} # value -> dict + self.value_src_loc = {} # value -> source location self.sigport_wires = {} # signal or port name -> (wire, value) self.driven_sigports = set() # set of signal or port name self.nets = {} # net -> (wire name, bit idx) @@ -372,6 +373,7 @@ def emit_signal_wires(self): # the design is flattened) will do that anyway, so it doesn't matter. attrs = self.value_attrs.setdefault(value, {}) attrs.update(signal.attrs) + self.value_src_loc[value] = signal.src_loc for repr in signal._value_repr: if repr.path == () and isinstance(repr.format, _repr.FormatEnum): @@ -399,7 +401,8 @@ def emit_port_wires(self): signed = named_signals[name].signed wire = self.builder.wire(width=len(value), signed=signed, port_id=port_id, port_kind=flow.value, - name=name, attrs=self.value_attrs.get(value, {})) + name=name, attrs=self.value_attrs.get(value, {}), + src=_src(self.value_src_loc.get(value))) self.sigport_wires[name] = (wire, value) if flow == _nir.ModuleNetFlow.Output: continue