From d4b45f38c3724d509e880a04d656e1d331e671d8 Mon Sep 17 00:00:00 2001 From: Wanda Date: Tue, 27 Feb 2024 11:20:33 +0100 Subject: [PATCH] back.rtlil: Remove code allowing internal yosys cells in `Instance`. This was allowed only because Amaranth used it internally. Now that all uses are gone, let's just disallow it entirely. --- amaranth/back/rtlil.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py index f597b84ed..6a1d8cc8b 100644 --- a/amaranth/back/rtlil.py +++ b/amaranth/back/rtlil.py @@ -923,12 +923,8 @@ def emit_instance(self, cell_idx, cell): ports[name] = self.instance_wires[cell_idx, name] for name, nets in cell.ports_io.items(): ports[name] = self.sigspec(nets) - if cell.type.startswith("$"): - type = cell.type - else: - type = "\\" + cell.type - self.builder.cell(type, cell.name, ports=ports, params=cell.parameters, - attrs=cell.attributes, src=_src(cell.src_loc)) + self.builder.cell(f"\\{cell.type}", cell.name, ports=ports, params=cell.parameters, + attrs=cell.attributes, src=_src(cell.src_loc)) def emit_cells(self): for cell_idx in self.module.cells: