From f89552aba399cdbdf12c412a86630ca26b4c755a Mon Sep 17 00:00:00 2001 From: Wanda Date: Tue, 27 Feb 2024 03:02:44 +0100 Subject: [PATCH] back.rtlil: strip `\` from names added to `name_map`. Fixes #1154. --- amaranth/back/rtlil.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/amaranth/back/rtlil.py b/amaranth/back/rtlil.py index e046d158f..e3bcc0fc0 100644 --- a/amaranth/back/rtlil.py +++ b/amaranth/back/rtlil.py @@ -383,13 +383,13 @@ def emit_signal_wires(self): if name in self.module.ports: port_value, _flow = self.module.ports[name] assert value == port_value - self.name_map[signal] = (*self.module.name, f"\\{name}") + self.name_map[signal] = (*self.module.name, name) else: wire = self.builder.wire(width=signal.width, signed=signal.signed, name=name, attrs=attrs, src=_src(signal.src_loc)) self.sigport_wires[name] = (wire, value) - self.name_map[signal] = (*self.module.name, wire) + self.name_map[signal] = (*self.module.name, wire[1:]) def emit_port_wires(self): named_signals = {name: signal for signal, name in self.module.signal_names.items()}