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hdl._nir: Remove ArrayMux, use AssignmentList instead.
1 parent fc9369b commit ea56137

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4 files changed

+62
-69
lines changed

4 files changed

+62
-69
lines changed

amaranth/back/rtlil.py

Lines changed: 1 addition & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -446,7 +446,7 @@ def emit_cell_wires(self):
446446
continue # No outputs.
447447
elif isinstance(cell, _nir.AssignmentList):
448448
width = len(cell.default)
449-
elif isinstance(cell, (_nir.Operator, _nir.Part, _nir.ArrayMux, _nir.AnyValue,
449+
elif isinstance(cell, (_nir.Operator, _nir.Part, _nir.AnyValue,
450450
_nir.SyncReadPort, _nir.AsyncReadPort)):
451451
width = cell.width
452452
elif isinstance(cell, _nir.FlipFlop):
@@ -738,21 +738,6 @@ def emit_part(self, cell_idx, cell):
738738
"Y_WIDTH": cell.width,
739739
}, src=_src(cell.src_loc))
740740

741-
def emit_array_mux(self, cell_idx, cell):
742-
wire = self.cell_wires[cell_idx]
743-
with self.builder.process(src=_src(cell.src_loc)) as proc:
744-
with proc.case() as root_case:
745-
with root_case.switch(self.sigspec(cell.index)) as switch:
746-
for index, elem in enumerate(cell.elems):
747-
if len(cell.index) > 0:
748-
pattern = "{:0{}b}".format(index, len(cell.index))
749-
else:
750-
pattern = ""
751-
with switch.case(pattern) as case:
752-
case.assign(wire, self.sigspec(elem))
753-
with switch.case() as case:
754-
case.assign(wire, self.sigspec(cell.elems[0]))
755-
756741
def emit_flip_flop(self, cell_idx, cell):
757742
ports = {
758743
"D": self.sigspec(cell.data),
@@ -944,8 +929,6 @@ def emit_cells(self):
944929
self.emit_operator(cell_idx, cell)
945930
elif isinstance(cell, _nir.Part):
946931
self.emit_part(cell_idx, cell)
947-
elif isinstance(cell, _nir.ArrayMux):
948-
self.emit_array_mux(cell_idx, cell)
949932
elif isinstance(cell, _nir.FlipFlop):
950933
self.emit_flip_flop(cell_idx, cell)
951934
elif isinstance(cell, _nir.IOBuffer):

amaranth/hdl/_ir.py

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -842,7 +842,21 @@ def emit_rhs(self, module_idx: int, value: _ast.Value) -> Tuple[_nir.Value, bool
842842
width = max(width, len(elem))
843843
elems = tuple(self.extend(elem, elem_signed, width) for elem, elem_signed in elems)
844844
index, _signed = self.emit_rhs(module_idx, value.index)
845-
cell = _nir.ArrayMux(module_idx, width=width, elems=elems, index=index,
845+
conds = []
846+
for case_index in range(len(elems)):
847+
cell = _nir.Matches(module_idx, value=index,
848+
patterns=(f"{case_index:0{len(index)}b}",),
849+
src_loc=value.src_loc)
850+
subcond, = self.netlist.add_value_cell(1, cell)
851+
conds.append(subcond)
852+
conds = _nir.Value(conds)
853+
cell = _nir.PriorityMatch(module_idx, en=_nir.Net.from_const(1), inputs=conds, src_loc=value.src_loc)
854+
conds = self.netlist.add_value_cell(len(conds), cell)
855+
assignments = [
856+
_nir.Assignment(cond=cond, start=0, value=elem, src_loc=value.src_loc)
857+
for cond, elem in zip(conds, elems)
858+
]
859+
cell = _nir.AssignmentList(module_idx, default=elems[0], assignments=assignments,
846860
src_loc=value.src_loc)
847861
result = self.netlist.add_value_cell(width, cell)
848862
elif isinstance(value, _ast.Cat):

amaranth/hdl/_nir.py

Lines changed: 1 addition & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
# Netlist core
99
"Net", "Value", "Netlist", "ModuleNetFlow", "Module", "Cell", "Top",
1010
# Computation cells
11-
"Operator", "Part", "ArrayMux",
11+
"Operator", "Part",
1212
# Decision tree cells
1313
"Matches", "PriorityMatch", "Assignment", "AssignmentList",
1414
# Storage cells
@@ -501,42 +501,6 @@ def __repr__(self):
501501
return f"(part {self.value} {value_signed} {self.offset} {self.width} {self.stride})"
502502

503503

504-
class ArrayMux(Cell):
505-
"""Corresponds to ``hdl.ast.ArrayProxy``. All values in the ``elems`` array need to have
506-
the same width as the output.
507-
508-
Attributes
509-
----------
510-
511-
width: int (width of output and all inputs)
512-
elems: tuple of Value
513-
index: Value
514-
"""
515-
def __init__(self, module_idx, *, width, elems, index, src_loc):
516-
super().__init__(module_idx, src_loc=src_loc)
517-
518-
self.width = width
519-
self.elems = tuple(Value(val) for val in elems)
520-
self.index = Value(index)
521-
522-
def input_nets(self):
523-
nets = set(self.index)
524-
for value in self.elems:
525-
nets |= set(value)
526-
return nets
527-
528-
def output_nets(self, self_idx: int):
529-
return {Net.from_cell(self_idx, bit) for bit in range(self.width)}
530-
531-
def resolve_nets(self, netlist: Netlist):
532-
self.elems = tuple(netlist.resolve_value(val) for val in self.elems)
533-
self.index = netlist.resolve_value(self.index)
534-
535-
def __repr__(self):
536-
elems = " ".join(repr(elem) for elem in self.elems)
537-
return f"(array_mux {self.width} {self.index} ({elems}))"
538-
539-
540504
class Matches(Cell):
541505
"""A combinatorial cell performing a comparison like ``Value.matches``
542506
(or, equivalently, a case condition).

tests/test_hdl_ir.py

Lines changed: 45 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2901,10 +2901,10 @@ def test_arrayproxy(self):
29012901
(input 'i8sb' 0.34:42)
29022902
(input 'i8sc' 0.42:50)
29032903
(input 'i4' 0.50:54)
2904-
(output 'o1' (cat 1.0:8 2'd0))
2905-
(output 'o2' (cat 2.0:9 2.8))
2906-
(output 'o3' (cat 3.0:8 3.7 3.7))
2907-
(output 'o4' (cat 4.0:8 4.7 4.7))
2904+
(output 'o1' (cat 5.0:8 2'd0))
2905+
(output 'o2' (cat 10.0:9 10.8))
2906+
(output 'o3' (cat 15.0:8 15.7 15.7))
2907+
(output 'o4' (cat 20.0:8 20.7 20.7))
29082908
)
29092909
(cell 0 0 (top
29102910
(input 'i8ua' 2:10)
@@ -2914,15 +2914,47 @@ def test_arrayproxy(self):
29142914
(input 'i8sb' 34:42)
29152915
(input 'i8sc' 42:50)
29162916
(input 'i4' 50:54)
2917-
(output 'o1' (cat 1.0:8 2'd0))
2918-
(output 'o2' (cat 2.0:9 2.8))
2919-
(output 'o3' (cat 3.0:8 3.7 3.7))
2920-
(output 'o4' (cat 4.0:8 4.7 4.7))
2921-
))
2922-
(cell 1 0 (array_mux 8 0.50:54 (0.2:10 0.10:18 0.18:26)))
2923-
(cell 2 0 (array_mux 9 0.50:54 ((cat 0.2:10 1'd0) (cat 0.10:18 1'd0) (cat 0.42:50 0.49))))
2924-
(cell 3 0 (array_mux 8 0.50:54 (0.26:34 0.34:42 0.42:50)))
2925-
(cell 4 0 (array_mux 8 0.50:54 (0.26:34 0.34:42 (cat 0.50:54 4'd0))))
2917+
(output 'o1' (cat 5.0:8 2'd0))
2918+
(output 'o2' (cat 10.0:9 10.8))
2919+
(output 'o3' (cat 15.0:8 15.7 15.7))
2920+
(output 'o4' (cat 20.0:8 20.7 20.7))
2921+
))
2922+
(cell 1 0 (matches 0.50:54 0000))
2923+
(cell 2 0 (matches 0.50:54 0001))
2924+
(cell 3 0 (matches 0.50:54 0010))
2925+
(cell 4 0 (priority_match 1 (cat 1.0 2.0 3.0)))
2926+
(cell 5 0 (assignment_list 0.2:10
2927+
(4.0 0:8 0.2:10)
2928+
(4.1 0:8 0.10:18)
2929+
(4.2 0:8 0.18:26)
2930+
))
2931+
(cell 6 0 (matches 0.50:54 0000))
2932+
(cell 7 0 (matches 0.50:54 0001))
2933+
(cell 8 0 (matches 0.50:54 0010))
2934+
(cell 9 0 (priority_match 1 (cat 6.0 7.0 8.0)))
2935+
(cell 10 0 (assignment_list (cat 0.2:10 1'd0)
2936+
(9.0 0:9 (cat 0.2:10 1'd0))
2937+
(9.1 0:9 (cat 0.10:18 1'd0))
2938+
(9.2 0:9 (cat 0.42:50 0.49))
2939+
))
2940+
(cell 11 0 (matches 0.50:54 0000))
2941+
(cell 12 0 (matches 0.50:54 0001))
2942+
(cell 13 0 (matches 0.50:54 0010))
2943+
(cell 14 0 (priority_match 1 (cat 11.0 12.0 13.0)))
2944+
(cell 15 0 (assignment_list 0.26:34
2945+
(14.0 0:8 0.26:34)
2946+
(14.1 0:8 0.34:42)
2947+
(14.2 0:8 0.42:50)
2948+
))
2949+
(cell 16 0 (matches 0.50:54 0000))
2950+
(cell 17 0 (matches 0.50:54 0001))
2951+
(cell 18 0 (matches 0.50:54 0010))
2952+
(cell 19 0 (priority_match 1 (cat 16.0 17.0 18.0)))
2953+
(cell 20 0 (assignment_list 0.26:34
2954+
(19.0 0:8 0.26:34)
2955+
(19.1 0:8 0.34:42)
2956+
(19.2 0:8 (cat 0.50:54 4'd0))
2957+
))
29262958
)
29272959
""")
29282960

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