Skip to content

Commit 16f187e

Browse files
wanda-phiwhitequark
wanda-phi
authored and
whitequark
committed
test_build_res: fix naming, squash warnings.
1 parent eebffc1 commit 16f187e

File tree

1 file changed

+64
-35
lines changed

1 file changed

+64
-35
lines changed

‎tests/test_build_res.py

Lines changed: 64 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,8 @@ def test_request_basic(self):
6363
self.assertEqual(user_led.width, 1)
6464
self.assertEqual(user_led.dir, "o")
6565

66-
pins = list(self.cm.iter_pins())
67-
(pin, port, buffer), = pins
66+
(pin, port, buffer), = self.cm.iter_pins()
67+
buffer._MustUse__silence = True
6868

6969
self.assertIs(pin, user_led)
7070
self.assertEqual(port.io.name, "user_led_0__io")
@@ -77,12 +77,18 @@ def test_request_with_dir(self):
7777
i2c = self.cm.request("i2c", 0, dir={"sda": "o"})
7878
self.assertIsInstance(flipped(i2c.sda), Pin)
7979
self.assertEqual(i2c.sda.dir, "o")
80+
((_, _, scl_buffer), (_, _, sda_buffer)) = self.cm.iter_pins()
81+
scl_buffer._MustUse__silence = True
82+
sda_buffer._MustUse__silence = True
8083

8184
def test_request_tristate(self):
8285
i2c = self.cm.request("i2c", 0)
8386
self.assertEqual(i2c.sda.dir, "io")
8487

85-
((scl_pin, scl_port, _), (sda_pin, sda_port, _)) = self.cm.iter_pins()
88+
((scl_pin, scl_port, scl_buffer), (sda_pin, sda_port, sda_buffer)) = self.cm.iter_pins()
89+
scl_buffer._MustUse__silence = True
90+
sda_buffer._MustUse__silence = True
91+
8692
self.assertIs(scl_pin, i2c.scl)
8793
self.assertIs(sda_pin, i2c.sda)
8894
self.assertEqual(scl_port.io.name, "i2c_0__scl__io")
@@ -96,7 +102,9 @@ def test_request_diffpairs(self):
96102
self.assertEqual(clk100.dir, "i")
97103
self.assertEqual(clk100.width, 1)
98104

99-
(clk100_pin, clk100_port, _), = self.cm.iter_pins()
105+
(clk100_pin, clk100_port, buffer), = self.cm.iter_pins()
106+
buffer._MustUse__silence = True
107+
100108
self.assertIs(clk100_pin, clk100)
101109
self.assertEqual(clk100_port.p.name, "clk100_0__p")
102110
self.assertEqual(clk100_port.p.width, clk100.width)
@@ -115,9 +123,11 @@ def test_request_inverted(self):
115123
cs = self.cm.request("cs")
116124
clk = self.cm.request("clk")
117125
(
118-
(cs_pin, cs_port, _),
119-
(clk_pin, clk_port, _),
126+
(cs_pin, cs_port, cs_buffer),
127+
(clk_pin, clk_port, clk_buffer),
120128
) = self.cm.iter_pins()
129+
cs_buffer._MustUse__silence = True
130+
clk_buffer._MustUse__silence = True
121131

122132
self.assertIs(cs_pin, cs)
123133
self.assertEqual(cs_port.invert, (True,))
@@ -138,27 +148,31 @@ def test_request_raw_diffpairs(self):
138148
def test_request_via_connector(self):
139149
self.cm.add_resources([
140150
Resource("spi", 0,
141-
Subsignal("ss", Pins("1", conn=("pmod", 0))),
151+
Subsignal("cs", Pins("1", conn=("pmod", 0))),
142152
Subsignal("clk", Pins("2", conn=("pmod", 0))),
143-
Subsignal("miso", Pins("3", conn=("pmod", 0))),
144-
Subsignal("mosi", Pins("4", conn=("pmod", 0))),
153+
Subsignal("cipo", Pins("3", conn=("pmod", 0))),
154+
Subsignal("copi", Pins("4", conn=("pmod", 0))),
145155
)
146156
])
147157
spi0 = self.cm.request("spi", 0)
148158
(
149-
(ss_pin, ss_port, _),
150-
(clk_pin, clk_port, _),
151-
(miso_pin, miso_port, _),
152-
(mosi_pin, mosi_port, _),
159+
(cs_pin, cs_port, cs_buffer),
160+
(clk_pin, clk_port, clk_buffer),
161+
(cipo_pin, cipo_port, cipo_buffer),
162+
(copi_pin, copi_port, copi_buffer),
153163
) = self.cm.iter_pins()
154-
self.assertIs(ss_pin, spi0.ss)
164+
cs_buffer._MustUse__silence = True
165+
clk_buffer._MustUse__silence = True
166+
cipo_buffer._MustUse__silence = True
167+
copi_buffer._MustUse__silence = True
168+
self.assertIs(cs_pin, spi0.cs)
155169
self.assertIs(clk_pin, spi0.clk)
156-
self.assertIs(miso_pin, spi0.miso)
157-
self.assertIs(mosi_pin, spi0.mosi)
158-
self.assertEqual(ss_port.io.metadata[0].name, "B0")
170+
self.assertIs(cipo_pin, spi0.cipo)
171+
self.assertIs(copi_pin, spi0.copi)
172+
self.assertEqual(cs_port.io.metadata[0].name, "B0")
159173
self.assertEqual(clk_port.io.metadata[0].name, "B1")
160-
self.assertEqual(miso_port.io.metadata[0].name, "B2")
161-
self.assertEqual(mosi_port.io.metadata[0].name, "B3")
174+
self.assertEqual(cipo_port.io.metadata[0].name, "B2")
175+
self.assertEqual(copi_port.io.metadata[0].name, "B3")
162176

163177
def test_request_via_nested_connector(self):
164178
new_connectors = [
@@ -167,35 +181,41 @@ def test_request_via_nested_connector(self):
167181
self.cm.add_connectors(new_connectors)
168182
self.cm.add_resources([
169183
Resource("spi", 0,
170-
Subsignal("ss", Pins("1", conn=("pmod_extension", 0))),
184+
Subsignal("cs", Pins("1", conn=("pmod_extension", 0))),
171185
Subsignal("clk", Pins("2", conn=("pmod_extension", 0))),
172-
Subsignal("miso", Pins("3", conn=("pmod_extension", 0))),
173-
Subsignal("mosi", Pins("4", conn=("pmod_extension", 0))),
186+
Subsignal("cipo", Pins("3", conn=("pmod_extension", 0))),
187+
Subsignal("copi", Pins("4", conn=("pmod_extension", 0))),
174188
)
175189
])
176190
spi0 = self.cm.request("spi", 0)
177191
(
178-
(ss_pin, ss_port, _),
179-
(clk_pin, clk_port, _),
180-
(miso_pin, miso_port, _),
181-
(mosi_pin, mosi_port, _),
192+
(cs_pin, cs_port, cs_buffer),
193+
(clk_pin, clk_port, clk_buffer),
194+
(cipo_pin, cipo_port, cipo_buffer),
195+
(copi_pin, copi_port, copi_buffer),
182196
) = self.cm.iter_pins()
183-
self.assertIs(ss_pin, spi0.ss)
197+
cs_buffer._MustUse__silence = True
198+
clk_buffer._MustUse__silence = True
199+
cipo_buffer._MustUse__silence = True
200+
copi_buffer._MustUse__silence = True
201+
self.assertIs(cs_pin, spi0.cs)
184202
self.assertIs(clk_pin, spi0.clk)
185-
self.assertIs(miso_pin, spi0.miso)
186-
self.assertIs(mosi_pin, spi0.mosi)
187-
self.assertEqual(ss_port.io.metadata[0].name, "B0")
203+
self.assertIs(cipo_pin, spi0.cipo)
204+
self.assertIs(copi_pin, spi0.copi)
205+
self.assertEqual(cs_port.io.metadata[0].name, "B0")
188206
self.assertEqual(clk_port.io.metadata[0].name, "B1")
189-
self.assertEqual(miso_port.io.metadata[0].name, "B2")
190-
self.assertEqual(mosi_port.io.metadata[0].name, "B3")
207+
self.assertEqual(cipo_port.io.metadata[0].name, "B2")
208+
self.assertEqual(copi_port.io.metadata[0].name, "B3")
191209

192210
def test_request_clock(self):
193211
clk100 = self.cm.request("clk100", 0)
194212
clk50 = self.cm.request("clk50", 0, dir="i")
195213
(
196-
(clk100_pin, clk100_port, _),
197-
(clk50_pin, clk50_port, _),
214+
(clk100_pin, clk100_port, clk100_buffer),
215+
(clk50_pin, clk50_port, clk50_buffer),
198216
) = self.cm.iter_pins()
217+
clk100_buffer._MustUse__silence = True
218+
clk50_buffer._MustUse__silence = True
199219
self.assertEqual(list(self.cm.iter_clock_constraints()), [
200220
(clk100.i, clk100_port.p, 100e6),
201221
(clk50.i, clk50_port.io, 50e6)
@@ -207,6 +227,9 @@ def test_add_clock(self):
207227
self.assertEqual(list(self.cm.iter_clock_constraints()), [
208228
(i2c.scl.o, None, 100e3)
209229
])
230+
((_, _, scl_buffer), (_, _, sda_buffer)) = self.cm.iter_pins()
231+
scl_buffer._MustUse__silence = True
232+
sda_buffer._MustUse__silence = True
210233

211234
def test_wrong_resources(self):
212235
with self.assertRaisesRegex(TypeError, r"^Object 'wrong' is not a Resource$"):
@@ -244,16 +267,20 @@ def test_wrong_clock_frequency(self):
244267
self.cm.add_clock_constraint(Signal(), None)
245268

246269
def test_wrong_request_duplicate(self):
270+
self.cm.request("user_led", 0)
271+
(pin, port, buffer), = self.cm.iter_pins()
272+
buffer._MustUse__silence = True
247273
with self.assertRaisesRegex(ResourceError,
248274
r"^Resource user_led#0 has already been requested$"):
249275
self.cm.request("user_led", 0)
250-
self.cm.request("user_led", 0)
251276

252277
def test_wrong_request_duplicate_physical(self):
253278
self.cm.add_resources([
254279
Resource("clk20", 0, Pins("H1", dir="i")),
255280
])
256281
self.cm.request("clk100", 0)
282+
(pin, port, buffer), = self.cm.iter_pins()
283+
buffer._MustUse__silence = True
257284
with self.assertRaisesRegex(ResourceError,
258285
(r"^Resource component clk20_0 uses physical pin H1, but it is already "
259286
r"used by resource component clk100_0 that was requested earlier$")):
@@ -293,6 +320,8 @@ def test_wrong_request_with_xdr_dict(self):
293320

294321
def test_wrong_clock_constraint_twice(self):
295322
clk100 = self.cm.request("clk100")
323+
(pin, port, buffer), = self.cm.iter_pins()
324+
buffer._MustUse__silence = True
296325
with self.assertRaisesRegex(ValueError,
297326
(r"^Cannot add clock constraint on \(sig clk100_0__i\), which is already "
298327
r"constrained to 100000000\.0 Hz$")):

0 commit comments

Comments
 (0)