Creating package of Ethernet design, Vivado crashes

[Aftab2798]

Hi Alex,

I have created a block design of your project for the ZCU102 and it is working fine. However, when I try to create a package of that design, Vivado crashes.
I have developed a custom RTL IP block (fpga_v1_0) which includes several RTL modules and an instance of the UltraScale FPGAs Transceivers Wizard v1.7. The design integrates correctly in a block design and works in simulation, but when I attempt to package this custom IP for reuse in other projects, Vivado crashes during the packaging step.
To isolate the issue, I removed components one by one. The crash only occurs when the UltraScale FPGAs Transceivers Wizard instance is included inside the IP. Without it, the packaging process completes successfully.

Vivado version: 2023.1

UltraScale FPGAs Transceivers Wizard: v1.7

[alexforencich]

This is really more a question for Xilinx and why their software is crashing. But, perhaps you can try switching the GT core out of out-of-context mode so it isn't handled as a separate core. I have had to do this with the CMAC so I could exclude the placement constraints by disabling the constraints file.