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support for MSP430 and PIC18 microcontrollers
1 parent 0d34eed commit f478894

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+2150
-11
lines changed

‎amoco/arch/core.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -286,7 +286,7 @@ def buildspec(self):
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go = +1
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chklen = True
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if direction=='<': # format goes from high bits to low bits
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fmt = reversed(fmt)
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fmt = list(reversed(fmt))
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go = -1
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if size == '*':
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self.size = 0

‎amoco/arch/msp430/__init__.py

Whitespace-only changes.

‎amoco/arch/msp430/asm.py

Lines changed: 189 additions & 0 deletions
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#!/usr/bin/env python
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# This code is part of Amoco
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# Copyright (C) 2013 Axel Tillequin (bdcht3@gmail.com)
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# published under GPLv2 license
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from .env import *
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from amoco.cas.utils import *
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def autoinc(i,fmap):
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rr = i.misc['autoinc']
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sz = 2 if i.BW else 1
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if rr is not None: fmap[rr] = fmap(rr+sz)
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# Ref: MSP430x1xx Family Users's Guide (Rev. F)
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#------------------------------------------------------------------------------
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def i_MOV(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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fmap[dst] = fmap(src)
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autoinc(i,fmap)
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def i_ADD(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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result,carry,overflow = AddWithCarry(fmap(src),fmap(dst))
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fmap[dst] = result
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fmap[cf] = carry
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fmap[zf] = (result==0)
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fmap[nf] = result[dst.size-1:dst.size]
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fmap[vf] = overflow
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autoinc(i,fmap)
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def i_ADDC(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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result,carry,overflow = AddWithCarry(fmap(src),fmap(dst),fmap(cf))
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fmap[dst] = result
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fmap[cf] = carry
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fmap[zf] = (result==0)
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fmap[nf] = result[dst.size-1:dst.size]
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fmap[vf] = overflow
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autoinc(i,fmap)
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def i_SUB(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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result,carry,overflow = AddWithCarry(fmap(src),fmap(dst))
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fmap[dst] = result
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fmap[cf] = carry
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fmap[zf] = (result==0)
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fmap[nf] = result[dst.size-1:dst.size]
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fmap[vf] = overflow
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autoinc(i,fmap)
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def i_CMP(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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result,carry,overflow = AddWithCarry(fmap(src),fmap(dst))
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fmap[cf] = carry
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fmap[zf] = (result==0)
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fmap[nf] = result[dst.size-1:dst.size]
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fmap[vf] = overflow
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autoinc(i,fmap)
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def i_SUBC(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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result,carry,overflow = AddWithCarry(fmap(src),fmap(dst),fmap(cf))
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fmap[dst] = result
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fmap[cf] = carry
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fmap[zf] = (result==0)
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fmap[nf] = result[dst.size-1:dst.size]
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fmap[vf] = overflow
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autoinc(i,fmap)
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def i_AND(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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result = fmap(src&dst)
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fmap[dst] = result
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fmap[nf] = result[dst.size-1:dst.size]
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fmap[zf] = (result==0)
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fmap[cf] = ~fmap(zf)
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fmap[vf] = bit0
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autoinc(i,fmap)
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def i_XOR(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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fmap[dst] = fmap(src^dst)
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fmap[nf] = result[dst.size-1:dst.size]
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fmap[zf] = (result==0)
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fmap[cf] = ~fmap(zf)
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fmap[vf] = bit0
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autoinc(i,fmap)
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def i_BIC(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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fmap[dst] = fmap((~src)&dst)
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autoinc(i,fmap)
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def i_BIS(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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fmap[dst] = fmap(src|dst)
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autoinc(i,fmap)
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def i_BIT(i,fmap):
113+
fmap[pc] = fmap[pc]+i.length
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src,dst = i.operands
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result = fmap(src|dst)
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fmap[nf] = result[dst.size-1:dst.size]
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fmap[zf] = (result==0)
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fmap[cf] = ~fmap(zf)
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fmap[vf] = bit0
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autoinc(i,fmap)
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def i_CALL(i,fmap):
123+
fmap[pc] = fmap[pc]+i.length
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dst = i.operands[0]
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tmp = fmap(dst)
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fmap[sp] = fmap(sp-2)
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fmap[mem(sp,pc.size)] = fmap(pc)
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fmap[pc] = tmp
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autoinc(i,fmap)
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#def i_RETI(i,fmap):
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# dst = i.operands[0]
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#def i_DADD(i,fmap):
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# NotImplemented
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def i_RRC(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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dst = i.operands[0]
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res,carry = RORWithCarry(fmap(dst),1,fmap(cf))
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fmap[dst] = res
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fmap[cf] = carry
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fmap[nf] = res[dst.size-1:dst.size]
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fmap[zf] = (res==0)
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fmap[vf] = bit0
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def i_SWPB(i,fmap):
148+
fmap[pc] = fmap[pc]+i.length
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dst = i.operands[0]
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res = composer([fmap(dst[8:16]),fmap(dst[0:8])])
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fmap[dst] = res
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def i_RRA(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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dst = i.operands[0]
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res,carry = RORWithCarry(fmap(dst),1,fmap(dst[dst.size-1:dst.size]))
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fmap[dst] = res
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fmap[cf] = carry
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fmap[nf] = res[dst.size-1:dst.size]
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fmap[zf] = (res==0)
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fmap[vf] = bit0
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def i_SXT(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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dst = i.operands[0]
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res = fmap(dst[0:8]).signextend(16)
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fmap[dst] = res
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fmap[nf] = res[dst.size-1:dst.size]
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fmap[zf] = (res==0)
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fmap[cf] = ~fmap(zf)
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fmap[vf] = bit0
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def i_PUSH(i,fmap):
174+
src = i.operands[0]
175+
fmap[sp] = fmap(sp-src.size)
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fmap[mem(sp,src.size)] = fmap(src)
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autoinc(i,fmap)
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def i_JMP(i,fmap):
180+
offset = i.operands[0]*2
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fmap[pc] = fmap(pc+i.length+offset)
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autoinc(i,fmap)
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def i_Jcc(i,fmap):
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fmap[pc] = fmap[pc]+i.length
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offset = i.operands[0]*2
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cond = fmap(COND[i.cond][1])
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fmap[pc] = tst(cond,fmap(pc+offset),fmap(pc))
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autoinc(i,fmap)

‎amoco/arch/msp430/cpu.py

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@@ -0,0 +1,17 @@
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from amoco.arch.msp430.asm import *
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# expose "microarchitecture" (instructions semantics)
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uarch = dict(filter(lambda kv:kv[0].startswith('i_'),locals().iteritems()))
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#import specifications:
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from amoco.arch.core import instruction, disassembler
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instruction.set_uarch(uarch)
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from amoco.arch.msp430.formats import MSP430_synthetic
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instruction.set_formatter(MSP430_synthetic)
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#define disassembler:
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from amoco.arch.msp430 import spec_msp430
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disassemble = disassembler([spec_msp430])
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disassemble.maxlen = 6

‎amoco/arch/msp430/env.py

Lines changed: 44 additions & 0 deletions
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#!/usr/bin/env python
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# This code is part of Amoco
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# Copyright (C) 2014 Axel Tillequin (bdcht3@gmail.com)
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# published under GPLv2 license
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# import expressions:
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from amoco.cas.expressions import *
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#reference documentation:
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# MSP430x1xx User's Guide, Texas Instruments, 2006.
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#registers :
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#-----------
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# general registers:
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R = [reg('r%d'%x,16) for x in range(16)]
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pc = R[0]
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sp = R[1]
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sr = R[2]
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cg1 = sr
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cg2 = R[3]
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pc.ref = 'pc'
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sp.ref = 'sp'
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sr.ref = 'sr'
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cf = slc(sr,0,1,ref='cf')
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zf = slc(sr,1,1,ref='zf')
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nf = slc(sr,2,1,ref='nf')
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vf = slc(sr,8,1,ref='vf')
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COND = {
35+
0b000: ('NE/NZ',zf==bit0),
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0b001: ('EQ/Z',zf==bit1),
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0b010: ('NC/LO',cf==bit0),
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0b011: ('C/HS',cf==bit1),
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0b100: ('N',nf==bit1),
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0b101: ('GE',vf==nf),
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0b110: ('L',vf!=nf),
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0b111: ('',bit1),
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}
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‎amoco/arch/msp430/formats.py

Lines changed: 89 additions & 0 deletions
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from .env import *
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from amoco.arch.core import Formatter
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def mnemo(i,pad=8):
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m = i.mnemonic
6+
if i.BW: m+='.B'
7+
return m.lower().ljust(pad)
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def mnemo_cond(i):
10+
m = mnemo(i,pad=0).replace('jcc','j')
11+
s = COND[i.cond][0].split('/')[0]
12+
return (m+s).lower().ljust(8)
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def ops(i):
15+
s = []
16+
for o in i.operands:
17+
if o._is_slc:
18+
assert i.BW
19+
o = o.x
20+
if o._is_reg:
21+
s.append(str(o))
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elif o._is_cst:
23+
s.append('#%s'%o)
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else:
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assert o._is_mem
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a = o.a.base
27+
if a._is_reg:
28+
if i.misc['autoinc'] is a:
29+
s.append('@%s+'%a)
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else:
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s.append('@%s'%a)
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elif a._is_cst:
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s.append('&%s'%a)
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else:
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assert a._is_eqn
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l,r = a.l,a.r
37+
if l==pc and i.address:
38+
s.append('*%s'%(i.address+r))
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else:
40+
s.append('%s(%s)'%(r,l))
41+
return ', '.join(s)
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MSP430_full_formats = {
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'msp430_doubleop' : [mnemo, ops],
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'msp430_singleop' : [mnemo, ops],
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'msp430_jumps' : [mnemo_cond, ops],
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}
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MSP430_full = Formatter(MSP430_full_formats)
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def MSP430_synthetic(null,i):
52+
s = MSP430_full(i)
53+
if i.mnemonic == 'ADDC' and i.operands[0]==0:
54+
return s.replace('addc','adc').replace('#0x0,','')
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if i.mnemonic == 'DADD' and i.operands[0]==0:
56+
return s.replace('dadd','dadc').replace('#0x0,','')
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if i.mnemonic == 'CMP' and i.operands[0]==0:
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return s.replace('cmp','tst').replace('#0x0,','')
59+
if i.mnemonic == 'MOV':
60+
if i.operands[1] is pc:
61+
return s.replace('mov','br').replace(',pc','')
62+
elif i.operands[0]==0:
63+
return s.replace('mov','clr').replace('#0x0,','')
64+
elif i.misc['autoinc'] is sp:
65+
if i.operands[1] is pc: return 'ret'
66+
return s.replace('mov','pop').replace('@sp+,','')
67+
if i.mnemonic == 'BIC':
68+
if i.operands[1] is sr:
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if i.operands[0]==1: return 'clrc'
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if i.operands[0]==4: return 'clrn'
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if i.operands[0]==2: return 'clrz'
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if i.operands[0]==8: return 'dint'
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if i.mnemonic == 'BIS':
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if i.operands[1] is sr:
75+
if i.operands[0]==1: return 'setc'
76+
if i.operands[0]==4: return 'setn'
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if i.operands[0]==2: return 'setz'
78+
if i.operands[0]==8: return 'eint'
79+
if i.mnemonic == 'SUB' and i.operands[0]==1:
80+
return s.replace('sub','dec').replace('#0x1,','')
81+
if i.mnemonic == 'SUB' and i.operands[0]==2:
82+
return s.replace('sub','decd').replace('#0x2,','')
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if i.mnemonic == 'ADD' and i.operands[0]==1:
84+
return s.replace('add','inc').replace('#0x1,','')
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if i.mnemonic == 'ADD' and i.operands[0]==2:
86+
return s.replace('add','incd').replace('#0x2,','')
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if i.mnemonic == 'XOR' and i.operands[0].signextend(16).value==-1:
88+
return 'inv '+ops(i).split(',')[-1].strip()
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return s

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