From d8c4cc936c218d5a526aa444075367cdd1af5ed5 Mon Sep 17 00:00:00 2001
From: curryfromuestc <curryyang8@gmail.com>
Date: Sun, 19 May 2024 21:00:03 +0800
Subject: [PATCH 1/2] Add Chinese comment

---
 src/alu.sv | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/alu.sv b/src/alu.sv
index 4d23614..ddb98fa 100644
--- a/src/alu.sv
+++ b/src/alu.sv
@@ -6,6 +6,7 @@
 // > In this minimal implementation, the ALU supports the 4 basic arithmetic operations
 // > Each thread in each core has it's own ALU
 // > ADD, SUB, MUL, DIV instructions are all executed here
+//本模块定义了ALU的行为，包括对寄存器值的计算，支持4种基本算术运算，每个核心的每个线程都有自己的ALU，ADD，SUB，MUL，DIV指令都在这里执行
 module alu (
     input wire clk,
     input wire reset,
@@ -20,7 +21,7 @@ module alu (
     input reg [7:0] rt,
     output wire [7:0] alu_out
 );
-    localparam ADD = 2'b00,
+    localparam ADD = 2'b00, //定义了4种基本算术运算对应的编码，且采用了本地参数
         SUB = 2'b01,
         MUL = 2'b10,
         DIV = 2'b11;
@@ -36,9 +37,9 @@ module alu (
             if (core_state == 3'b101) begin 
                 if (decoded_alu_output_mux == 1) begin 
                     // Set values to compare with NZP register in alu_out[2:0]
-                    alu_out_reg <= {5'b0, (rs - rt > 0), (rs - rt == 0), (rs - rt < 0)};
+                    alu_out_reg <= {5'b0, (rs - rt > 0), (rs - rt == 0), (rs - rt < 0)}; //alu_out的低3位分别存储了NZP寄存器的值
                 end else begin 
-                    // Execute the specified arithmetic instruction
+                    // Execute the specified arithmetic instruction //执行指定的算术指令
                     case (decoded_alu_arithmetic_mux)
                         ADD: begin 
                             alu_out_reg <= rs + rt;

From cedd8ad696ca9e02a711c451dc98e010a3861c1a Mon Sep 17 00:00:00 2001
From: curryfromuestc <curryyang8@gmail.com>
Date: Fri, 24 May 2024 21:53:10 +0800
Subject: [PATCH 2/2] =?UTF-8?q?=E6=B7=BB=E5=8A=A0lsu=E7=9A=84=E4=B8=AD?=
 =?UTF-8?q?=E6=96=87=E6=B3=A8=E9=87=8A?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/lsu.sv | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/lsu.sv b/src/lsu.sv
index 77b716b..2649477 100644
--- a/src/lsu.sv
+++ b/src/lsu.sv
@@ -5,11 +5,12 @@
 // > Handles asynchronous memory load and store operations and waits for response
 // > Each thread in each core has it's own LSU
 // > LDR, STR instructions are executed here
+//LDR是加载指令和内存地址，STR是存储指令和内存地址
 module lsu (
     input wire clk,
     input wire reset,
     input wire enable, // If current block has less threads then block size, some LSUs will be inactive
-
+//enable信号可以控制吃模块是否开启，在进程数小于块大小时，一些LSUs将处于非活动状态
     // State
     input reg [2:0] core_state,
 
@@ -38,7 +39,7 @@ module lsu (
     localparam IDLE = 2'b00, REQUESTING = 2'b01, WAITING = 2'b10, DONE = 2'b11;
 
     always @(posedge clk) begin
-        if (reset) begin
+        if (reset) begin//复位逻辑
             lsu_state <= IDLE;
             lsu_out <= 0;
             mem_read_valid <= 0;